JPH0467876U - - Google Patents
Info
- Publication number
- JPH0467876U JPH0467876U JP11089090U JP11089090U JPH0467876U JP H0467876 U JPH0467876 U JP H0467876U JP 11089090 U JP11089090 U JP 11089090U JP 11089090 U JP11089090 U JP 11089090U JP H0467876 U JPH0467876 U JP H0467876U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clamp
- voltage
- video signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 claims 1
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Picture Signal Circuits (AREA)
- Television Receiver Circuits (AREA)
Description
第１図は本考案の一実施例を示す自動輝度制限
回路のブロツク図、第２図は同第１図の各部動作
を示すタイミング図である。
３は可変ゲイン増幅器、８はペデスタルクラン
プ回路、１２はインタフエース集積回路である。
FIG. 1 is a block diagram of an automatic brightness limiting circuit showing one embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of each part of FIG. 3 is a variable gain amplifier, 8 is a pedestal clamp circuit, and 12 is an interface integrated circuit.
Claims (1)
いて、映像信号の自動コントラスト制限回路と、
同自動コントラスト制限回路出力をペデスタルク
ランプするクランプ回路と、同クランプ回路出力
をペデスタルクランプパルス期間のみ遮断し所定
のバイアス電圧に切り換えるスイツチ回路と、同
スイツチ回路出力映像信号を結合コンデンサを介
して入力するインタフエース集積回路と、受像管
アノード電流が制限値以上に増加すると下がり始
める自動輝度制限電圧の分圧回路とを有し、同分
圧回路電圧を前記クランプ回路のクランプ電圧と
してなる自動輝度制限回路。 In a video signal processing circuit such as a color television receiver, an automatic contrast limiting circuit for a video signal,
A clamp circuit that pedestally clamps the output of the automatic contrast limiting circuit, a switch circuit that cuts off the output of the clamp circuit only during the pedestal clamp pulse period and switches to a predetermined bias voltage, and inputs the video signal output from the switch circuit via a coupling capacitor. An automatic brightness limiting circuit comprising an interface integrated circuit and a voltage dividing circuit for an automatic brightness limiting voltage that starts to decrease when the picture tube anode current increases beyond a limit value, and uses the voltage dividing circuit as the clamp voltage of the clamp circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11089090U JPH0467876U (en) | 1990-10-23 | 1990-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11089090U JPH0467876U (en) | 1990-10-23 | 1990-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467876U true JPH0467876U (en) | 1992-06-16 |
Family
ID=31858293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11089090U Pending JPH0467876U (en) | 1990-10-23 | 1990-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467876U (en) |
-
1990
- 1990-10-23 JP JP11089090U patent/JPH0467876U/ja active Pending
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