JPH0468523A - Heat treatment method - Google Patents
Heat treatment methodInfo
- Publication number
- JPH0468523A JPH0468523A JP18201590A JP18201590A JPH0468523A JP H0468523 A JPH0468523 A JP H0468523A JP 18201590 A JP18201590 A JP 18201590A JP 18201590 A JP18201590 A JP 18201590A JP H0468523 A JPH0468523 A JP H0468523A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- si3n4
- heat treatment
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010438 heat treatment Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 title claims description 15
- 239000000203 mixture Substances 0.000 claims abstract description 3
- 230000001681 protective effect Effects 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 15
- 238000000137 annealing Methods 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 abstract description 3
- 239000006185 dispersion Substances 0.000 abstract 2
- 229910020286 SiOxNy Inorganic materials 0.000 abstract 1
- 229910020776 SixNy Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 11
- 239000012535 impurity Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 239000000470 constituent Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は例えば、ＩＩＬＶ族半導体単結晶基板にイオン
注入した後に熱処理して導電層を形成するに際し、電気
的特性の再現性に優れた導電層が得られる熱処理方法に
関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides a conductive layer with excellent reproducibility of electrical characteristics when, for example, a conductive layer is formed by heat treatment after ion implantation into a IILV group semiconductor single crystal substrate. It relates to a heat treatment method by which a layer is obtained.
（従来の技術）
近年、ＩＩＬＶ族化合物半導体材料を用いた高速デジタ
ル集積回路の開発が進むにつれて、熱処理技術の重要性
がますます高まってきている。すなわち、ＧａＡｓＭＥ
Ｓ型ＦＥＴやペテロ接合バイポーラ・トランジスタ、ペ
テロ接合電界効果トランジスタなどの異種接合デバイス
の製造プロセスにおいて、コンタクト抵抗の低減を目的
としたイオン注入が行われており、これらのデバイスの
製造においては、均一性、再現性の優れた熱処理方法が
要求されている。現在も一般に行なわれているのは、素
子表面にアニール保護膜を堆積させて行なう保護膜アニ
ールである。保護膜をつけることの理由は、高温でのア
ニール時に結晶の表面からの構成元素の分解および構成
元素の外部拡散を防止することである。アニール保護膜
に要求される特徴としては、上に挙げた目的にかなうこ
との他に、■構成元素の、膜中への拡散に対して十分な
障壁となる、■半導体に対する密着性がよく、膜にピン
ホールやクラックが発生しない、■保護膜と半導体界面
が熱的に安定で、反応したり、膜から構成元素が半導体
中に拡散混入しない、■アニール時に半導体界面に大き
なひずみを導入しない、■アニール後の除去が容易であ
る、等が挙げられる（［半導体イオン注入技術］蒲生健
次編著産業図書１９８６年刊）。以上の観点を考慮して
、現在最も広く用いられているのがＳｉＯ２とＳｉ３Ｎ
４である。このうち、ＳｉＯを保護膜としてＧａＡｓを
アニールした場合、ＧａＡｓから８１０２中にＧａの外
部拡散がおこり結晶中にＧａ空孔が導入されるため、素
子特性の均一性が劣化する傾向があることが知られてお
り、例えばアブライドフィジックスレターズ１７巻３３
２頁１９７０年に記載されている（Ｊ、 Ｇｙｕｌａｉ
、 Ｊ、 Ｗ、 Ｍａｙｅｒ ａｎｄ １． Ｖ。(Prior Art) In recent years, as the development of high-speed digital integrated circuits using IILV group compound semiconductor materials progresses, the importance of heat treatment technology is increasing. That is, GaAsME
In the manufacturing process of heterojunction devices such as S-type FETs, petrojunction bipolar transistors, and petrojunction field effect transistors, ion implantation is performed to reduce contact resistance. There is a need for a heat treatment method with excellent performance and reproducibility. What is commonly performed today is protective film annealing, which is performed by depositing an annealed protective film on the surface of the element. The reason for providing the protective film is to prevent the decomposition of the constituent elements from the surface of the crystal and the outward diffusion of the constituent elements during annealing at high temperatures. In addition to fulfilling the above-mentioned purposes, the characteristics required of an annealed protective film include: (1) providing a sufficient barrier to the diffusion of constituent elements into the film; (2) having good adhesion to the semiconductor; No pinholes or cracks occur in the film. ■ The interface between the protective film and the semiconductor is thermally stable and does not react or the constituent elements from the film diffuse into the semiconductor. ■ No large strain is introduced to the semiconductor interface during annealing. , ■ It is easy to remove after annealing ([Semiconductor ion implantation technology] edited by Kenji Gamo, Sangyo Tosho, published in 1986). Considering the above points, the two most widely used at present are SiO2 and Si3N.
It is 4. Among these, when GaAs is annealed using SiO as a protective film, external diffusion of Ga occurs from GaAs into 8102 and Ga vacancies are introduced into the crystal, which tends to deteriorate the uniformity of device characteristics. For example, Abride Physics Letters Volume 17, Volume 33.
2 pages 1970 (J, Gyulai
, J., W., Mayer and 1. V.
Ｍｉｃｈｅｌｌ： Ａｐｐｌ、 Ｐｈｙｓ、 Ｌｅｔｔ
、 １７（１９７０）３３２）。一方、Ｓｉ３Ｎ４を用
いた場合は、このような問題は発生せず、均一な素子特
性が得られる。このようにＳｉ３Ｎ４はＳｉＯと比べて
Ｇａ拡散に対する抑止効果が高く、ＧａＡｓを熱処理す
る時の保護膜として優れている。Michel: Appl, Phys, Lett
, 17 (1970) 332). On the other hand, when Si3N4 is used, such problems do not occur and uniform device characteristics can be obtained. As described above, Si3N4 has a higher inhibitory effect on Ga diffusion than SiO, and is excellent as a protective film when heat-treating GaAs.
（発明が解決しようとする課題）
しかし、Ｓｉ３Ｎ４を保護膜として用いて場合、アニー
ル時に膜と結晶の間に１０９ｄｙｎ／Ｃｍ程度におよぶ
大きな応力が発生し、膜の剥離やクラックが発生しやす
い傾向があることが知られている。また、このような応
力は注入不純物の拡散や基板結晶中の不純物の再分布を
助長したりすることも知られている。応力発生の原因は
、５１３Ｎ４の熱膨張係数がＧａＡｓと異なることによ
る。通常Ｓｉ３Ｎ４はプラズマＣＶＤ法等により４００
°Ｃ付近で成長させるのに対し熱処理は通常８００°Ｃ
以上の高温で行なわれる。この温度差による熱膨張率が
ＱａＡｓとＳｉ３Ｎ４とで大きく異なるため、上記のよ
うに応力が発生すると考えられる。一方、ＳｉＯに関し
ては、応力発生による問題の発生は報告されていない。(Problem to be solved by the invention) However, when Si3N4 is used as a protective film, a large stress of about 109 dyn/Cm is generated between the film and the crystal during annealing, and the film tends to peel off and crack. It is known that there is. It is also known that such stress promotes the diffusion of implanted impurities and the redistribution of impurities in the substrate crystal. The cause of the stress is that the coefficient of thermal expansion of 513N4 is different from that of GaAs. Normally Si3N4 is made by plasma CVD method etc.
Growth is done at around °C, whereas heat treatment is usually at 800 °C.
It is carried out at higher temperatures than above. It is thought that stress is generated as described above because the thermal expansion coefficients due to this temperature difference are significantly different between QaAs and Si3N4. On the other hand, with respect to SiO, no problems have been reported due to stress generation.
このことは、高温でのＳｉＯの熱膨張係数がＧａＡｓの
それに近いことを示している。This indicates that the thermal expansion coefficient of SiO at high temperatures is close to that of GaAs.
本発明は以上述べたような保護膜熱処理方法に関する従
来の問題点を解決するためになされたものであり、熱膨
張係数の違いによりアニール時に半導体結晶と保護膜の
間に発生する応力を緩和し、膜の剥離、クラックの発生
、注入不純物の拡散や基板結晶中の不純物の再分布の助
長といった問題点を解決し、均一性、再現性の優れたイ
オン注入活性層を形成しうる熱処理方法を提供するもの
である。The present invention was made in order to solve the conventional problems related to the above-mentioned protective film heat treatment method, and it alleviates the stress generated between the semiconductor crystal and the protective film during annealing due to the difference in thermal expansion coefficient. We developed a heat treatment method that can form an ion-implanted active layer with excellent uniformity and reproducibility by solving problems such as film peeling, cracking, diffusion of implanted impurities, and promotion of redistribution of impurities in the substrate crystal. This is what we provide.
（課題を解決するための手段）
本発明の熱処理方法は、イオン注入したＩＩＩ−Ｖ族化
合物半導体基板を熱処理するにあたり、Ｓｉ３Ｎ４膜の
上に５１３Ｎ４から８１０２までなめらかに変化する組
成を持ったＳｉＮグレーデッド層があり、最上部にｙ
８１０２層が堆積された構造の保護膜を用いることを特
徴とする。(Means for Solving the Problems) In the heat treatment method of the present invention, when an ion-implanted III-V compound semiconductor substrate is heat treated, a SiN gray film having a composition that smoothly changes from 513N4 to 8102 is deposited on the Si3N4 film. It is characterized by using a protective film having a structure including a dead layer and a Y8102 layer deposited on top.
（作用）
本発明の熱処理方法は、従来の５１３Ｎ４を用いた場合
の問題点であった、熱膨張係数の違いによりアニール時
に半導体結晶と保護膜の間に発生する応力を緩和し、膜
の剥離、クラックの発生、注入不純物の拡散や基板結晶
中の不純物の再分布の助長等を解決し、均一性、再現性
の優れたイオン注入活性層を形成しうる熱処理方法を提
供するものである。上記の構造のアニール保護膜を用い
てイオン注入ＧａＡｓ基板を熱処理することにより、従
来の５１３Ｎ４を用いた場合の問題点であった膜の剥離
、クラックの発生、注入不純物の拡散や基板結晶中の不
純物の再分布の助長等を防ぎ、均一性に優れた素子特性
が得られた実験事実に基づくものである。上記の構造の
アニール保護膜を用いてイオン注入ＧａＡｓ基板を熱処
理することにより熱処理中の膜の剥離、クラックの発生
、注入不純物の拡散や基板結晶中の不純物の再分布の助
長等を抑制できる理由としては、Ｓｉ３Ｎ４と比べて熱
膨張係数がＧａＡｓのそれに近いＳｉＯ２をＳｉ３Ｎ４
の上に重ねた構造のアニール保護膜を用いることにより
、ＧａＡｓと保護膜との熱膨張係数の違いによる界面で
の応力の発生が緩和されることによるものと考えられる
。(Function) The heat treatment method of the present invention alleviates the stress that occurs between the semiconductor crystal and the protective film during annealing due to the difference in thermal expansion coefficient, which was a problem when using conventional 513N4, and the film peels off. The present invention provides a heat treatment method that can form an ion-implanted active layer with excellent uniformity and reproducibility by solving problems such as the occurrence of cracks, the diffusion of implanted impurities, and the promotion of redistribution of impurities in the substrate crystal. By heat-treating the ion-implanted GaAs substrate using the annealing protective film with the above structure, it is possible to eliminate the problems of film peeling, cracking, and diffusion of implanted impurities in the substrate crystal, which were problems when using conventional 513N4. This is based on experimental evidence that the promotion of impurity redistribution was prevented and device characteristics with excellent uniformity were obtained. The reason why heat-treating an ion-implanted GaAs substrate using an annealing protective film with the above structure can suppress film peeling, cracking, diffusion of implanted impurities, and promotion of redistribution of impurities in the substrate crystal during heat treatment. As for Si3N4, SiO2 has a thermal expansion coefficient close to that of GaAs compared to Si3N4.
This is thought to be due to the fact that by using the annealed protective film layered over the GaAs layer, the stress generated at the interface due to the difference in thermal expansion coefficient between GaAs and the protective film is alleviated.
（実施例） 以下に本発明の実施例について詳細に説明する。(Example) Examples of the present invention will be described in detail below.
第１図は、本発明のアニール保護膜の構造を示す図であ
る。ＧａＡｓ基板１上に形成されたＳｉ３Ｎ４膜層２（
厚さ４００オングストローム）の上に、ＳｉＮグレーｙ
トッド層３（１０００オングストローム）があり、最上
部に８１０２層４（３０００オングストローム）が堆積
されている。FIG. 1 is a diagram showing the structure of the annealing protective film of the present invention. Si3N4 film layer 2 (
On top of the SiN gray tod layer 3 (1000 angstroms) is deposited on top the 8102 layer 4 (3000 angstroms).
以上に示した構造の膜をアニール保護膜に用いて、次の
ような実験を行った。面方位＜１００＞ＬＥＣ（Ｌｉｑ
ｕｉｄ Ｅｎｃａｐｓｕｌａｔｅｄ Ｃｚｏｃｈａｒａ
ｌｓｋｉ）法アンドープ半絶縁性ＧａＡｓ基板１に注入
エネルギー１００ＫｅＶでＳｉ＋をＬＸ １０１３ｃｍ
−２室温で注入しイオン注入層５を形成した後、第１図
に示した構造のアニール保護膜を用いて９００°Ｃで１
０秒間処理した。この結果得られた活性層シート抵抗の
ばらつきはσＲｓ＝５Ω／口でありＳｉ３Ｎ４を保護膜
に用いた場合のばらつきσＲｓ＝１５Ω／口と比べて大
幅に改善されている。The following experiment was conducted using the film having the structure shown above as an annealing protective film. Surface orientation <100> LEC (Liq
uid Encapsulated Czochara
lski) method Si+ is implanted into an undoped semi-insulating GaAs substrate 1 at a depth of LX 1013 cm with an energy of 100 KeV.
-2 After forming the ion implantation layer 5 at room temperature, the annealing protective film having the structure shown in FIG.
Processed for 0 seconds. The resulting variation in the sheet resistance of the active layer is σRs=5Ω/hole, which is significantly improved compared to the variation σRs=15Ω/hole when Si3N4 is used as the protective film.
本発明の方法は、任意の膜の厚さの組合せが選択できる
。また、上に述べたイオン注入条件のみでなく、他の注
入条件に対して有効であり、アニール条件についても同
様である。さらに本発明の方法は、ＧａＡｓの他にも、
熱処理を必要とし、高温での熱膨張係数がＳｉＯと近い
値を有するあらゆる種類の物質に対して適用することが
できる。In the method of the present invention, any combination of film thicknesses can be selected. Further, this is effective not only for the above-mentioned ion implantation conditions but also for other implantation conditions, and the same applies to annealing conditions. Furthermore, in addition to GaAs, the method of the present invention can also be applied to
It can be applied to all kinds of materials that require heat treatment and have a coefficient of thermal expansion at high temperatures close to that of SiO.
以上のことから、本発明の方法を用いることにより、熱
処理されたイオン注入活性層の電気的均一性が大幅に向
上することが確認された。From the above, it was confirmed that by using the method of the present invention, the electrical uniformity of the heat-treated ion-implanted active layer was significantly improved.
（発明の効果）
以上説明したように、本発明の方法によれば、例えばＩ
ＩＩ ＋ Ｖ族化合物半導体の熱処理により得られた基
板面内の均一性を従来よりも大幅に向上させることが出
来、従って高速集積回路の歩留りを大幅に改善すること
が出来る。(Effects of the Invention) As explained above, according to the method of the present invention, for example, I
The in-plane uniformity of the substrate obtained by heat treatment of the II+V group compound semiconductor can be significantly improved compared to the conventional method, and therefore the yield of high-speed integrated circuits can be significantly improved.
第１図は本発明の一実施例を概略的に示す構造図である
。
１−ＧａＡｓ基板、２・・・Ｓｉ３Ｎ４層、３・・・Ｓ
ｉＸＮ、グレーデッド層、４・・・８１０２層、５・・
・イオン注入層FIG. 1 is a structural diagram schematically showing an embodiment of the present invention. 1-GaAs substrate, 2...Si3N4 layer, 3...S
iXN, graded layer, 4...8102 layer, 5...
・Ion implantation layer
Claims (1)
にＳｉ＿３Ｎ＿４からＳｉＯ＿２までなめらかに変化す
る組成を持ったＳｉＯ＿ｘＮ＿ｙグレーデッド層があり
、最上部にＳｉＯ＿２層が堆積された構造の保護膜を用
いることを特徴とする熱処理方法。In the semiconductor heat treatment process, a protective film having a structure in which there is an SiO_xN_y graded layer with a composition that changes smoothly from Si_3N_4 to SiO_2 on the Si_3N_4 film, and a SiO_2 layer is deposited on top, is used. Heat treatment method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18201590A JPH0468523A (en) | 1990-07-10 | 1990-07-10 | Heat treatment method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18201590A JPH0468523A (en) | 1990-07-10 | 1990-07-10 | Heat treatment method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0468523A true JPH0468523A (en) | 1992-03-04 |
Family
ID=16110846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18201590A Pending JPH0468523A (en) | 1990-07-10 | 1990-07-10 | Heat treatment method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0468523A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7052918B2 (en) | 1999-10-19 | 2006-05-30 | Samsung Electronics Co., Ltd. | Multi-layer film for thin film structure, capacitor using the same and fabrication method thereof |
-
1990
- 1990-07-10 JP JP18201590A patent/JPH0468523A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7052918B2 (en) | 1999-10-19 | 2006-05-30 | Samsung Electronics Co., Ltd. | Multi-layer film for thin film structure, capacitor using the same and fabrication method thereof |
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