JPH0468557U - - Google Patents
Info
- Publication number
- JPH0468557U JPH0468557U JP11240290U JP11240290U JPH0468557U JP H0468557 U JPH0468557 U JP H0468557U JP 11240290 U JP11240290 U JP 11240290U JP 11240290 U JP11240290 U JP 11240290U JP H0468557 U JPH0468557 U JP H0468557U
- Authority
- JP
- Japan
- Prior art keywords
- package
- short
- terminal
- lsi
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009434 installation Methods 0.000 claims 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案のＬＳＩパツケージおよびパツ
ケージ搭載用の印刷配線板の一実施例を示す斜視
図、第２図は第１図の結合後の一例を示す断面図
である。
１０……パツケージ、１１……短端子、１２…
…配設用端子、２０……印刷配線板、２１……案
内穴。
FIG. 1 is a perspective view showing an embodiment of the LSI package of the present invention and a printed wiring board for mounting the package, and FIG. 2 is a cross-sectional view showing an example of the LSI package in FIG. 1 after being combined. 10...Package, 11...Short terminal, 12...
... terminal for arrangement, 20 ... printed wiring board, 21 ... guide hole.
Claims (1)
つバツトリードＰＧＡ（ピングリツドアレー）形
のＬＳＩ（大規模集積回路）パツケージにおいて
、前記短端子格子状平面にほぼ垂直をなし、先端
までが前記短端子より長い長さで所定の位置に前
記短端子に並設する少くとも二つの配設用端子を
有することを特徴とするＬＳＩパツケージ。 ２ 請求項１記載のＬＳＩパツケージが有する配
設用端子を挿入するパツケージ案内穴を所定位置
に有することを特徴とするパツケージ搭載用印刷
配線板。[Claims for Utility Model Registration] 1. In a butt-lead PGA (pin grid array) type LSI (Large Scale Integrated Circuit) package having a large number of short terminals arranged in a lattice shape, the short terminals are arranged in a lattice-like plane. An LSI package comprising at least two installation terminals that are vertical and have a length up to the tip that is longer than the short terminal and are arranged in parallel with the short terminal at predetermined positions. 2. A printed wiring board for mounting a package, characterized in that it has a package guide hole at a predetermined position into which a terminal for arrangement included in the LSI package according to claim 1 is inserted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11240290U JPH0468557U (en) | 1990-10-25 | 1990-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11240290U JPH0468557U (en) | 1990-10-25 | 1990-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0468557U true JPH0468557U (en) | 1992-06-17 |
Family
ID=31859908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11240290U Pending JPH0468557U (en) | 1990-10-25 | 1990-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0468557U (en) |
-
1990
- 1990-10-25 JP JP11240290U patent/JPH0468557U/ja active Pending
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