JPH046866A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH046866A JPH046866A JP2108018A JP10801890A JPH046866A JP H046866 A JPH046866 A JP H046866A JP 2108018 A JP2108018 A JP 2108018A JP 10801890 A JP10801890 A JP 10801890A JP H046866 A JPH046866 A JP H046866A
- Authority
- JP
- Japan
- Prior art keywords
- film
- diffused layer
- ferroelectric film
- capacitor
- ferroelectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、強誘電体を用いた、メモリ、中でも特に、容
量に電荷をためることにより信号を記憶する、ダイナミ
ックRAMの構造に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a structure of a memory using a ferroelectric material, and in particular, a dynamic RAM that stores signals by storing charge in a capacitor. .
C発明の概要〕
本発明は、強誘電体膜を用いた、メモリの構造において
、強誘電体膜が高濃度拡散層上に形成され、強誘電体膜
と高濃度拡散層との間の少なくとも一部分に、酸化Si
か、窒化Si膜が形成されていることにより、比誘電率
の大きい、かつ、絶縁耐圧の高いキャパシタを集積化さ
せたメモリを得るようにしたものである。C. Summary of the Invention] The present invention provides a memory structure using a ferroelectric film, in which the ferroelectric film is formed on a high concentration diffusion layer, and at least one layer between the ferroelectric film and the high concentration diffusion layer. Partly, Si oxide
Alternatively, by forming a Si nitride film, a memory in which a capacitor having a high dielectric constant and a high dielectric strength voltage is integrated can be obtained.
従来の半導体メモリDRAMとしては、高濃度拡散層上
に5i02をキャパシタの絶縁膜としてもちいていた。In a conventional semiconductor memory DRAM, 5i02 was used as a capacitor insulating film on a heavily doped diffusion layer.
しかし、近年、微細化が進み、素子面積を小さくする努
力がされている。微細化を進めると、キャパシタを形成
する面積も小さく成り、電荷を貯えるに必要な容量を確
保出来なくなってきた。そこで、例えば、キャパシタの
面積を大きく取るために、トレンチ型のキャパシタや、
キャパシタをトランジスタの上部にまで集積化させたス
タック型のキャパシタなとのように、構造によりキャパ
シタの面積を大きくする試みや、SiNや、TaO2な
どのように比誘電率が大きい材料を用いてキャパシタの
容量を増やす試みなどがされてきた。However, in recent years, miniaturization has progressed and efforts have been made to reduce the element area. As miniaturization progresses, the area on which a capacitor is formed also becomes smaller, making it difficult to secure the capacity necessary to store charge. Therefore, for example, in order to increase the area of the capacitor, trench-type capacitors,
Attempts are being made to increase the area of the capacitor by changing its structure, such as stacked capacitors in which the capacitor is integrated up to the top of the transistor, and by using materials with high dielectric constants such as SiN and TaO2. Attempts have been made to increase the capacity of
しかし、これらのいずれの方法も十分な容量を得るまで
にはいたっていない。そこで本発明はこのような課題を
解決するもので、その目的とする所は、比誘電率が桁違
いに大きい強誘電体膜を用いて、容量の大きいキャパシ
タを持ち、かつ、絶縁耐圧の十分なりRAMなどの半導
体メモリを提供する所にある。However, none of these methods has reached the point where sufficient capacity can be obtained. The present invention is intended to solve these problems, and its purpose is to create a capacitor with a large capacitance and sufficient dielectric strength by using a ferroelectric film with an order of magnitude higher relative dielectric constant. It is located in a place that provides semiconductor memory such as RAM.
本発明の半導体装置は、強誘電体膜を高濃度拡散層上に
形成し、かつ、強誘電体膜と高濃度拡散層との間の少な
くとも一部分に、酸化Siか窒化Si膜が形成したこと
を特徴とする。In the semiconductor device of the present invention, a ferroelectric film is formed on a high concentration diffusion layer, and a Si oxide or Si nitride film is formed at least in a portion between the ferroelectric film and the high concentration diffusion layer. It is characterized by
第1図は、本発明の半導体装置の一実施例に於ける主要
断面図である。以下、第1図に従い、本発明の半導体装
置を説明する。ここでは説明の都合上Si基板を用い、
Nチャンネルトランジスタを用いた例につき説明する。FIG. 1 is a main sectional view of an embodiment of the semiconductor device of the present invention. The semiconductor device of the present invention will be described below with reference to FIG. For convenience of explanation, a Si substrate is used here.
An example using an N-channel transistor will be explained.
(101)はP型Si基板であり、例えば200hm、
cmの比抵抗のウェハを用いる。(102)は素子分離
用の絶縁膜であり、例えば、従来技術であるLOCO5
法により酸化膜を600OA形成する。(103)はソ
ースとなるN型拡散層であり、例えばリンを80KeV
5E15cm−2イオン注入することにより形成する。(101) is a P-type Si substrate, for example, 200hm,
A wafer with a resistivity of cm is used. (102) is an insulating film for element isolation, for example, the conventional technology LOCO5
An oxide film with a thickness of 600 OA is formed by the method. (103) is an N-type diffusion layer that becomes a source, and for example, phosphorus is heated to 80KeV.
It is formed by implanting 5E15 cm-2 ions.
(104)はドレインとなるN型拡散層であり、(10
3)と同時に形成する。(105)はゲート電極であり
、例えばリンでドープされたポリSiを用いる。(10
6)が本発明の構成要素となる、強誘電体膜であるPb
TiO3、PZT (PbZr03、PbTiO3、P
LZT (La、PbZrO3、PbTi03)であり
、例えばスパッタ法などにより100OA形成する。(
107)は強誘電体膜の電極となる例えばポリSiであ
り、CVD法により1500Aの厚みで形成する。(1
08)は(107)の電極とドレインへの配線電極であ
る(109)を分離する絶縁膜であり、こコでハ、CV
D法ニヨリ5i02膜を4000A形成する。そして(
110)か本発明のもう一つの構成要素となる酸化Si
膜であり、例えば、酸素を含む雰囲気中てのランプアニ
ールにより、15Aの均一な酸化Si膜を(106)の
強誘電体膜の形成前に形成する。(104) is an N-type diffusion layer that becomes a drain, and (10
3) Form at the same time. (105) is a gate electrode, for example, poly-Si doped with phosphorus is used. (10
6) is a Pb which is a ferroelectric film which is a component of the present invention.
TiO3, PZT (PbZr03, PbTiO3, P
It is LZT (La, PbZrO3, PbTi03), and is formed with a thickness of 100 OA by, for example, a sputtering method. (
Reference numeral 107) is made of poly-Si, for example, which becomes the electrode of the ferroelectric film, and is formed to a thickness of 1500 Å by the CVD method. (1
08) is an insulating film that separates the electrode (107) from (109), which is the wiring electrode to the drain.
A 5i02 film of 4000A is formed using the D method. and(
110) or Si oxide which is another component of the present invention
For example, a uniform Si oxide film of 15 A is formed by lamp annealing in an atmosphere containing oxygen before forming the ferroelectric film (106).
さて、第1図のような構造のキャパシタの容量について
考えてみると、強誘電体膜の比誘電率は、仮に強誘電体
膜としてPZTを用いた場合、約1000であるため、
1/C=1/C(S i 02)+1/C(PZT)と
なり、前述した膜厚で計算すると、5i02換算て14
Aのキャパシタが形成出来る。この換算膜厚は、(11
0)の酸化Si膜の膜厚とほぼかわりはないが、(11
0)の様に、15Aの膜厚の酸化Si膜のみを直接キャ
パシタの絶縁膜とした場合には、絶縁耐圧が数ボルトし
かなく、素子は構成出来なかった。それに対し、第1図
のように酸化Si膜と強誘電体膜を積層化させることに
より、絶縁耐圧としては20Vの値か得られ、絶縁耐圧
としても十分てあり、かつ容量としても、非常に単位面
積当たりの容量値か大きいキャパシタか得られた。Now, if we consider the capacitance of a capacitor with the structure shown in Figure 1, the relative dielectric constant of the ferroelectric film is approximately 1000 if PZT is used as the ferroelectric film, so it is 1/C. = 1/C (S i 02) + 1/C (PZT), and when calculated using the film thickness mentioned above, it is 14 in terms of 5i02.
Capacitor A can be formed. This equivalent film thickness is (11
The thickness is almost the same as that of the Si oxide film in (0), but the thickness is (11
0), when only a 15A thick Si oxide film was directly used as the insulating film of the capacitor, the dielectric strength was only a few volts, and the device could not be constructed. On the other hand, by laminating a Si oxide film and a ferroelectric film as shown in Figure 1, a dielectric strength voltage of 20V can be obtained, which is sufficient as a dielectric strength voltage and has a very high capacity. The capacitance value per unit area or the large capacitor was obtained.
以上の説明においては、強誘電体膜を積層する絶縁膜と
して、酸化S1膜を用いた場合について説明したか、窒
化Si膜や、酸化Si膜と窒化Si膜の積層膜を用いて
も良いことはいうまでもない。In the above explanation, the case where an oxidized S1 film is used as the insulating film on which the ferroelectric film is laminated has been explained, but it is also possible to use a Si nitride film or a laminated film of a Si oxide film and a Si nitride film. Needless to say.
本発明のように、強誘電体膜か、高濃度拡散層上に形成
され、かつ、強誘電体膜と高濃度拡散層との間の少なく
とも一部分に、酸化Si、または窒化Si膜が形成した
ため、絶縁耐圧か高く、かつ容量としても、非常に単位
面積当たりの容量値が大きいキャパシタが集積化出来る
という効果を有する。As in the present invention, the Si oxide or Si nitride film is formed on the ferroelectric film or the high concentration diffusion layer, and at least in a portion between the ferroelectric film and the high concentration diffusion layer. This has the effect that a capacitor having a high dielectric strength voltage and a very large capacitance per unit area can be integrated.
第1図は本発明の主要断面図である。 ・81基板 ・素子分離絶縁膜 ・ソース拡散層 ・ドレイン拡散層 ・ゲート電極 ・強誘電体膜 ・電極 ・層間絶縁膜 ・配線電極 ・キャパシタ絶縁膜 出願人 セイコーエプソン株式会社 FIG. 1 is a main sectional view of the present invention. ・81 board ・Element isolation insulating film ・Source diffusion layer ・Drain diffusion layer ・Gate electrode ・Ferroelectric film ·electrode ・Interlayer insulation film ・Wiring electrode ・Capacitor insulation film Applicant: Seiko Epson Corporation
Claims (1)
基板上に、集積された半導体装置において、前記強誘電
体膜が高濃度拡散層上に形成され、かつ、前記強誘電体
膜と前記高濃度拡散層との間の少なくとも一部分に、酸
化Siか、窒化Si膜のいずれかの絶縁膜が形成されて
ることを特徴とする半導体装置。(1) In a semiconductor device in which a ferroelectric film is integrated on the same semiconductor substrate on which active elements are formed, the ferroelectric film is formed on a high concentration diffusion layer, and the ferroelectric film 1. A semiconductor device characterized in that an insulating film of either Si oxide or Si nitride film is formed at least in a portion between the layer and the high concentration diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108018A JPH046866A (en) | 1990-04-24 | 1990-04-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108018A JPH046866A (en) | 1990-04-24 | 1990-04-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH046866A true JPH046866A (en) | 1992-01-10 |
Family
ID=14473896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2108018A Pending JPH046866A (en) | 1990-04-24 | 1990-04-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046866A (en) |
-
1990
- 1990-04-24 JP JP2108018A patent/JPH046866A/en active Pending
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