JPH0468837B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color solid-state imaging device that uses a solid-state imaging plate to obtain color image signals.

Charge transfer devices used as color solid-state imaging devices
Although it has been considered to use one, two, or three CCDs, the present invention particularly relates to a single-chip imaging system and device that uses one CCD.

Conventionally, in a single-chip solid-state imaging device using a solid-state imaging device such as a CCD, color separation is performed by overlapping a color filter array and an imaging cell one-on-one. The color filter used in this single-chip solid-state imaging device
In order to save the number of CCD imaging cells, the array generally uses a color filter in which formulas are arranged in a mosaic pattern as shown in FIG. 1. The color filter array shown in FIG. 1 is called a Bayer array, and numerals 1, 2, and 3 indicate color filter elements that pass red R, blue B, and green G component lights, respectively. Even if the overlapping between the color filter elements 1, 2, and 3 and the CCD imaging cells is perfect, signal leakage occurs between each CCD cell, resulting in color mixture and color separation becoming uncertain. There is a problem.

In particular, in frame transfer type CCDs, their structure,
A considerable amount of color mixing occurs. The relationship between them will be explained using a diagram.

Figure 2 a and b are 4-phase drive frame transfer type
The figure shows a vertical cross-sectional view and the probability of charge capture when imaging is performed by accumulating signals under two of the four electrodes of a CCD.

Further, FIGS. 3a and 3b show a horizontal cross-sectional view and the probability of charge capture, respectively.

In FIGS. 2 and 3, reference numeral 4 denotes a transfer electrode, which is driven in four phases, so that a set of φ1, φ2, φ3, and φ4 constitutes an electrode for one cell. Reference numeral 5 indicates an insulating layer, 6 indicates a silicon substrate, 7 indicates a potential shape, and 8 and 9 indicate a potential well and barrier formed by a voltage applied to the transmission electrode 4, respectively.

10 is a channel stopper. In this state, the channel stopper 10 and the transfer electrode φ
A potential well 8 for signal storage, that is, a light receiving cell (hereinafter, the potential well will be referred to as a light receiving cell) is formed in a portion surrounded by the potential barrier 9 below 3 and φ4.

Figures 2b and 3b respectively show the probability distributions g(x) and h(y ) is shown.

Looking at these probability distributions g(x) and h(y), the photoelectric sensitivity of the adjacent light receiving cells 8 is
and the potential below the transfer electrodes 4, φ3, φ4.
They overlap at the barrier portion 9, and therefore, even if the color filter elements 1, 2, and 3 and the imaging cells are completely overlapped, color mixture will occur between adjacent cells.

However, in the case of a two-dimensional CCD, since the channel stopper section 10 can be shielded from light in the horizontal direction, color mixture in the horizontal direction can be eliminated.
However, in the vertical direction, since interlaced imaging is performed, the transfer electrode section 4 cannot be shielded from light, and when combined with the mosaic color filters 1, 2, and 3 shown in FIG. Color mixture will occur. In order to look into the effects of this color mixture in terms of circuitry, a fairly complex correction circuit is required, which is why frame transfer type
The method of combining a CCD and the Bayer array color filter shown in FIG. 1 has the drawback that it cannot be a very practical method.

In order to eliminate these drawbacks, the applicant has filed a patent application
55-17968 (Japanese Patent Publication No. 1-47956), a plurality of potential wells are formed in each pixel cell, a color filter is placed in each potential well, and the signals accumulated in each potential well are added for each cell. The present invention provides a color solid-state imaging device that obtains color signals without color mixture by performing arithmetic processing on the signals of cells in adjacent rows in the vertical direction of the imaging screen after reading out the signals.

However, in general, in color solid-state imaging devices that obtain color signals by mutually processing the signals of cells in vertically adjacent rows of the imaging screen, false images are generated, especially for subjects with diagonal edges. There is a problem with the color signal being noticeable.

The present invention aims to solve such problems, and provides a color solid-state imaging device that obtains color signals by mutually processing signals of cells in vertically adjacent rows of an imaging screen. A color signal forming means is provided for forming at least a color signal for one row by adding signals of three adjacent rows in the vertical direction of the imaging screen with symmetrical weighting in the vertical direction of the imaging screen. This effectively removes false color signals that occur when color signals are formed by vertical correlation processing.

Other objects of the present invention will become clear from the following description of embodiments with reference to the drawings.

Figures 4 to 6 are the premises of the present invention, respectively.
This is a diagram showing an example of the configuration of a CCD, a color filter pattern, and an electric circuit, using the configuration of the aforementioned Japanese Patent Application No. 17968/1983 (Japanese Patent Application No. 1-47956) as an example. The four-phase drive type CCD has driver 1 as shown in Figure 4a.
By applying a DC bias voltage 12 to each of the potentials 1 and 1, a potential shape 13 is formed as shown in the figure. The shape of the bottom of the potential well can be shaped like a descending staircase in the direction of charge transfer. Potential shape 1 shown by dotted line
3' shows the state when the phase of the transfer pulse waveform giving the potential shape 13 is changed by 180°.
Even in a two-phase drive type CCD and a one-phase drive type CCD, a downward staircase-like potential shape as shown in FIG. 4a can be formed. Although the present invention is naturally applicable to those types of CCDs, a four-phase drive type CCD will be explained here.

The shape of the potential explained above is essentially the shape required when transferring charge, but
In the state where charges are accumulated, it is possible to change the shape of the potential to the state shown in FIG. 4b by applying an appropriate voltage to the transfer electrode. The probability distribution of charge trapping at this time is as shown in FIG. 4c.

This CCD is provided with color filters 15 having a color arrangement as shown in FIG. 5, which is an example of a color arrangement, in correspondence with each photosensitive element as shown in the figure. As shown in the figure, each color filter element has a potential well (in this example, φ2, φ
4, etc. are formed under the electrodes. ) respectively. In addition, as shown in the figure, in the example, the filter is extended so as to cover all the areas where potential wells cannot be formed (for example, under the electrodes φ1, φ3, etc.), but this entire area is covered with a color filter. It doesn't matter if you don't have it. For example, in the figure, the width of the border portion of the color filter may be slightly increased. However, in this embodiment, in order to improve the sensitivity of the entire image sensor, the color filter is extended so as to cover all areas without potential wells, as shown in the figure. In addition, in the embodiment, in order to make the color mixing rate of adjacent pixels by the color filter almost equal for all pixels, the border of the color filter is located exactly at the center of the electrodes φ1, φ3, etc. Even without it, the effects of the present invention can be obtained.

It is assumed that this set of filter elements is repeated in the horizontal and vertical directions.

5, 16, 17, 18, and 19 indicate color filter elements that respectively pass red R, green G, blue B, and magenta Ma component light, and 20 indicates an opaque element Opaque and a light-shielding layer in the channel stopper portion. It shows. As shown in the figure, this color filter has a plurality of color filter elements arranged in different layers in a plurality of potential wells of one cell (photosensitive pixel) consisting of electrodes φ1, φ2, φ3, and φ4. It is characterized in that one of the plurality of color filter elements arranged in each pixel has a common color. As will be described later, during the interlacing operation, the positions of the cells (photosensitive pixels) will be shifted as shown in the figure.

In FIG. 5, φ1, φ1', and φ1'' are the same electrodes, but for convenience of explanation, dart signals are attached to the electrodes in different cells.

If this color image sensor has a potential shape as shown in Figure 4b, the potential well under the 23rd φ2 electrode in the nth row corresponds to the light component that has passed through the R color filter element. At the same time, the signal charge obtained from the photosensitive element is accumulated, and at the same time, as estimated from the charge capture rate distribution shown in FIG. Charges generated by light passing through a certain G are accumulated, and this becomes a color mixture component. Now, if the amount of charge that does not include color mixing components that passes through each color filter element 15 and is accumulated in the potential well directly below it is indicated by lowercase letters such as r, g, b, ma, and opaque, color mixing The amount of charge r' accumulated in the potential well under the n-th column φ2 electrode is given by r'=r+2α·g (1), where α is the coefficient of the component/leakage amount.

Similarly, for the potential well under the φ4 electrode in the nth row, g'=α・r+g+α・b (2) For the potential well under the φ2′ electrode in the nth row, b′=2α・g+b (3) In the n-th column, the potential well under the φ4' electrode has g'=α・r+g+α・b (4) In the n+1st column 24, the potential well under the φ2 electrode has ma'=ma+2α・g (5) column, the potential well under the φ4 electrode has g'=α・ma+g (6) the n+1st column, the potential well under the φ2′ electrode has opaque′=2α・g (7) the n+1st column, the φ4′ electrode g'=α・ma+g (8) will be accumulated in the lower potential well.

The above shows the amount of charge accumulated in the potential well under each electrode in the accumulation mode, but after charge accumulation, when moving to the transfer mode for reading out the signal, the transfer pulse voltage applied to each electrode is changed. , the shape of the potential is shown in Fig. 4b from Fig. 4a.
Convert it into a descending staircase like 13'. At this time, the charge r' accumulated in the potential well under the φ2 electrode in the n-th column and the charge g' accumulated in the potential well under the φ4 electrode in the n-th column are added together, and a new charge is formed under the φ4 electrode. will be stored in one potential well. Also n+
The charge ma' accumulated in the potential well under the φ2 electrode in the 1st column and the charge g' accumulated in the potential well under the φ4 electrode in the n+1st column are added together and accumulated in the potential well under the φ4 electrode. .

Therefore, r'+g', ma'+
g' will be read out alternately and repeatedly. Similarly, from the horizontal line 22 consisting of φ1', φ2', φ3' and φ4' electrodes,
b'+g' and opaque'+g' are read out alternately and repeatedly.

During interlaced operation, 1 in Figure 4 a.
Since the transfer pulse voltage is changed so that the potential shape shown in 3 is obtained, from the horizontal line 21' consisting of the φ3, φ4, φ1' and φ2' electrodes,
2r'+g',
and ma'+g' are read out alternately.

FIG. 6 is a control block diagram showing an example of the configuration which is the premise of the present invention for generating a color signal from the output signal from the color image sensor read out in this manner.

In the figure, a signal generator 35 generates electrode drive signals φ1 to φ4.

36 is a switch circuit that receives the drive signals φ1 to φ4 of the signal generator 35 and the DC bias voltage 37.
The drive signal with the addition of . The switch circuit 36 changes its output by applying a mode signal M.

Reference numeral 26 denotes a delay line that delays the signal for one horizontal scanning period to obtain a luminance signal Y, red signal R, and blue signal B by utilizing vertical correlation. 25 is a color solid-state image sensing device which is a combination of the above-mentioned mosaic color filter and CCD, and corresponds to the one shown in FIG. Color image sensor 2
The output signal from 5 is input to the adder 27, the delay line 26, and the input terminals a and d of the switch circuit 28.
is guided by. Further, the output of the delay line 26 is led to input terminals b and e of an adder 27 and a switch circuit 28.

The signal obtained from the adder 27 is derived from the first to fourth equations in the n-th column, and now, if the signal level corresponding to each charge amount is expressed in capital letters, (R'+G' )+(B′+G′)=(1+2α)(R+2G
+
B), and in the n+1st column, from equations 5 to 8, (Ma′+G′)+(Opaque′+G′)=(1+2α)(M
a
+2G) and here Ma=R+B, so each can be used as a luminance signal Y.

Looking at the above results, the effect of color mixing is R+2G+B
It can be seen that there is no particular problem because the coefficient (1+2α) is simply applied to the luminance signal. Furthermore, since a luminance signal is obtained every clock, it is possible to obtain sufficient resolution with a relatively small number of CCD pixels in the horizontal direction.

Output terminals e and f of the switch circuit 28 are connected to input terminals a and c, respectively, for 1H period, and are connected to input terminals b and d for the next 1H period. Therefore, fH shown in the figure indicates the horizontal scanning frequency. This output terminal e is subtracted by the subtractor 29
When the output terminal f is connected to the positive side of ′)−(Opaque′+G′)=Ma signals can be obtained alternately. switch circuit 28
is operated so as to prevent the signals BR and -Ma from being inverted. At this time, all mixed color components are corrected by subtraction processing as described above, and the resulting signal becomes a signal that does not include any mixed color components.

The output of this subtracter 29 is connected to an adder 31, a 1-bit delay line 30 for delaying signals of adjacent cell components, and a subtracter 32. Also, the output of the 1-bit delay line 30 is output to the adder 3.
1 and a subtracter 32, respectively. In this way, the signal obtained at the output of the adder 31 becomes a red R signal. Also, the output of the subtracter 32 includes blue B
Signals are obtained alternately between positive and negative. This blue B signal is converted into a blue B signal by a pig duct detector 33.

Each Y, R, and B signal is passed through a low-pass filter,
The signal enters a processor 34 consisting of an r correction circuit, a matrix circuit, a color encoder circuit, etc., and an NTSC color signal is obtained as an output of this processor 34.

According to the color solid-state imaging device described above, the color mixing problem that conventionally occurred between the photosensitive pixels of the imaging device,
In particular, it is possible to solve the problem of color mixture that occurs when a mosaic-like color filter is combined with an image sensor such as a frame transfer type CCD, but under certain conditions, false color signals become noticeable. It had For example, FIG. 7 shows the same color arrangement as shown in FIG. 5, and for convenience of explanation, the outputs from each filter and potential well 3 are numbered, and the light shielding part 20 is omitted. There is.

In a certain field, the signals obtained sequentially from the scanning lines are (R11 + G21), (Ma12 + G22),
(R13 + G23), ..., and from the same scanning line, (B31 + G41), (Op32 + G42), (B33 + G43), ...
The signal of ... is from the scanning line of (R51+G61), (Ma52+G62), (R53+G63),
It becomes... As a result, when scanning the scanning line of, the R signal obtained through the circuit shown in FIG. +R13+G23-B33-G43 Rout(44)=R13+G23-B33-G43 +Ma14+G24-Op34-G44.

Further, the R signal obtained when scanning the next scanning line is as follows.

Rout (62) = -B31 - G41 + R51 + G61 - Op32 - G42 + Ma52 + G62 Rout (63) = - Op32 - G42 + Ma52 + G62 - B33 - G43 + R53 + G63 Rout (64) = -B33 - G43 + R53 + G63 - Op34 - G44 + Ma54 + G64 interlaced operation. Therefore, the R signal becomes as follows.

When scanning the scan line ′, Rout(52)=-G21-B31+G41+R51 −G22−Op32+G42+Ma52 Rout(53)=-G22-Op32+G42+Ma52 −G23−B33+G43+R53 Rout(54)=-G23-B33+G43+R53 −G24−Op34+G44+Ma54 So, when scanning the scanning line ′, Rout(72)=G41+R51−G61−B71 +G42+Ma52−G62−Op72 Rout(73)=G42+Ma52−G62−Op72 +G43+R53−G63−B73 Rout(74)=G43+R53−G63−B73 +G44+Ma54−G64−Op74 becomes.

When calculating the Rout signal from each filter output shown above, the positive and negative signs applied to the original output are as follows.

FIG. 8a shows that when scanning the scanning line of
This represents the coefficient that is added to each cell in order to calculate the output of Rout. Similarly, when an interlacing operation is performed and the scanning line ' is being scanned, the coefficients will be in the form shown in Figure 8b, and when the scanning line is being scanned, the scanning line ' will be as shown in Figure 8c. During scanning, the coefficients are of the form shown in FIG. 8d.

As is clear from the figure, when scanning the scanning line ,', the coefficients used to calculate the color signal are positive for two cells in the vertical direction and negative for two consecutive cells. On the other hand, when scanning ', the coefficients are given negative signs for two cells and positive signs for two cells. In this way, when calculating a color signal from an input signal, the coefficients applied to the output of each cell are asymmetrical in the vertical direction.
As will be described later, when an input pixel has a luminance gradient in the vertical direction of the screen, a very noticeable false color signal will be generated. Moreover, this false color signal is
The effect of the optical low-pass filter is small because it is caused by a linear gradient of brightness, and
Since it is uniform in the scanning direction, it cannot be canceled by applying an electrical low-pass filter to the obtained electrical signal.

FIG. 9 schematically shows how this false color signal appears. FIG. 9a shows an achromatic input image in which the upper left is bright and the lower right is dark. (In the figure, brightness is indicated by the amount of diagonal lines.) FIG. 9b is a diagram showing the Rout signal obtained as a result of signal processing by the circuit shown in FIG. 6.

As shown in this figure, for an achromatic input image that has a luminance distribution that is bright at the top and dark at the bottom, the color signal is obtained using the coefficients shown in Figures 8a and 8b.
Rout is obtained by subtracting the output values of B, G, in a low brightness area from the output values of G, R, Ma in a high brightness area, and in some cases it may be much larger than the original Rout signal. More than twice as many Rout signals will be obtained.

On the other hand, in the cases of Figures 8c and 8d, the component due to the luminance gradient is subtracted from the original Rout value, and there are cases where a 0 or negative Rout value is obtained. .

As a result of the process described above, the Rout output for the achromatic input image shown in Figure 9a becomes too large or too small for the original signal for every two scanning lines, as shown in Fig. 9b. As a result, irregularities occur every two scanning lines in a figure that should originally be a straight line. This false color signal occurs in a low spatial frequency region of the image and is therefore relatively easy to notice.

The above problem arises because the video signal is formed by performing vertical correlation processing using two rows of signals as described above, even though there are edges in the vertical direction.

The present invention has been made to solve these problems, and it is an object of the present invention to provide a color solid-state imaging device that does not generate false colors even when there are edges or the like in the vertical direction.

Hereinafter, the present invention will be explained in detail using FIG. 10.

The same parts as shown in FIG. 6 are given the same numbers, and only the different points will be explained. In the same figure, 38 is the IH daylay line,
It receives the output of the adder 31, delays it, and outputs it. 3
An adder 9 adds the output of the 1H delay line 38 and the output of the adder 31, and applies the signal R to the process circuit 34.

By adding such a processing circuit, the seventh
Obtained when scanning the scan lines in the figure.
The coefficients for calculating the Rout signal are shown in Figure 8a,
The average value is shown in FIG. 8c, and the shape is vertically symmetrical as shown in FIG. 11a. Further, in the next scanning line, the coefficients become as shown in FIG. 11b. As a result, Figure 9b
The uneven pattern shown in Fig. 2 will no longer occur. At this time, strictly speaking, the resolution of the Rout signal in the vertical direction decreases, but the color signal does not originally require that much resolution, and when performing this processing, the luminance signal is not affected at all. The final image quality is improved by the amount that the false color signals disappear.

In the above embodiments, only one color signal has been described, but in a general color arrangement, it is desirable to use both color signals, and this can be realized based on the above idea.

Also, as a filter of the image sensor 25, as shown in FIG.
A filter as shown in FIG. 5 is obtained by replacing the blue and red positions in the color arrangement shown in FIG. 5. In this case, it is desirable to insert a delay line into the B signal.

Furthermore, when using the filters shown in FIGS. 12b, c, d, etc., it is desirable to include a delay line in both the B and R signals.

Moreover, as a method for obtaining luminance signals and color signals from these color arrangements, methods other than the processing circuit shown in FIG. 10 that can obtain the same effect can also be considered from the above points.

Next, another embodiment according to the present invention is shown in FIG.

In the figure, a signal generator 40 generates electrode drive signals Sφ1 to Sφ4.

Reference numeral 41 designates a switch circuit that outputs the drive signals Sφ1 to Sφ4 of the signal generator 40 and the DC bias voltage 4 thereto.
The driving signal obtained by adding 2 is applied to the color image sensor 43 while being switched depending on the transfer mode and accumulation mode.
The switch circuit 41 changes its output by applying the mode signal M. Reference numeral 43 denotes a color solid-state image sensing device which is a combination of the above-mentioned mosaic color filter and CCD, and corresponds to the one shown in FIG. 4
5 is a delay line that delays the signal for one horizontal scanning period and uses vertical correlation to convert the luminance signal Y,
The purpose is to obtain a red signal R and a green signal B.
The output signal from the image sensor 43 is led to an adder 44, a delay line 45, and a subtracter 46. The output of the delay line 45 is connected to an adder 44, a delay line 47, and an amplifier 48. The output of the subtracter 46 is applied to a sign inverter 49 and switching circuits 50 and 51. Such a switching circuit is self-excited and switched for each scanning line number. The outputs of the switching circuits 50 and 51 are applied to a process circuit 54 (same configuration as 34 in FIG. 6) via low-pass filters 52 and 53,
It becomes an NTSC signal.

The operation of the above configuration will now be described.

The output from the color image sensor 43 is delayed by a delay line 45 and then added to the undelayed signal by an adder 44 to become a luminance signal input to a process circuit 54. On the other hand, the output of the delay line 45 is further input to the delay line 47, and as a result, the output of the delay line 47 is obtained as the original signal delayed by two scanning lines. As for the output of the color image sensor 43, only the signal delayed by one scanning line is amplified twice by the amplifier 48, and both the original signal, the signal delayed by one scanning line, and the signal delayed by two scanning lines are sent to the subtracter. 46. A part of the output of the subtracter 46 is sent to the sign inverter 4
9 and the switching circuit 50,5
1 is input. The switching circuits 50 and 51 are switched according to the number of horizontal element position scanning lines, and the outputs of the transition switching circuit 50 are (R+B), (R-B), (R+B), (R-B).
Since the signals of . . . are obtained sequentially, the R signal is obtained through the low-pass filter 52. On the other hand, from the switching circuit 51, (B+R), (B-R),
(B+R) . . . signals are sequentially obtained, which pass through the low-pass filter 53 to obtain the B signal.
The Y, R, and B signals obtained in this manner are input to the process circuit 54, and an NTSC signal is obtained.

Note that the low-pass filters 52 and 53 are
It may include a 1-bit delay circuit and an adder as shown in the embodiment of FIG. 10, or even if it does not include such a circuit, it may be one that sufficiently reduces high frequency components. Good.

[Brief explanation of drawings]

Figure 1 shows a mosaic color filter (Bayer array), and Figure 2a shows the vertical direction when imaging is performed by accumulating signals under two of the four electrodes of a four-phase drive type CCD. Cross-sectional view, Figure 2b is a diagram showing the probability of charge trapping, Figure 3a is a horizontal cross-sectional view similar to Figure 2, Figure 3b is a diagram showing the probability of charge trapping, Figure 4a , b, c are diagrams showing solid-state imaging elements used in the color solid-state imaging device according to the present invention,
FIG. 5 is a diagram showing a solid-state image sensor and a color filter used in the same example. FIG. 6 is a block diagram showing the signal processing circuit that is the premise of the present invention, and FIG. 7 is the color arrangement of the filter that is the premise of the present invention.
A diagram showing how each color filter is numbered,
Figures 8a, b, c, and d are diagrams showing the signs of the coefficients multiplied by the output from each potential well in order to calculate the R signal in the case of the color arrangement shown in Figure 7. Figures a and b are diagrams showing a modeled input image and color signals obtained from this input image, Figure 10 is a block diagram showing a signal processing circuit in an embodiment of the present invention, and Figures 11a and b
12A and 12B are diagrams representing the signs of coefficients multiplied by the output from each potential well in order to obtain a color signal in the embodiment of the present invention, FIGS.
FIG. 13 is a block diagram showing a signal processing circuit according to an embodiment of the present invention. 38...1H delay line, 39...adder,
31...Adder, 45...Delay line, 47
...Delay line, 44...Adder, 49...
Sign inverter, 50...Switching circuit, 51...
...Switching circuit.

Claims (1)

[Scope of Claims] 1. In each of the plurality of light receiving parts arranged in a matrix of a solid-state imaging device, odd numbered rows in the vertical direction of the imaging screen are set as a first color arrangement pattern, and even numbered rows are set as the first color arrangement pattern. A second color array pattern different from the array pattern is used, and the same color component is obtained even if the colors of any two vertically adjacent rows are mixed in the shooting screen, and the colors of those two rows are also mixed. A means for accumulating signal charges by associating color filter elements with a color arrangement such that a luminance signal can be obtained when mixed; and an imaging screen obtained by reading out the signals accumulated in each of the light receiving sections. In a color solid-state imaging device that obtains color signals by arithmetic processing of the signals of the light receiving sections of three vertically adjacent rows, the signals of the three vertically adjacent rows are processed approximately vertically. A color signal forming means is provided which forms a red component signal and a blue component signal by adding and subtracting them with symmetrical weighting, and the signal levels of the upper and lower rows of the above three rows of signals are approximately equal, and the center signal is 1. A color solid-state imaging device, characterized in that the generation of false colors caused by differences in signal levels between the upper and lower rows is prevented by adding and subtracting to the signals of the rows.