JPH0468871A - Direct current reproducing circuit for ntsc video signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a circuit that clamps the DC level of an NTSC video signal, the purpose is to perform more stable DC playback of an NTSC video signal at the vedestal level without using a photoreflector. a comparator that compares the signal with a pedestal reference level and outputs it as an on/off signal, a timing circuit that generates a timing signal corresponding to the color burst section of the NTSC video signal, and a timing circuit that generates a signal from the comparator based on the timing signal. An analog switch that passes an on/off signal, a filter that converts the on/off signal output from the analog switch to a DC level corresponding to a duty ratio, and a hold circuit that holds the DC level based on the timing signal. , the difference between the DC level held in the hold circuit and the reference level is used as the variation amount
It consists of a comparator that adds and subtracts the TSC video signal in an adder and clamps it.

[Industrial application field]

The present invention relates to a DC reproduction circuit for an NTSC video signal, and more particularly to a circuit for clamping the DC level of an NTSC video signal.

In order to handle an NTSC video signal, it is necessary to correct and re-clamp the DC component of the NTSC video signal, since the NTSC video signal is affected by DC lift due to analog systems such as transmission lines.

[Conventional technology]

FIG. 4 shows an example of a bottom clamp type circuit as a DC reproduction circuit for an NTSC video signal, which has been conventionally used.

In the figure, a timing circuit 32 detects a synchronization signal (see FIG. 2) section of the NTSC video signal, generates a corresponding timing signal, and sends it to an analog switch 33.

The analog switch 33 allows only the synchronizing signal portion of the NTSC video signal to pass through, and the hold circuit 34, which also receives the timing signal from the timing circuit 32, holds the bottom level of the synchronizing signal.

Then, the comparator 35 compares this held bottom level and the bottom reference level (this is determined globally), and the difference is given to the subtraction unit 31, so that the NTS
Adjusts (clamps) the bottom level of the C video signal.

As a result, when the bottom level of the synchronization signal is higher than the reference level, it is clamped low, and when it is lower than the reference level, it is clamped high, so that the synchronization signal is always clamped at a constant bottom level.

[Problem to be solved by the invention]

In the bottom clamp method as described above, the potential difference between the bottom level and the pedestal level (D shown in Figure 2) is not stable, so the bottom level is set to S+'1! Even if it is clamped to the level, it does not mean that the important pedestal level is clamped to the reference level.

On the other hand, in the case of the method of clamping at the pedestal level, stable sampling cannot be performed because the range of the pedestal level (see FIG. 2) is narrow.

Therefore, in either method, there is a problem in that the brightness level fluctuates during direct current reproduction of the NTSC video signal, causing the screen to flicker.

Therefore, an object of the present invention is to perform more stable DC reproduction of an NTSC video signal at the pedestal level without using the bottom level.

[Means to solve the problem]

In order to achieve the above object, the NTSC video signal DC reproducing circuit according to the present invention compares the NTSC video signal with a pedestal reference level and outputs it as an on/off signal, as shown in principle in FIG. Comparator l and the NTSC
a timing circuit 2 that generates a timing signal corresponding to a color burst section of a video signal; an analog switch 3 that passes an on/off signal from the comparator 1 based on the timing signal; A filter 4 that converts the on/off signal into a DC level corresponding to the duty ratio, a Holt circuit 5 that holds the DC level based on the timing signal, and a DC level held in the hold circuit 5 and the reference level. The NTSC video signal is added to and subtracted from the NTSC video signal by using the difference between the two as a variation amount in an adder 7 and clamped.

[Operation] The operating principle of the present invention shown in FIG. 1 will be explained below with reference to the waveform diagram shown in FIG. 2.

First, the comparator 1 compares the NTSC video signal with a world-wide pedestal reference level and generates an on/off signal (rectangular wave signal) based on the magnitude relationship.

On the other hand, the timing circuit 2 detects the section of the color burst signal for color phase control superimposed on the vedestal level of the NTSC video signal, and supplies the corresponding timing signal to the analog switch 3 and the hold circuit 5.

Of the on/off signals from the comparator 1, the analog switch 3 passes only the on/off signal (signal A in FIG. 2) corresponding to the color burst section and sends it to the filter 4.

The filter 4 smoothes the on/off signal that has passed through the analog switch 3 to a DC level L that corresponds to the duty ratio.

The hold circuit 5 holds the DC level L during this color burst period and supplies it to the comparator 6.

The comparator 6 outputs the difference between the pedestal reference level and the DC level L, and the adder 7 adds and subtracts the difference from the NTSC video signal. By repeating this, the pedestal level of the NTSC video signal is clamped to the reference level. be able to.

Note that the NTSC video signal itself is taken out from the input side of the comparator 1.

In this manner, the present invention makes it possible to realize stable DC reproduction at a bedscale level, regardless of the bottom level.

〔Example〕

FIG. 3 shows an embodiment of the DC reproducing circuit for NTSC video signals according to the present invention, and the same parts as those shown in FIG. do.

In this embodiment, a simple clamp circuit 11 is provided at the input end of the NTSC video signal.

This is to make it easier to control the subsequent clamp circuit by clamping the bottom level of the NTSCN image signal to around "0", for example, as shown in Figure 2, but only at the beginning. A simple clamp may also be used.

Further, the adder 7 shown in FIG. 1 uses a differential amplifier that inputs the differential output from the comparator 6 and the output signal from the simple clamp circuit 11, and the output is sent to the A/D converter. At step 12, the signal is converted into a digital signal and sent to an NTSC video J language processing section (not shown).

Further, the timing circuit 2 shown in FIG. 1 includes a synchronous separation circuit 21 connected to the output of the simple clamp circuit 11, and P L 1 . , circuit 2
2, and a timing generation circuit 23 connected to this PLL@ path 22 and generating a timing signal.

In this timing circuit 2, a synchronization separation circuit 21 separates the horizontal synchronization signal (see FIG. 2), and a PLL circuit 22 separates the horizontal synchronization signal (see FIG. 2).
Generates a clock synchronized with the SC video signal.

Upon receiving this clock, the timing generation circuit 23 generates a timing signal whose starting point (rising) is the end point of the section W from the horizontal synchronizing signal to the color burst signal and whose ending point (falling point) is the end point of the color burst section.

The hold circuit 5 samples the smoothed DC level signal from the filter 4 at the falling edge of this timing signal and holds it for one line.

〔Effect of the invention〕

As described above, according to the NTSC video signal DC reproducing circuit according to the present invention, the NTSC video signal is compared with the pedestal reference level only in the section corresponding to the color burst section and converted into an on/off signal, and the on/off signal is converted into an on/off signal. The structure is configured so that the DC level is converted to a DC level corresponding to the duty ratio of the signal and held, and the difference between the DC level held and the pedestal reference level is used as a variation to add/subtract the NTSC video signal and clamp it. DC regeneration is achieved at the reference pedestal level, making it possible to realize a highly accurate lamp circuit.

Therefore, an excessive DC level is not applied to the NTSC video signal processing circuit, and furthermore, it is possible to eliminate flickering of brightness due to the screen due to the optimum DC level.

[Brief explanation of drawings]

Fig. 1 is a basic block diagram of the DC reproduction circuit for NTSC video signals according to the present invention. Fig. 2 is a waveform diagram for explaining the operating principle of the present invention. FIG. 4 is a block diagram showing one embodiment of a video signal DC regeneration circuit.
2 is a block diagram showing an example of a DC reproduction circuit (bottom clamp method) for an SC video signal. FIG. In FIG. 1, 1... Comparator, 2... Timing circuit, 3... Analog switch, 4... Filter, 5... Hold circuit, 6... Comparator, 7... Addition section. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A comparator (1) that compares an NTSC video signal with a pedestal reference level and outputs it as an on/off signal;
a timing circuit (2) that generates a timing signal corresponding to a color burst section of a C video signal; and a timing circuit (2) that generates a timing signal corresponding to a color burst section of a C video signal;
an analog switch (3) that passes the off signal; a filter (4) that converts the on/off signal output from the analog switch (3) to a DC level corresponding to a duty ratio; A hold circuit (5) that holds the level, and a difference between the DC level held in the hold circuit (5) and the reference level as a variation, and the NTSC video signal is added or subtracted by an adder (7) and clamped. A DC regeneration circuit for an NTSC video signal, comprising: a comparator (6);