JPH0470052A - Facsimile answering equipment - Google Patents

Facsimile answering equipment

Info

Publication number
JPH0470052A
JPH0470052A JP2182491A JP18249190A JPH0470052A JP H0470052 A JPH0470052 A JP H0470052A JP 2182491 A JP2182491 A JP 2182491A JP 18249190 A JP18249190 A JP 18249190A JP H0470052 A JPH0470052 A JP H0470052A
Authority
JP
Japan
Prior art keywords
facsimile
data
exclusive
circuit
facsimile terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2182491A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Mihashi
三橋 嘉之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2182491A priority Critical patent/JPH0470052A/en
Publication of JPH0470052A publication Critical patent/JPH0470052A/en
Pending legal-status Critical Current

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  • Facsimiles In General (AREA)

Abstract

PURPOSE:To prevent the misoutput of the data on other circuits by providing an exclusive OR circuit to secure an exclusive OR with a circuit No. to the date transferred to a buffer memory. CONSTITUTION:A facsimile answering equipment is provided with an anti-host device interface part 1 including an exclusive OR circuit, the buffers 2-4, and the facsimile terminal control parts 5-7 containing the exclusive OR circuits. In such a constitution, the exclusive OR is secured between the data and the circuit Nos when the data received from the host device are stored in the buffers 2-4 corresponding to the circuits. Then the same processing is also carried out when the data are read out of the buffers 2-4 respectively. Thus the misoutput of the data on other circuits is prevented.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ファクシミリ装置、更に詳しくは、ファクシ
ミリ画信号を入力どし1、ファクシミリ端末どの手順、
面出力を複数回線多重動作を行うファクシミリ応答装置
に関し、特に、他回線に対する画信号が誤って出力され
ることを防止する装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a facsimile machine, more specifically, to input a facsimile image signal, to a facsimile terminal, to
The present invention relates to a facsimile answering device that performs a multiplex operation for image output over multiple lines, and particularly relates to a device that prevents image signals from being erroneously output to other lines.

従来の技術 ファクシミリ応答装置は、上位装置よりキャラクタコー
ド情報域にはファクシミリ画信号を受信し、コード情報
の場合には文字バタンに変換した後にファクシミリ符号
化を行い、ファクシミリ画信号の場合には符号化方式の
変換などを行う。その後、回線に接続されたファクシミ
リ端末と手順を進めて前記の画信号を出力する0以上の
動作を複数回線の多重で行う。
A conventional facsimile answering device receives a facsimile image signal in the character code information area from a host device, converts the code information into a character stamp, and then performs facsimile encoding; Converts the format, etc. Thereafter, the procedure is carried out with the facsimile terminal connected to the line, and zero or more operations of outputting the above-mentioned image signals are performed by multiplexing over a plurality of lines.

発明が解決しようとする課題 上述したファクシミリ応答装置は、ファームウェアで構
成されており、内蔵されたプログラムに従ってマイクロ
コンピュータが装置内の各部の制御を行っている。
Problems to be Solved by the Invention The above-mentioned facsimile response device is composed of firmware, and a microcomputer controls each part within the device according to a built-in program.

このようなファクシミリ応答装置は、上位装置とは例え
ばGPIB等のバスによって接続され、このバスを通し
て制御データ、画信号データ等の授受が行われる0例え
ば上位装置から受信した画信号データをそのままファク
シミリ端末に出力する場合を考えると、ファクシミリ応
答装置は上位装置からバスを通して一定の大きさく例え
ば8にバイト)を単位としたブロックのデータを受信す
る。
Such a facsimile response device is connected to a host device via a bus such as GPIB, and through this bus, control data, image signal data, etc. are exchanged.For example, the image signal data received from the host device is sent directly to the facsimile terminal. In this case, the facsimile response device receives data in blocks of a certain size (for example, 8 bytes) from the host device via the bus.

このデータは装置内部のメモリ上に回線対応に割り当て
られたバッファメモリに一旦格納される。
This data is temporarily stored in a buffer memory allocated to each line on the internal memory of the device.

その後、ファクシミリ端末制御部がファクシミリ端末と
手順をとった後、前記バッファ中のデータを読み出して
ファクシミリ端末に出力する。
Thereafter, the facsimile terminal control section performs procedures with the facsimile terminal, and then reads out the data in the buffer and outputs it to the facsimile terminal.

上記のバッファは通常システムメモリ上に回線対応にア
ドレスを分割して割り当てられる。そのために、上位装
置からデータを受信する際、誤つて他回線のバッファに
データを格納したり、ファクシミリ端末に出力する際に
他回線のバッファからデータを読み出したりすると、他
回線の内容のファクシミリ画面がそのまま出力されてし
まい、サービス上重大な問題となる。
The above-mentioned buffer is normally allocated in the system memory by dividing addresses into lines. Therefore, if you accidentally store data in the buffer of another line when receiving data from a host device, or read data from the buffer of another line when outputting to a facsimile terminal, the facsimile screen of the contents of the other line may will be output as is, resulting in a serious service problem.

本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記課題
を解決し、他回線のデータの誤出力を防止することを可
能とした新規なファクシミリ応答装置を提供することに
ある。
The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a new facsimile response device that solves the above-mentioned problems inherent in the conventional technology and can prevent erroneous output of data from other lines.

課題を解決するための手段 上記目的を達成する為に1本発明に係るファクシミリ応
答装置は、装置内のバッファメモリと上位装置間のデー
タの授受を行う対上位インタフェース部、及びバッファ
メモリとファクシミリ端末間のデータの授受を行うファ
クシミリ端末制御部等のバッファメモリをアクセスする
部位において、バッファメモリに送受するデータに対し
、回線番号との排他的論理和をとるための排他的論理和
回路を備えて構成される。
Means for Solving the Problems In order to achieve the above objects, the facsimile response device according to the present invention includes a high-level interface section for exchanging data between a buffer memory within the device and a high-level device, and a buffer memory and a facsimile terminal. A part that accesses the buffer memory, such as a facsimile terminal control unit that sends and receives data between machines, is equipped with an exclusive OR circuit to perform an exclusive OR with the line number on the data sent and received in the buffer memory. configured.

実施例 次に本発明をその好ましい一実施例について図面を参照
して具体的に説明する。
Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック構成図である
FIG. 1 is a block diagram showing one embodiment of the present invention.

第1図を参照するに、本発明に係るファクシミリ応答装
置の一実施例は、排他的論理和回路を備えた対上位イン
タフェース部1と、バッファ(#0〜#n)2〜4と、
それぞれ排他的論理和回路を有するファクシミリ端末制
御部〈#θ〜#n〉5〜7とを具備している。
Referring to FIG. 1, one embodiment of the facsimile response device according to the present invention includes a high-level interface unit 1 equipped with an exclusive OR circuit, buffers (#0 to #n) 2 to 4,
It is provided with facsimile terminal control units <#θ to #n> 5 to 7 each having an exclusive OR circuit.

ファクシミリ応答装置は上位装置より対上位インタフェ
ース部lを通して画信号データを受信する。このとき、
排他的論理和回路を内蔵している対上位インタフェース
部lは、受信したデータ1バイトごとに回線番号との排
他的論理和をとり、その回線に対応したバッファ2〜4
にデータを格納する。
The facsimile response device receives image signal data from the host device through the host interface section l. At this time,
The upper-level interface unit l, which has a built-in exclusive OR circuit, performs an exclusive OR with the line number for each byte of received data, and stores buffers 2 to 4 corresponding to the line.
Store data in .

該当バッファのデータをファクシミリ端末に出力する際
には、まずファクシミリ端末制御部5〜7は、ファクシ
ミリ端末と手順をとった後にバッファのデータを読み比
し、ファクシミリ端末に送信する。ここで、それぞれ排
他的論理和回路を備えたファクシミリ端末制御部5〜7
は、読みだしたデータ1バイト毎に、バッファ格納時に
行ったと同じく回線番号との4他的論理和をとった後に
、そのデータをファクシミリ端末に送出する。
When outputting the data in the corresponding buffer to the facsimile terminal, the facsimile terminal controllers 5 to 7 first perform procedures with the facsimile terminal, read and compare the data in the buffer, and transmit the data to the facsimile terminal. Here, facsimile terminal control units 5 to 7 each having an exclusive OR circuit.
performs a 4-alternative OR with the line number for each byte of read data, as was done when storing the data in the buffer, and then sends the data to the facsimile terminal.

上述したバッファ格納、読みだし時の処理例を第2図に
示す。
FIG. 2 shows an example of the processing at the time of buffer storage and reading described above.

発明の詳細 な説明したように、本発明のファクシミリ応答装置によ
れば、上位から受信するデータを回線対応のバッファに
格納する際にデータと回線番号の排他的論理和をとり、
バッファからデータを読みだす際にも同じ処理を行うこ
とにより、誤って他回線のバッファからデータを読みだ
した場合でも正しいデータが得られず、ファクシミリ端
末に対して正常に認識できる画面が出力されることは無
くなり、他回線のデータの誤出力を防止できる効果が得
られる。
As described in detail, according to the facsimile response device of the present invention, when data received from a higher level is stored in a buffer corresponding to a line, an exclusive OR of the data and the line number is performed,
By performing the same process when reading data from the buffer, even if data is read from the buffer of another line by mistake, the correct data will not be obtained and a screen that can be correctly recognized will be output to the facsimile terminal. This eliminates the problem of erroneous output of data from other lines.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るファクシミリ応答装置の一実施例
を示すブロック111I成図である。 1− it上位装置インタフェース部、2〜・1・・・
回線χ・↑応バッファメモリ、5〜.7・・回線対応フ
ァクシミリ制御部 第2図はデータのハ・!7ア格納 読みだし時の処理例
を示した図である5、
FIG. 1 is a block 111I diagram showing one embodiment of a facsimile answering device according to the present invention. 1- IT host device interface section, 2~・1...
Line χ・↑corresponding buffer memory, 5~. 7...Line compatible facsimile control unit Figure 2 shows the data Ha! Figure 5 shows an example of processing when storing and reading 7A.

Claims (2)

【特許請求の範囲】[Claims] (1)、ファクシミリ画信号を入力とし、ファクシミリ
端末制御回路とこれを制御する制御回路を有し、ファク
シミリ画信号を必要に応じて符号化方式の変換を行いフ
ァクシミリ端末に出力する動作を複数回線の多重で行う
ファクシミリ応答装置であって、装置内のバッファメモ
リと上位装置間のデータの授受を行う対上位装置インタ
フェース部及びバッファメモリとファクシミリ端末間の
データの授受を行うファクシミリ端末制御部等の装置内
のバッファメモリをアクセスする部位において、画信号
データとそのデータの回線番号とを入力とし、入力した
回線番号と画信号データの排他的論理和をとる排他的論
理和回路を有することを特徴とするファクシミリ応答装
置。
(1) It takes a facsimile image signal as input, has a facsimile terminal control circuit and a control circuit that controls it, converts the encoding method of the facsimile image signal as necessary, and outputs it to the facsimile terminal over multiple lines. A facsimile response device that performs multiplexing, including a host device interface section that sends and receives data between a buffer memory in the device and a host device, and a facsimile terminal control section that sends and receives data between the buffer memory and a facsimile terminal. A portion of the device that accesses the buffer memory is characterized by having an exclusive OR circuit that receives image signal data and a line number of the data as input and performs an exclusive OR of the input line number and image signal data. facsimile answering device.
(2)、前記排他的論理和回路は前記対上位装置インタ
フェース部及び前記各ファクシミリ端末制御部に内蔵さ
れていることを更に特徴とする請求項(1)に記載のフ
ァクシミリ応答装置。
(2) The facsimile response device according to claim (1), further characterized in that the exclusive OR circuit is built in the upper-level device interface section and each of the facsimile terminal control sections.
JP2182491A 1990-07-09 1990-07-09 Facsimile answering equipment Pending JPH0470052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2182491A JPH0470052A (en) 1990-07-09 1990-07-09 Facsimile answering equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2182491A JPH0470052A (en) 1990-07-09 1990-07-09 Facsimile answering equipment

Publications (1)

Publication Number Publication Date
JPH0470052A true JPH0470052A (en) 1992-03-05

Family

ID=16119215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2182491A Pending JPH0470052A (en) 1990-07-09 1990-07-09 Facsimile answering equipment

Country Status (1)

Country Link
JP (1) JPH0470052A (en)

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