JPH0470820B2 - - Google Patents
Info
- Publication number
- JPH0470820B2 JPH0470820B2 JP21457589A JP21457589A JPH0470820B2 JP H0470820 B2 JPH0470820 B2 JP H0470820B2 JP 21457589 A JP21457589 A JP 21457589A JP 21457589 A JP21457589 A JP 21457589A JP H0470820 B2 JPH0470820 B2 JP H0470820B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistors
- parallel
- capacitor
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000004804 winding Methods 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 12
- 238000001514 detection method Methods 0.000 description 7
- 238000005259 measurement Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は電話装置における側音特性を改善した
局線とのインタフエイスの直流終端回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a DC termination circuit for an interface with a central office line in a telephone device, which has improved sidetone characteristics.
（従来の技術）
電話装置における局線とのインタフエイス回路
には信号電流と同時に直流電流が流れている。こ
の場合、変圧器に直流電流が流れるとそのループ
電流値の変化により側音レベルが大きく変化す
る。(Prior Art) A direct current flows simultaneously with a signal current in an interface circuit with a central office line in a telephone device. In this case, when direct current flows through the transformer, the sidetone level changes significantly due to changes in the loop current value.
第４図は従来の直流終端回路を示す図である。
図において、局線より直流電流と信号電流とが端
子L1，L2に入力される。信号はトランスＴの１
次側から２次側に変換されて出力端子T1，T2に
出力される。トランジスタQ1とQ2とはコンプリ
メンタリトランジスタを構成し、両者のコレク
タ・エミツタ間電圧の極性によつて交互にオンす
る。SSはトランジスタQ1，Q2のベースに直列に
接続される双方向ダイオードアレーでベース電流
を供給する。またREとトランジスタQ1，Q2の共
通のエミツタ抵抗、PC1及びPC2はトランジスタ
Q1，Q2のそれぞれのコレクタに接続されたホト
カプラで、図示されない受光素子と接合してそれ
ぞれに対応した信号を出力する。すなわち、ホト
カプラPC1，PC2は直流電流の検出信号と、いず
れのホトカプラPC1又はPC2がオンであるかで直
流極性の検出信号とを出力する。 FIG. 4 is a diagram showing a conventional DC termination circuit.
In the figure, direct current and signal current are input from the station line to terminals L 1 and L 2 . The signal is transformer T1
It is converted from the next side to the secondary side and output to output terminals T 1 and T 2 . Transistors Q 1 and Q 2 constitute complementary transistors, and are turned on alternately depending on the polarity of their collector-emitter voltages. SS is a bidirectional diode array connected in series to the bases of transistors Q 1 and Q 2 to supply base current. Also, the common emitter resistance of R E and transistors Q 1 and Q 2 , PC 1 and PC 2 are transistors
A photocoupler is connected to the collector of each of Q 1 and Q 2 and is connected to a light-receiving element (not shown) to output a signal corresponding to each. That is, the photocouplers PC 1 and PC 2 output a DC current detection signal and a DC polarity detection signal depending on which photocoupler PC 1 or PC 2 is on.
（発明が解決しようとする課題）
上記構成からなる直流終端回路はトランスＴに
直流のループ電流Ｉが流れるため、ループ電流Ｉ
の変化により側音レベルの変化が大きくなる欠点
がある。この変化については後述する。(Problem to be Solved by the Invention) In the DC termination circuit having the above configuration, since the DC loop current I flows through the transformer T, the loop current I
The disadvantage is that changes in the sidetone level result in large changes in the sidetone level. This change will be discussed later.
本発明は側音レベルの変化を抑制した直流終端
回路を提供することを目的とする。 An object of the present invention is to provide a DC termination circuit that suppresses changes in sidetone level.
（課題を解決するための手段）
本発明は上記目的を達成するため、局線端子間
に２組のホトトランジスタとトランジスタとの直
列回路を並列に接続し、２組のトランジスタは相
互にコンプリメンタリトランジスタ回路を構成
し、両トランジスタの共通のエミツタ抵抗を介し
て並列に接続し、かつ逆並列ダイオードとベース
抵抗とコンデンサの直列回路を並列に接続し、ベ
ース抵抗とコンデンサとの接続点に前記両トラン
ジスタのベースを接続し、さらに１次側が２巻線
からなるトランスの巻線間にコンデンサを接続し
て局線端子間に接続したことを特徴とする直流終
端回路を要旨とする。(Means for Solving the Problems) In order to achieve the above object, the present invention connects two sets of series circuits of phototransistors and transistors in parallel between station line terminals, and the two sets of transistors are mutually complementary transistors. Construct a circuit, connect both transistors in parallel through a common emitter resistance, and connect in parallel a series circuit of an anti-parallel diode, a base resistor, and a capacitor, and connect both transistors at the connection point between the base resistor and the capacitor. The gist is a DC termination circuit characterized in that the bases of the transformer are connected to each other, and a capacitor is connected between the windings of a transformer having two windings on the primary side, and is connected between the station line terminals.
（作用）
本発明は上記構成により、ループ電流をトラン
スに流さない構成とし、ループ電流が変化しても
側音レベルが変化しない回路とした。(Function) With the above configuration, the present invention provides a circuit in which no loop current is passed through the transformer, and the sidetone level does not change even if the loop current changes.
（実施例）
以下、図面に沿つて本発明の一実施例を説明す
る。なお、実施例は一つの例示であつて、本発明
の精神を逸脱しない範囲で種々の変更あるいは改
良を行いうることは言うまでもない。(Example) An example of the present invention will be described below with reference to the drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.
第１図は本発明の一実施例を示す回路図であ
る。図において、L1，L2は局線が接続される端
子、ホトカプラPC1、トランジスタQ1、エミツタ
抵抗REの直列回路とホトカプラPC2、トランジス
タQ2、エミツタ抵抗REの直列回路とが端子L1と
L2とに並列に接続され、逆並列に接続されたダ
イオードD1，D2、ベース抵抗RB、コンデンサC1
の直列回路も同様に端子L1とL2とに並列に接続
され、トランジスタQ1，Q2のベースは共通にベ
ース抵抗RBとコンデンサC1とに接続されるとと
もに、エミツタ抵抗REはトランジスタQ1，Q2の
共通のエミツタ抵抗である。また、ホトカプラ
PC1，PC2はコンプリメンタリトランジスタで構
成され、直流のループ電流Ｉの極性によつて一方
が導通し、図示してない受光素子を介して信号を
出力する。また、ダイオードD1，D2はホトカプ
ラPC1，PC2の電圧降下を補償するためのもので
ある。さらに、トランスT0は１次側を２巻線と
して、１次巻線相互間にコンデンサC2を接続す
る。 FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, L 1 and L 2 are terminals to which the office line is connected, and a series circuit of a photocoupler PC 1 , a transistor Q 1 , and an emitter resistor RE is connected to a series circuit of a photocoupler PC 2 , a transistor Q 2 , and an emitter resistor RE . terminal L 1 and
Diodes D 1 , D 2 connected in parallel with L 2 and antiparallel connected, base resistor R B , capacitor C 1
Similarly, the series circuit of is connected in parallel to terminals L 1 and L 2 , the bases of transistors Q 1 and Q 2 are commonly connected to base resistor R B and capacitor C 1 , and emitter resistor R E is This is the common emitter resistance of transistors Q 1 and Q 2 . Also, photocoupler
PC 1 and PC 2 are composed of complementary transistors, one of which becomes conductive depending on the polarity of the DC loop current I, and outputs a signal via a light receiving element (not shown). Furthermore, the diodes D 1 and D 2 are for compensating the voltage drop of the photocouplers PC 1 and PC 2 . Further, the transformer T 0 has two windings on the primary side, and a capacitor C 2 is connected between the primary windings.
かくして、トランジスタQ1又Q2にはループ電
流Ｉの極性によりベース抵抗RBを介してベース
電流が供給され、ループ電流Ｉの電流検出と、い
ずれのホトカプラPC1又はPC2がオンであるかに
よつてループ電流の極性検出を可能とする。な
お、ループ電流の電流検出、極性検出を必要とし
ない場合はホトカプラPC1，PC2はダイオードに
置き換えることができる。 Thus, the transistor Q 1 or Q 2 is supplied with a base current via the base resistor R B depending on the polarity of the loop current I, and it is possible to detect the current of the loop current I and which photocoupler PC 1 or PC 2 is on. This makes it possible to detect the polarity of the loop current. Note that if current detection and polarity detection of the loop current are not required, the photocouplers PC 1 and PC 2 can be replaced with diodes.
また、第２図は本発明の直流終端回路を局線と
のインタフエイス回路に適用した例を示す回路図
で、第１図と同一符号を付したものは同一の機能
を有する。図において、DSはダイヤルスイツチ、
HSはフツクスイツチ、ＣはフツクスイツチHSに
よつて作動する着信検出回路、HYBは２線／４
線変換回路である。このような局線とのインタフ
エイス回路を構成することにより、トランスT0
はループ電流Ｉの影響を受けることなく、２線／
４線変換回路を含めて通話回路の側音レベルを抑
制することができる。 Further, FIG. 2 is a circuit diagram showing an example in which the DC termination circuit of the present invention is applied to an interface circuit with a central office line, and the same reference numerals as in FIG. 1 have the same functions. In the figure, DS is a dial switch,
HS is a switch, C is an incoming call detection circuit activated by the switch HS, and HYB is a 2-wire/4-wire
It is a line conversion circuit. By configuring an interface circuit with such a station line, the transformer T 0
is unaffected by the loop current I, and the 2-wire/
It is possible to suppress the sidetone level of the speech circuit including the 4-wire conversion circuit.
次いで、第３図は電流検出、極性検出の受光素
子側の接続を示した図で、ホトカプラPC1，PC2
から信号S1，S2を出力する。 Next, Figure 3 is a diagram showing the connections on the light receiving element side for current detection and polarity detection, including photocouplers PC 1 and PC 2 .
Outputs signals S 1 and S 2 from.
次に、従来の直流終端回路と本発明の一実施例
の直流終端回路との特性について説明する。この
特性比較は等価的に行つたものである。 Next, the characteristics of a conventional DC termination circuit and a DC termination circuit according to an embodiment of the present invention will be explained. This comparison of characteristics was performed equivalently.
第５図は通話回路のブロツク図で、側音レベル
をvp／viとして定義する。但し、vpは送話系レベ
ル、viは受話系レベルで、Ｉは直流のループ電流
である。なお、DCは直流終端回路である。 FIG. 5 is a block diagram of a speech circuit, in which the sidetone level is defined as v p /v i . However, v p is the transmitting system level, v i is the receiving system level, and I is the DC loop current. Note that DC is a direct current termination circuit.
第６図及び第７図はそれぞれ、従来及び本発明
の測定回路、第８図及び第９図はそれぞれ、第６
図及び第７図の特性図を示す。測定は抵抗RL、
電流ILをパラメータとして受話系レベルviの入力
周波数を変化し、この変化に対し送話系レベルvp
を測定した。 FIGS. 6 and 7 show the conventional and inventive measuring circuits, respectively, and FIGS. 8 and 9 show the 6th measurement circuit, respectively.
7 and the characteristic diagram of FIG. The measurement is resistance RL ,
The input frequency of the receiving system level v i is changed using the current I L as a parameter, and the transmitting system level v p corresponds to this change.
was measured.
第７図において、RL＝0Ω、RL＝10Ω、IL＝125
ｍＡ、IL＝15ｍＡに対し最大100Hzにおいて15db
ｍの差があるのに対し、第８図ではRL＝0Ω、RL
＝10Ω、RL＝22Ω、IL＝15ｍＡ、IL＝125ｍＡに対
し、RL＝0Ω、IL＝125ｍＡの場合を除けば8dbｍ
以内であり、さらに、RL＝0Ω、IL＝15ｍＡを除
けば2dbｍ以内に抑制することができる。 In Figure 7, R L = 0Ω, R L = 10Ω, I L = 125
mA, I L = 15db at up to 100Hz for 15mA
m, whereas in Fig. 8, R L = 0Ω, R L
= 10Ω, R L = 22Ω, I L = 15 mA, I L = 125 mA, but 8 dbm except when R L = 0 Ω, I L = 125 mA.
Furthermore, if R L =0Ω and I L =15 mA are excluded, it can be suppressed to within 2 dbm.
（発明の効果）
以上説明したように、本発明によれば局線端子
間に２組のホトトランジスタとトランジスタとの
直列回路を並列に接続し、２組のトランジスタは
相互にコンプリメンタリトランジスタ回路を構成
し、両トランジスタの共通のエミツタ抵抗を介し
て並列に接続し、かつ逆並列ダイオードとベース
抵抗とコンデンサの直列回路を並列に接続し、ベ
ース抵抗とコンデンサとの接続点に前記両トラン
ジスタのベースを接続し、さらに１次側が２巻線
からなるトランスの巻線間にコンデンサを接続し
て局線端子間に接続したことにより、側音レベル
をループ電流の変化に対し、抑制することを可能
とし、例えば局線の線路長の長短により、短い場
合の抵抗挿入などの回路素子の付加をすることの
ない直流終端回路を提供することができる。(Effects of the Invention) As explained above, according to the present invention, two sets of series circuits of a phototransistor and a transistor are connected in parallel between the station line terminals, and the two sets of transistors mutually constitute a complementary transistor circuit. Both transistors are connected in parallel through a common emitter resistor, and a series circuit of an anti-parallel diode, a base resistor, and a capacitor are connected in parallel, and the bases of both transistors are connected to the connection point between the base resistor and the capacitor. By connecting a capacitor between the windings of a transformer whose primary side has two windings and connecting it between the station line terminals, it is possible to suppress the sidetone level against changes in the loop current. For example, depending on the length of the central office line, it is possible to provide a DC termination circuit that does not require the addition of circuit elements such as insertion of a resistor when the line length is short.
第１図は本発明の一実施例を示す回路図、第２
図は本発明の一実施例を局線とのインタフエイス
回路に適用した例を示す図、第３図はホトカプラ
の受光素子回路の一例を示す図、第４図は従来の
直流終端回路を示す回路図、第５図は側音レベル
を説明する図、第６図及び第７図は従来及び本発
明の特性測定回路図、第８図及び第９図は従来及
び本発明の特性を示す図である。
L1，L2……局線端子、PC1，PC2……ホトカプ
ラ、Q1，Q2……トランジスタ、RE……エミツタ
抵抗、D1，D2……ダイオード、RB……ベース抵
抗、C1，C2……コンデンサ、T0……トランス、
T1，T2……出力端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure shows an example in which an embodiment of the present invention is applied to an interface circuit with a central office line, Fig. 3 shows an example of a photocoupler light receiving element circuit, and Fig. 4 shows a conventional DC termination circuit. Circuit diagram, FIG. 5 is a diagram explaining the sidetone level, FIGS. 6 and 7 are characteristic measurement circuit diagrams of the conventional and present invention, and FIGS. 8 and 9 are diagrams showing the characteristics of the conventional and present invention. It is. L 1 , L 2 ... Station line terminal, PC 1 , PC 2 ... Photocoupler, Q 1 , Q 2 ... Transistor, R E ... Emitter resistor, D 1 , D 2 ... Diode, R B ... Base Resistor, C 1 , C 2 ... Capacitor, T 0 ... Transformer,
T 1 , T 2 ... Output terminals.
Claims (1)
ンジスタとの直列回路を並列に接続し、２組のト
ランジスタは相互にコンプリメンタリトランジス
タ回路を構成し、両トランジスタの共通のエミツ
タ抵抗を介して並列に接続し、かつ逆並列ダイオ
ードとベース抵抗とコンデンサの直列回路を並列
に接続し、ベース抵抗とコンデンサとの接続点に
前記両トランジスタのベースを接続し、さらに１
次側が２巻線からなるトランスの巻線間にコンデ
ンサを接続して局線端子間に接続したことを特徴
とする直流終端回路。1 Two sets of series circuits consisting of a phototransistor and a transistor are connected in parallel between the station line terminals, and the two sets of transistors mutually constitute a complementary transistor circuit, and are connected in parallel through the common emitter resistance of both transistors. and a series circuit of an anti-parallel diode, a base resistor, and a capacitor are connected in parallel, and the bases of the two transistors are connected to the connection point of the base resistor and the capacitor.
A DC termination circuit characterized in that a capacitor is connected between the windings of a transformer having two windings on the next side and connected between the station line terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21457589A JPH0378357A (en) | 1989-08-21 | 1989-08-21 | Dc termination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21457589A JPH0378357A (en) | 1989-08-21 | 1989-08-21 | Dc termination circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0378357A JPH0378357A (en) | 1991-04-03 |
| JPH0470820B2 true JPH0470820B2 (en) | 1992-11-12 |
Family
ID=16657987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21457589A Granted JPH0378357A (en) | 1989-08-21 | 1989-08-21 | Dc termination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0378357A (en) |
-
1989
- 1989-08-21 JP JP21457589A patent/JPH0378357A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0378357A (en) | 1991-04-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |