JPH0471392B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image signal decoding circuit in a facsimile device, etc., and more specifically, when receiving and decoding an encoded image signal, The present invention relates to a decoding circuit that includes a circuit that detects a scanning line synchronization signal (hereinafter referred to as an EOL signal) and forms a signal for decoding processing.

[Conventional technology]

Conventionally, devices such as facsimile machines and electronic files use microprocessors to encode and decode image signals using programs stored in memory. Examples of such devices include, for example, IEICE technical research report, "LSI Processor for Multipoint Monitoring and Control," IEICE, SSD80, No. 52, October 28, 1980, P.1-8;
Oki Electric Research & Development “Development of Custom LSI for FAX Simulation” No. 114, Vol. 48, No. 2, September 1981,
There is something disclosed on pages 31-38. The program processing used in this type of device is
Encode the black and white signal of the image according to CCITT recommendation T4,
It means decoding.

The decoding in the conventional device described above is based on the image signal
This is done by receiving the EOL signal, decoding the image data following the EOL signal, and converting it into an image drawing signal. Here, the EOL signal is added before the data of the first scanning line of the page and after the data of each scanning line, and is a 12-bit signal in the form of "000000000001". Confirmation of the received encoding system is performed according to a predetermined communication control procedure for the facsimile device before receiving the image signal. In program processing, each pixel is colored white based on the received image signal.
The decoding operation is performed by detecting the black signal and reading the EOL signal and image data.

[Problem that the invention seeks to solve]

However, in the above-mentioned prior art apparatus, the image signal is encoded and decoded through program processing by a microprocessor, and therefore has the disadvantage that the processing takes time. For example, when receiving image data spanning multiple pages, a control return signal (hereinafter referred to as RTC signal) consisting of six consecutive EOL signals is sent at the point where the page changes.
receive and distinguish from others. Normally, the receiving side recognizes 3 to 4 of these 6 EOL signals and marks the end of the page. In this case, EOL
The problem is that the program logic for counting the signals (12 or 13 bits) each time and distinguishing and processing the image data following the EOL signal becomes very complex.

Therefore, the present invention has been made to solve the problems of the prior art as described above.
The object of the present invention is to provide a decoding circuit that avoids complicated logic for distinguishing between an EOL signal and the image data that follows it, and realizes decoding with a simple circuit configuration.
Furthermore, the present invention provides an economical decoding circuit using a dedicated logic circuit using LSI technology.

[Means for solving problems]

The decoding circuit of the present invention receives an image signal encoded by an encoding method based on CCITT recommendation T.4, and extracts a synchronization signal from the image signal that is added to the beginning of each scanning line including the beginning of each page. In the decoding circuit for detecting a signal, a first shift register having five or more stages and driven by a clock signal corresponding to one bit timing of the image signal, and a final shift register of the first shift register are provided. The synchronization signal has an input connected to the output end of the stage and is added to the front of the image signal by 1.
A second shift register having a number of stages corresponding to the sum of bits and driven by the clock signal, and a second shift register driven by the clock signal, and the synchronization signal reception of,
and logical means for logically identifying the reception of the leading data when there is image data to be decoded next, and the first and second shift registers are configured to read the image signal including the synchronization signal. The clock signal is shifted and inputted using the clock signal.

(Operation) When the first bit of the synchronization signal included in the image signal reaches the final stage of the second shift register, the logic means immediately and reliably indicates the detection of the synchronization signal. The above purpose is achieved by outputting.

〔Example〕

FIG. 1 is a block diagram showing a decoding circuit according to an embodiment of the present invention. In the figure, 1 is an image signal input terminal, 11 is an EOL detection section, 12 is a received data decoding section, 13 is a techo preprocessing section, and 14 is a
FIFO (First In First Out) memory section, 15 is decoding post-processing section, 16 is line memory section A, 17
is line memory section B.

FIG. 2 is a circuit diagram showing details of the EOL detection section 11 of this embodiment. FIG. 3 is a table showing the processing procedure for decoding the two-dimensional code of facsimile image data, and this table also shows the processing procedure by the storage program. In the figure, P is pass mode, H is horizontal mode, V (V
(0), V _R (1), V _R (2), V _R (3), V _L (1), V _L
(2), V _L (3)) indicate vertical mode. FIG. 4 shows a configuration example of an EOL signal of a facsimile image signal and image data, and FIG. 5 shows a part of FIG. 4 in detail. The data shown in FIGS. 4 and 5 are examples of two-dimensionally encoded image data, and this format is confirmed by communication between facsimile devices before receiving the image signal. In other words, it is necessary to distinguish whether the whole is one-dimensionally encoded or two-dimensionally encoded, and if it is two-dimensionally encoded, the first EOL signal (EOL+1 or
Whether the image data following EOL+0) is one-dimensional encoded data or two-dimensional encoded data is confirmed by communication performed in advance between the two facsimile devices. In addition, “1” and “0” following the EOL code
The tag bits indicate that the next line is one-dimensional encoded data or two-dimensional encoded data, respectively, and a signal obtained by adding a tag bit "1" to the EOL code is placed on the first data line.

Input terminal 1 in FIG. 1 receives a binarized image signal and supplies it to EOL detection section 11. Input terminal 1 in FIG.
The EOL detection unit 11 automatically detects the EOL signal for each line from the received image signal, and confirms that the received data decoding unit 12 operates correctly.
It has a function to ensure that the first bit of each piece of received data comes to the starting point (initial setting point) shown in the figure. The received data decoder 12 has input terminals 1 and 1.
Input received data via the EOL detection unit 11,
For example, if the received data is a so-called prefix code, it works in conjunction with the decoding preprocessing section 13 to decode each bit in accordance with the processing table shown in FIG. Then, one of the prefix codes such as V(0), H, . . . is decoded and determined.
After the decoding process reaches each terminal point, the decoding preprocessing section 13 operates at each terminal point and transfers the decoded data to the FIFO memory section 14. The FIFO memory unit 14 stores the transferred data. When receiving and decoding an image signal, it is essential that the first bit of each line of the image signal or the first bit of image data be accurately captured and processed by the received data decoder 12. The decode post-processing unit 15 performs conversion processing on the data from the FIFO unit 15, and the converted data is supplied to either the line memory unit A16 or the line memory unit B17, that is, the one that is not performing the output operation, and is used for drawing. served.

Here, the EOL detection section 11 will be explained in detail with reference to FIG. 2. In the figure, 1 is an input terminal, 2 is a clock input terminal, 4, 5, 6, and 7 are output terminals,
21 is an 8-bit shift register, 22 is a 13-bit shift register, and 23 to 28 are logic circuits.

The input terminal 1 is the same as in FIG. 1 and receives an image signal. Clock input terminal 2 receives a clock signal (CK) corresponding to the 1-bit timing of the image signal.
Enter. The shift registers 21 and 22 are constructed by a known technique using 8 and 13 flip-flops (hereinafter referred to as F/F), respectively, and output a logic "1" or "0" signal. Shift register 22 is the No. 1 F/F in shift register 21
The output of is the input signal. Therefore, the shift registers 21 and 22 store continuous received signals in synchronization with the clock pulse (CK) inputted from the clock pulse input terminal 2, and also transfer the signal bit by bit to the lower F/F. The function of the EOL detection section 11 is to monitor the 12 or 13 bit and 8 bit signals from the starting position T of each line of the image signal shown in FIG. The purpose is to send out the detected signal. Terminal 4 is for each line in the case of one-dimensional encoding processing.
Outputs EOL signal. Terminal 5 outputs an EOL signal for each line in the case of two-dimensional encoding processing, and outputs (EOL+1) when the image data following the EOL signal is one-dimensional encoded data. Terminal 6 is the EOL signal of each line in the case of two-dimensional encoding processing.
Outputs (EOL+0) when the image data following the signal is two-dimensional encoded data.

In the case of two-dimensional encoding processing, the CCITT Recommendation stipulates that one-dimensional encoded data appears every second line, every fourth line, or only on the first line. When the 13-bit and 8-bit signals on the right side of point T of the image signal shown in FIG. 5 are stored in the shift registers 21 and 22 shown in FIG. 2, a detection signal is outputted to the terminal 5 shown in FIG. The image signals 1 and 0 shown in FIG. 5 are input to F/Fs No. 1 to No. 8 of registers 21 and 22 every one clock from the left side.
Transferred to F/Fs No. 1 to No. 13. terminals 4, 5, 6
The decoding preprocessing unit 13 selects which of the outputs is to be used as the EOL signal. Terminal 7 is connected to the second shift register when the EOL signal is received.
It is provided so that the first data of the next line is output, and is similar to the received data decoder 12 in FIG.
connected to.

In the above embodiment, the number of stages of the shift register 21 is set to eight in order to comply with CCITT Recommendation T.4 and also to support one-dimensional and two-dimensional encoding processing. However, if the data conforming to the rules in CCITT Recommendation T.4 is based on a one-dimensional encoding method, the shift register 22 has 13 stages, so the number of stages of the shift register 21 may be 5 or more.

〔Effect of the invention〕

As described above in detail, according to the present invention, since the first shift register, the second shift register, and the logic means are provided, the synchronization signal can be accurately captured in a short time. Therefore, there is an advantage that decoding processing can be performed quickly and easily. When this invention is applied to a facsimile device, it is very effective for high-speed operation of the device, and the logic of decoding processing that guarantees operation is simple, so it is also economically effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a decoding circuit according to an embodiment of the present invention, Fig. 2 is a detailed circuit diagram of an EOL detection section in the above embodiment, and Fig. 3 is a diagram showing a table of processing procedures for two-dimensional encoded data. , FIG. 4, and FIG. 5 are diagrams showing a configuration example of a received image signal and a detailed example of a part thereof, respectively. 11...EOL detection unit, 12...Received data decoding unit, 13...Decoding preprocessing unit, 14...
FIFO memory section, 15...Decoding post-processing section, 1
6... Line memory section A, 17... Line memory section B.

Claims (1)

[Claims] 1. An image signal encoded by an encoding method based on CCITT Recommendation T.4 is received, and a synchronization signal added to the beginning of each scanning line including the beginning of each page is extracted from the image signal. The decoding circuit for detection includes a first shift register having five or more stages and driven by a clock signal corresponding to 1-bit timing of the image signal, and a final stage of the first shift register. and has a number of stages corresponding to the number of bits of the synchronization signal added before the image signal plus one bit, and is driven by the clock signal. and a second shift register that receives the synchronization signal based on the output from each stage of the first and second shift registers, and when there is image data to be decoded next, the leading data is and logical means for logically identifying the reception of the clock signal, and the first and second shift registers shift and input the image signal including the synchronization signal using the clock signal. decoding circuit.