JPH0471U - - Google Patents

Info

Publication number
JPH0471U
JPH0471U JP3848090U JP3848090U JPH0471U JP H0471 U JPH0471 U JP H0471U JP 3848090 U JP3848090 U JP 3848090U JP 3848090 U JP3848090 U JP 3848090U JP H0471 U JPH0471 U JP H0471U
Authority
JP
Japan
Prior art keywords
time
schedule
register
core
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3848090U
Other languages
Japanese (ja)
Other versions
JP2514671Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990038480U priority Critical patent/JP2514671Y2/en
Publication of JPH0471U publication Critical patent/JPH0471U/ja
Application granted granted Critical
Publication of JP2514671Y2 publication Critical patent/JP2514671Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の回路構成を示す図
、第2図は第1図におけるRAMの構成を示す図
、第3図は第1図の表示部に設けられている液晶
表示パネルの表示体の配設状態を示す図、第4図
は本実施例の動作の概要を示すジエネラルフロー
チヤート、第5図は第4図中のスイツチ処理を詳
細に示すフローチヤート、第6図は第4図中のス
ケジユール処理を詳細に示すフローチヤート、第
7図は第4図中の表示処理を詳細に示すフローチ
ヤート、第8,9図は各種スイツチ操作に伴ない
液晶表示パネルにおける表示の変遷を示す図であ
る。 1……CPU、2……発振回路、3……分周回
路、4……時刻計数回路、5……日付計数回路、
6……RAM、7……スイツチ部、8……表示部
、9……RSフリツプフロツプ、10……報音装
置、11……液晶表示パネル、M……モードレジ
スタ、AF……アラームフラグ、N……次回スケ
ジユールレジスタ、P……メモリ指定レジスタ、
GT……累計労働時間レジスタ、TT……退社時
刻レジスタ、RT……労働時間レジスタ、ST…
…出社時刻レジスタ、X……全拘束時間レジスタ
、Y……コアタイム外拘束時間レジスタ、SH…
…基準出社時刻レジスタ、TH……基準退社時刻
レジスタ、CTA……コアタイム開始レジスタ、
CTB……コアタイム終了レジスタ、ZT……残
り拘束時間レジスタ、SF……出社フラグ、Q…
…拘束データ表示状態フラグ、SR……最低労働
時間レジスタ、KT……休憩時間記憶部、DM…
…スケジユール記憶部。
FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the RAM in FIG. 1, and FIG. 3 is a liquid crystal display panel provided in the display section of FIG. 1. FIG. 4 is a general flowchart showing an overview of the operation of this embodiment, FIG. 5 is a flowchart showing details of the switch processing in FIG. 4, and FIG. is a flowchart showing details of the schedule processing in Fig. 4, Fig. 7 is a flowchart showing details of display processing in Fig. 4, and Figs. 8 and 9 are displays on the liquid crystal display panel accompanying various switch operations. FIG. 1... CPU, 2... Oscillation circuit, 3... Frequency dividing circuit, 4... Time counting circuit, 5... Date counting circuit,
6...RAM, 7...Switch section, 8...Display section, 9...RS flip-flop, 10...Sound alarm device, 11...Liquid crystal display panel, M...Mode register, AF...Alarm flag, N ...Next schedule register, P...Memory specification register,
GT...Total working hours register, TT...Leaving time register, RT...Working hours register, ST...
...Attendance time register, X...Total restricted time register, Y...Restricted time outside core time register, SH...
...Standard arrival time register, TH...Standard leaving time register, CTA...Core time start register,
CTB...Core time end register, ZT...Remaining restraint time register, SF...Work attendance flag, Q...
...Restriction data display status flag, SR...Minimum working hours register, KT...Break time storage section, DM...
...Schedule Memory Department.

Claims (1)

【実用新案登録請求の範囲】 (1) コアタイムの開始および終了時刻を記憶す
るコアタイム記憶手段と、 スケジユール時刻を記憶するスケジユール時刻
記憶手段と、 コアタイムの開始および終了時刻と所望の日の
スケジユール時刻とからその所望の日の拘束時間
を求める手段と、 この手段で得られた拘束時間を表示する手段と
を備えることを特徴とする時間管理装置。 (2) コアタイムの開始および終了時刻を記憶す
るコアタイム記憶手段と、 スケジユール時刻を記憶するスケジユール時刻
記憶手段と、 コアタイムの開始および終了時刻と所望の日の
スケジユール時刻とからその所望の日の実労働時
間を求める手段と、 この手段で得られた拘束時間を表示する手段と
を備えることを特徴とする時間管理装置。
[Scope of Claim for Utility Model Registration] (1) Core time storage means for storing the start and end times of core time, schedule time storage means for storing schedule times, and start and end times of core time and desired days. 1. A time management device comprising: means for determining the restraint time on a desired day from the schedule time; and means for displaying the restraint time obtained by this means. (2) Core time storage means for storing the start and end times of core time; Schedule time storage means for storing schedule times; 1. A time management device comprising: means for determining actual working hours; and means for displaying restricted hours obtained by this means.
JP1990038480U 1990-04-12 1990-04-12 Time management device Expired - Lifetime JP2514671Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990038480U JP2514671Y2 (en) 1990-04-12 1990-04-12 Time management device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990038480U JP2514671Y2 (en) 1990-04-12 1990-04-12 Time management device

Publications (2)

Publication Number Publication Date
JPH0471U true JPH0471U (en) 1992-01-06
JP2514671Y2 JP2514671Y2 (en) 1996-10-23

Family

ID=31546523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990038480U Expired - Lifetime JP2514671Y2 (en) 1990-04-12 1990-04-12 Time management device

Country Status (1)

Country Link
JP (1) JP2514671Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5263585A (en) * 1975-11-20 1977-05-26 Shisutetsuku Kk Time control machine
JPH022758U (en) * 1988-06-13 1990-01-10

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5263585A (en) * 1975-11-20 1977-05-26 Shisutetsuku Kk Time control machine
JPH022758U (en) * 1988-06-13 1990-01-10

Also Published As

Publication number Publication date
JP2514671Y2 (en) 1996-10-23

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