JPH0472423B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a frame structure having a total length of (n+m) bits, consisting of a frame synchronization pattern of n bit length and information of m bit length.
The present invention relates to a frame synchronization method for value signal sequences, and particularly relates to a frame synchronization method having a forward protection function for N frames and a backward protection function for M frames.

Generally, in such a frame synchronization method, a counting means of the method (n+m) that counts the bit clock of the input binary signal sequence for one frame is used, and each time the count value of this counting means reaches a certain value K, a frame is A pulse is generated, and the counting means is controlled so that the position of the frame pulse thus generated is always at the beginning position of the frame of the input binary signal sequence or at a position shifted by a certain bit length from the beginning. In this control, for example, an n-bit length pattern (P ₁ , P ₂ . . . P _o ) of the input binary signal sequence is observed at each frame pattern position, and this is determined by a predetermined frame synchronization pattern ( r ₁ , r ₂ ... r _o ) is matched or mismatched. That is, if (P ₁ ,
If P ₂ . . . P _h ) and (r ₁ , _{r 2} . (This self-propelled state will be called the steady state.) If (P ₁ , P ₂ ...
If P _o ) and (r ₁ , r _{2 .} . . r _o ) do not match, it is assumed that the current frame pulse is in an asynchronous state and a process of searching for a correct frame pulse (this process is abbreviated as a hunting process) is started. However, such simple control will cause a serious defect if the input binary sequence has a code error in the transmission path or the like. That is, even though the frame pulse originally indicates the correct position, there is a risk that the frame pulse will be regarded as an asynchronous state due to a code error. Furthermore, in the hunting process, even if there is no transmission path error, there is a risk of finding a frame synchronization pattern in the information pattern, erroneously determining the correct frame position, and generating a new frame pulse. In order to reduce this risk, the hunting process may not be started immediately after a mismatch is detected, but only after the mismatch is detected multiple times. This is called a forward protection function, and the number of forward protection frames is the number of consecutive mismatches required to enter the hunting process. On the other hand, a function called backward protection is a function in which, even if a match is detected during the hunting process, the process returns to the hunting process unless this match continues for a plurality of consecutive frames. The number of consecutive matches required to return to steady state is the number of backward protection frames.

Conventionally, the design guidelines for such frame synchronization methods have been to keep the steady state as long as possible while keeping the time for returning from an asynchronous state to a synchronous state, that is, the time for returning synchronization to a required value or less, and to avoid reducing transmission efficiency. The question was what values should be chosen for n, N, and M. When designing such conventional frame synchronization systems, especially in PCM backbone transmission systems, it is important to remember that (1) sudden synchronization loss (for example, a one-bit shift in bit timing) occurs extremely rarely, and (2) steady state It is assumed that if the average duration is set sufficiently large, the hunting process will actually only appear in the initial synchronization pull-in process, and therefore the loss or duplication of frame pulses during the hunting process will not be a problem. Ta.

However, in recent years, as digital communication systems have been applied to consumer equipment and the like, situations have come to be seen where the above prerequisites do not necessarily hold true. In other words, under harsh usage environments,
Sudden loss of synchronization tends to occur with a relatively high probability. Furthermore, under such poor environments, error correction codes that are correlated over several frames are often used to accurately restore the current binary information; Loss or duplication can cause serious decoding errors.

In view of the above-mentioned circumstances, the present invention provides a frame synchronization method that can obtain a proper frame pulse even under a poor signal reception environment.

The principle of the present invention will be explained below using the drawings.

FIG. 1 is a block diagram showing an example of the most versatile conventional frame synchronization method known as the contention counting type frame synchronization method, and FIG. 2 is a waveform diagram showing its operating waveforms. As shown in FIG. 2A, the binary data series inputted from terminal 1 in FIG. 1 consists of a frame consisting of an n-bit frame synchronization pattern followed by an m-bit information series. In FIG. 1, a coincidence/mismatch detection circuit 4 observes n bits of data that have arrived up to a certain observation point, and if this matches the frame synchronization pattern, it supplies a coincidence pulse to the state control circuit 5, and if the frame synchronization pattern If they do not match, a mismatch pulse is supplied to the state control circuit. The counter 6 counts the clock pulses supplied from the terminal 2 by the modulus (n+m), and when the counting result reaches a certain value K, generates a frame pulse.
The observation time point of the coincidence/mismatch detection circuit 4 is specified by a clock pulse gated with a signal obtained by calculating the logical sum of the hunting instruction signal outputted from the state control circuit and the frame pulse. It is determined by the output of

The following is now defined as the internal state of the state control circuit. That is, S(x, y): The number of mismatch detections in steady state is x
H(z): A state in which the number of match detections is y in the hunting state. Now, in the contention counting type frame synchronization method,
When x of S(x, y) reaches the specified value N ₁ , the state is
Transition to Ho. Furthermore, if y of S(x,y) reaches the specified value _N2 first, the state is reset to S(o,o). Furthermore, the hunting instruction signal is at a high level only in state Ho. Further, when _z of the state Hz reaches the specified value M, the state is reset to S(o, o) again. Further, if a mismatch is detected in the state _Hz , the state returns to Ho. Therefore, the specified value N ₁ determines the length of the front protection, and the specified value M determines the length of the rear protection. Counter 6 is state control circuit 5
As a control method, for example, a method can be considered in which the counter is stopped in state Ho, and when the state changes to state _H1 , K is loaded into the counter and the self-running is started again. Here N ₁ = 4, N ₂ =
The operation of the conventional contention counting type frame synchronization method shown in FIG. 1 with M=2 and M=2 will be explained.

As mentioned above, A in FIG. 2 represents the input binary data series. Further, B represents a mismatch pulse, and C represents a match pulse. Furthermore, D represents a frame pulse and E represents a hunting instruction signal.
It is assumed that the mismatch pulses indicated by 21 and 22 in FIG. 2 are mismatch pulses that are generated when the binary data sequence undergoes random errors. Also, 23,2
It is assumed that the mismatched pulses 4, 25, and 26 are mismatched pulses resulting from true out-of-synchronization. Even if a mismatch pulse occurs due to a random error, as long as the internal state of the state control circuit does not reach S (4, 0) or S (4, 1), the counter runs free, so the correct frame pulse is maintained. When true synchronization occurs, on the other hand, the previous frame pulse position is held during the four frames in which forward protection is applied. At the time the mismatch pulse 26 occurs, the system is 27
In this state, the counting operation of the counter is stopped by inhibiting the input clock, etc., and a matching pattern is attempted to be detected while shifting the observation point one bit at a time. Assuming that a coincidence pulse is generated at time 28, this time is considered to be a temporary frame position, the above-mentioned hunting state is temporarily released, and the internal state of the state control circuit is set to _H1 . Also, at this time, a predetermined count value K is loaded into the counter, and as a result, the counter generates a frame pulse at the currently obtained temporary frame position and thereafter restarts the clock counting operation. When a coincidence pulse 29 is detected at the next observation point determined by this frame pulse, the internal state of the state control circuit becomes S(o,o).
The system is reset to the above-mentioned steady state again. However, the above conventional example causes the following problems. That is, in the hunting process, if the coincidence pulse 28, which should originally indicate a new frame position, disappears due to a transmission line error, the counter does not generate a frame pulse, resulting in frame pulse dropout. Such missing frame pulses cause the undecodable state to continue for the number of frames, for example, when the input data is an error correction code that has a correlation over several frames. Furthermore, even if a matching pulse is detected in the hunting process and synchronization is restored, if this is immediately used as a frame pulse, the frame pulse up to the point of synchronization restoration and the frame pulse after synchronization restoration may partially overlap. It can happen. Now, it is necessary to sequentially number the frame pulses that are currently continuing before synchronization is restored as the first frame pulse, second frame pulse, ..., nth frame pulse, and perform code processing such as error correction over the n frames. Assume that there is. The n frames are usually counted in a frame counter. Assume here that after synchronization is detected in the second frame and the hunting process is completed, a frame pulse after synchronization is restored occurs several bits later than the third frame pulse. Since this frame pulse, which is currently obtained as the third frame pulse, is generated at the correct position, it is called the 3'-th frame pulse. All the fourth frame pulses and subsequent ones are updated with newly obtained frame pulses after the 4'th frame pulse. However, the third frame pulse and the 3'-th frame pulse overlap as pulses representing the third frame position, resulting in a difference of one pulse in the count value of the frame counter. Therefore, the above-mentioned encoding processing over n frames is all performed based on erroneous count values.

The present invention provides a new frame synchronization method that eliminates these drawbacks. First, after eliminating the frame pulse dropout during hunting,
The present invention is characterized in that when two frame pulses overlap in a half frame, only the first pulse is extracted, thereby obtaining a regular frame pulse with no omissions or overlaps.

That is, an object of the present invention is to obtain a total sum (n
+m) This is a frame synchronization method for a binary signal sequence with a clock cycle of T seconds, which has a bit length frame structure, and has a forward protection function for N frames and a backward protection function for M frames (however, N and M are 1
In a frame synchronization method having a positive integer equal to or more than
The bit pattern (P _k P _k+1 ,..., where n' is a positive integer less than or equal to n) that has arrived by t _k is
P _k+o ′ _-1 ) and detecting the correlation between the observed bit pattern thus obtained and a predetermined reference pattern of n′ bits; state control means for controlling;
frame pulse overlapping output prohibition means for prohibiting the pulse that occurs later in time when two pseudo frame pulses occur during a half frame, and the internal state of the state control means is returned to an initial state. If so, the generation time of the pseudo frame pulse that appears every (n+m) T seconds is set as the observation time, and when the internal state of the state control means is in the hunting state, the bit timing time every T seconds is set as the observation time. In the initial state, when the output of the correlation detection means is below a certain value N times in a row, the internal state of the state control means is changed to a hunting state, and in the hunting state, the output of the correlation detection means is When the state in which the value is equal to or higher than a certain value continues M times, the internal state of the state control means is changed to the initial state, the count value of the counting means is forcibly set to K, and the output of the frame pulse duplication output inhibiting means is used to prevent the frame from being generated. An object of the present invention is to provide a frame synchronization method characterized by using pulses.

FIG. 3 is a block diagram showing a general embodiment of the frame synchronization system according to the present invention, in which 31 is a data input terminal, 32 is a clock input terminal, 33 is a regular frame pulse output terminal, and 34 is a normal frame pulse output terminal. Correlation detection means, 35 state control means, 36 counting means, 37
is a frame pulse duplicate output prohibition circuit. Now, assuming that the internal state of the state control means 35 is in the initial state, in this state, the counting means 36 is
The clock pulses are counted and the counting result is the specified value K.
It runs on its own, generating a pseudo frame pulse every time it reaches . This pseudo frame pulse determines the pattern observation time of the correlation detection means 34 in a steady state. The correlation detection means 34 observes a pattern (P ₁ , P ₂ , ... P _o ') of n' bit length (where n' is a positive integer such that n'≦n) that has arrived up to this observation time, and compares it with this observed pattern. Correlation with predetermined reference patterns (r ₁ , r ₂ , ... r _o ') is taken, and if the correlation value is above a certain value, matching information is supplied to the state control means 35, and if the correlation value is below a certain value If so, mismatch information is supplied to the state control means 35. When the mismatch information reaches the predetermined number _N1 of forward protection frames, the internal state of the state control means 35 becomes state Ho. At this time, the state control means 35 outputs a hunting instruction signal 39, and causes the correlation detection means 34 to perform pattern matching detection while shifting the observation time point of the frame synchronization pattern one bit at a time. Conversely, when the matching information reaches the specified number _N2 , the internal state of the state control means 35 is reset to the initial state. State control means 3
When the internal state of 5 changes to the hunting state Ho,
The correlation detection means 34 uses all bit timing times as observation points. Here, the specified number of backward protection frames is assumed to be M. When M=1, once matching information is detected in the hunting state Ho, the internal state of the state control means 35 is immediately reset to the initial state. At this time, the state control means 35 outputs the load signal 40, and the counting means 36 receives the specified value K.
is forced to load. When M≧2, when matching information is detected in the hunting state, the state control means 35 forcibly loads K into the counting means 36 and performs correlation detection 34 using the pseudo frame pulse generated from the counting means 36. Determine the observation point. If (M-1) pieces of matching information are successively detected in this state, the state control means 35 is reset to the initial state. If (M-1) pieces of matching information are not obtained, the hunting state reverts. However, if the original frame synchronization pattern is detected by the correlation detection means 34 after the pseudo frame pulse is output from the counting means 36, the frame synchronization is detected. Two pseudo frame pulses may be output from the counting means 36 within a time period shorter than the period of the pattern.
This duplicate output of pseudo frame pulses can occur when the frequency of the clock supplied from terminal 32 is higher than the maximum change frequency of the input binary data sequence. In this case, the value of the counting means 36 becomes a constant value K and a pseudo frame pulse is output, and after the value of the counting means becomes larger than K, the correlation detecting means 34 detects a frame synchronization pattern. As a result, the counting means 36 is set to K by the load signal 40 and outputs the pseudo frame pulse again.
This pseudo frame pulse is input to a frame pulse duplicate output prohibition circuit 37, where only the first of the duplicate pulses is output, and the output of subsequent frame pulses is prohibited.

Here, the period in which the output of subsequent frame pulses is prohibited after the first pulse is output in the frame pulse duplication output prohibition circuit 37 may be set to about half a frame. As already mentioned, duplication of pseudo-frame pulses occurs when the clock frequency fc is higher than the maximum change frequency fs of the input binary data sequence, so that
The fact that these pseudo frame pulses are outputted repeatedly means that fs≈2fc. In reality,
Such extreme cases will never occur,
The interval between overlapping pulses is much shorter than half a frame. Therefore, it is practically sufficient to set the length of this prohibited section to half a frame.

When the length of this prohibition section is set to half a frame, a frame pulse duplication output prohibition circuit is configured as shown in FIG. 4, for example.

That is, FIG. 4 is a circuit diagram showing a specific implementation example of the frame pulse duplicate output prohibition circuit used in the frame synchronization method according to the present invention.
is an input terminal to which the pseudo frame pulse is input,
42 is a clock input terminal, 43 is an output terminal from which a regular frame pulse is output, 44 and 48 are inverters, 45, 46, 49 and 50 are AND gates, and 47 is a counter that counts the number of clocks for half a frame. .

FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. 4. The operation of the frame pulse duplicate output prohibition circuit shown in FIG. 4 will be explained with reference to FIG. 5 as well.

FIG. 5A shows an example of a pseudo frame pulse supplied from the counting means 36 shown in FIG. 3 to the frame pulse duplication output prohibition circuit 37. For example, if the forward protection is for two frames, 52 and 53 represent frame pulses that are output at the same period as the past frame pulses before 51 during the forward protection period when frame synchronization is detected. . 5
4 and 55 are frame pulses indicating the frame synchronization position newly captured by the hunting operation, indicating that the new frame synchronization position has shifted by 2 bits in the positive direction from the previous frame synchronization position. There is. Note that, contrary to the above, when there is a two-bit shift in the negative direction, a frame pulse corresponding to 54 is not generated. FIG. 5A shows an example in which frame pulses overlap because the frame synchronization position is shifted in the positive direction. FIG. 5B is a clock pulse supplied from the terminal 42 in FIG. 4, and the inverted output and the pseudo frame pulse are ANDed by the AND gate 45 in FIG. 4, and the output is: An AND gate 50 performs a logical product with the output of the counter 47. FIG. 5C shows the output of the AND gate 50 thus obtained, which output is supplied as a reset pulse to the counter 47. The counter 47 counts a predetermined number of clocks from the time of reset (half a frame in the example of FIG. 5), and since the counter output is at a low level during the counting period, the reset pulse is As shown, the pulse corresponding to frame pulse 54 is erased. FIG. 5D shows the output of the counter 47 obtained in this way, and if this output is ANDed with the pseudo frame pulse of FIG. 5A, a desired frame pulse with no overlap as shown in E is obtained. can get.

Here, the pulse 53 output as a frame pulse is not the original frame pulse, but the erased pulse 54 is the original frame pulse.
However, since the counting means 36 is set to a constant value K and operates at the timing of the original frame pulse (pulse 54), this subsequent pulse 5
4 has no effect on the occurrence of the next frame synchronization pattern detection timing (the period during which the pulse 55 in FIG. 5A is at a high level).

As described above, according to the present invention, it is possible to obtain a frame synchronization method with no pulse dropout or duplication even under poor environments. In addition, in the above explanation,
Even if the state control means or both the state control means and the correlation detection means are implemented as firmware using a read-only memory, the gist of the present invention does not change in any way.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional frame synchronization method, in which 4 is a coincidence/mismatch detection circuit, 5
is a state control circuit, and 6 is a counter. FIG. 2 is a waveform diagram for explaining the operation of the frame synchronization method shown in FIG. 1, where A represents an input binary data sequence, B represents a mismatched opulse,
C represents a coincidence pulse, D represents a frame pulse, and E represents a hunting instruction signal. Third
The figure is a block diagram showing a general embodiment of the frame synchronization method according to the present invention, in which 34 is a correlation detection means, 35 is a state control means, 36 is a counting means, and 37 is a correlation detection means.
is a frame pulse duplicate output prohibition circuit. Fourth
The figure is a circuit diagram showing a specific embodiment of the pulse duplication prohibition means used in the present invention.
4 and 48 are inverters, 45, 46, 49 and 50 are AND gates, and 47 is a counter for counting the number of clocks for half a frame. Figure 5 A-E
4 is a waveform diagram for explaining the operation of the circuit shown in FIG. 4. FIG.

Claims (1)

[Claims] 1 A frame synchronization method for a binary signal sequence with a clock cycle of T seconds, which has a frame structure with a total (n+m) bit length consisting of an n-bit length frame synchronization pattern and m-bit length information, and forward protection for N frames. In the frame synchronization method, which has a backward protection function for M frames (N and M are positive integers), the number of clock pulses is counted modulo (n+m), and each time the counted value reaches a specified value K, a pseudo A counting means for generating frame pulses and a bit pattern (P _ko ′ ₊₁ , _... , P _k-1 , 1P _k ) and the observed bit pattern obtained in this way and the predetermined
correlation detecting means for determining the correlation with the reference pattern of n'bits; state control means for controlling the counting means according to the state of the system; includes frame pulse duplication output prohibition means for prohibiting a pulse that occurs later in time, and if the internal state of the state control means is in the initial state, the pseudo frame pulse appears every (n+m) T seconds. When the internal state of the state control means is in the hunting state, all bit timing times every T seconds are taken as the observation time, and in the initial state, the output of the correlation detection means is constant. The internal state of the state control means is changed to a hunting state when the state in which the output is equal to or less than a certain value continues N times, and in the hunting state, when the state in which the output of the correlation detection means is equal to or greater than a certain value continues M times, the state is changed to the hunting state. A frame synchronization method characterized in that the internal state of the control means is changed to an initial state, the count value of the counting means is forcibly set to K, and the output of the frame pulse duplication output inhibiting means is set as a frame periodic pulse. .