JPH0472427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission system for digital signals.

Conventionally, this type of digital signal transmission method includes a serial signal transmission method represented by the RS232C method and a parallel signal transmission method represented by the IEEE-488 method. When trying to make a connection, it has a high-class configuration, and the interface has many attached circuits and a large number of signal lines to be connected, so a large number of connectors and connection lines are required. As the price went up, problems arose. In particular, for devices that require smaller size and lighter weight, such as embedded devices for automobiles and portable devices,
The increase in the number of connectors and connection lines has been a major obstacle to miniaturizing devices.

An object of the present invention is to miniaturize the connecting connector and connecting cable between a pair of devices that transmit a relatively small amount of information, and to transmit the synchronizing clock signal exclusively and independently, thereby improving the synchronizing signal regeneration circuit. It is an object of the present invention to provide a digital signal transmission system in which the circuit is simplified by omitting the circuit.

The digital signal transmission system of the present invention includes a control signal line for transmitting a control signal having at least two different levels, a data transmission line for transmitting data, and a clock transmission line for transmitting a clock.
and a second device, and when transmitting data from the second device to the first device, the second device has both the data transmission line and the clock transmission line in a standby state. When it is confirmed that the clock signal is transmitted from the second device to the first device, the control signal is set to a predetermined level indicating the direction of data transmission from the second device to the first device, and in response to the level setting, the control signal is set to a predetermined level indicating the direction of data transmission from the first device to the first device. The data is transmitted to the first device in synchronization with the clock output on the transmission line for a predetermined period, and the first device reads the data transmitted in synchronization with the clock and transmits the data from the first device. When transmitting data to the second device, when the first device confirms that the control signal is at a level other than the predetermined level, it outputs the clock on the clock transmission line for a predetermined period, and The data is transmitted to the second device in synchronization with this clock after a predetermined clock period after the start of output, and the second device reads the transmitted data in synchronization with the clock.

According to the configuration of the present invention, since digital signals can be transmitted using three signal lines: the data transmission request signal line, the data signal transmission line, and the clock transmission signal line, the connection between devices is simplified, and the connection between these devices is simplified. The circuit between them is also simplified, allowing the device to be smaller and lighter.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.
This embodiment shows a case where signal transmission is carried out between a device 1 of a radio section and a device 2 of a telephone section in a car telephone. Digital signal transmission between device 1 and device 2 includes a unidirectional data transmission request signal line 3 from device 2 to device 1, a bidirectional data transmission signal line 4, and a unidirectional clock signal line from device 1 to device 2. This is done using three signal lines, the transmission signal line 5. The data transmission request signal line 3 is output from the output port po3 of the microprocessor 15 in the device 2 and is connected to the device 1 via a protection resistor r3. In the device 1, the signal is connected to a pull-up resistor R1 and input to the input port pi1 of the microprocessor 11 via a protection resistor r1. This data transmission request signal line 3 is always at a high (H) level, and becomes a low (L) level only when there is data to be sent from the device 2 to the device 1.

On the other hand, the data transmission signal line 4 is a line that transmits bidirectional signals. When data is sent from the device 1 to the device 2, the data is output from the output port po1 of the microprocessor 11 in the device 1, and is connected to the device 2 via the open collector driver 12. In device 2, microprocessor 1 is connected via protective resistor r4.
5, and when the device 2 is in reception mode, it operates as an input port.

Next, when sending data from device 2 to device 1,
Output port of microprocessor 15 in device 2
It is outputted from po4 via the open collector driver 16 and connected to the device 1 via the transmission signal line 4. This transmission signal line 4 is connected to a pull-up resistor R2 and input to the input port pi2 of the microprocessor 11 via a protection resistor r2. The open collector driver 12 is connected to this input port pi2, and is set to an open state when the device 1 is in the input mode.

Further, the clock transmission signal line 5 is connected to the clock output from the output port po2 of the microprocessor 11 of the device 1 to the copen collector driver 13.
The signal is connected to the device 2 via the protection resistor r5, and is input to the input port pi3 of the microprocessor 15.

FIGS. 2a, b, and c are time charts showing how data is transmitted from device 2 to device 1. FIG. Second
2A shows the operation waveforms of the data transmission request signal line 3, FIG. 2B shows the operation waveforms of the data transmission signal line 4, and FIG. 2C shows the operation waveforms of the clock transmission signal line 5. When the device 2 has data to send, it confirms that the data transmission/signal line 4 and the clock signal transmission line 5 are in the standby state (both at high level), and changes the data transmission request signal line 3 to low level. The device 1 constantly monitors the level of the data transmission request signal line 3, and when it changes to low level, it determines that it is a data transmission request from the device 2, and starts transmitting a synchronized clock signal with a period of 2t seconds to the clock transmission signal line. Send to 5.
The device 2 detects the fall of the synchronous clock signal, latches the data to be sent out at the timing of this fall, and sends the data to the data transmission signal line 4. Device 1
It is assumed that the signal on the data transmission signal line 4 is read at the rising edge of the synchronous clock signal. This read operation repeats this operation for one word (in this example, 8 bits) to transmit data, and when the transmission of one word is finished, the device 2 sets the data transmission request signal line 3 to a high level. At the same time, the output mode for the data transmission signal line 4 is switched to the input mode, and data transmission from the device 2 to the device 1 is completed.

Next, FIGS. 3a, b, and c are time charts showing the state of data transmission from device 1 to device 2, and a, b, and c correspond to the operating waveforms in FIG. 2. First, if there is data to be sent, the device 1 confirms that the data transmission request signal line 3 is at a high level, switches the data transmission signal line 4 to output mode, and switches the synchronous clock signal with a period of 2t seconds to the clock transmission signal. Send to line 5. It is assumed that this device 2 monitors the clock transmission signal line 5 when waiting for a signal, and receives data after detecting one period of the synchronous clock signal.

The device 1 latches the sending data and sends the data to the data transmission signal line 4 at each falling point of the synchronous clock signal from the falling edge of the second period. It is assumed that the device 2 reads the signal on the data transmission signal line 4 at each rising edge of the synchronous clock signal from the rising edge of the second cycle. This operation is repeated for one word to transmit data. When the transmission of one word is completed, the device 1 switches the data transmission signal line 4 to the input mode and stops the synchronous clock signal. Further, the device 2 returns from the reception state to the standby state and continues monitoring the clock transmission signal line.

FIGS. 4 and 5 also each show a time chart showing the operation of each signal line.

Fig. 4 a, b, and c show the case where data is transmitted from device 1 to device 2 (T1), and then 2-word data is transmitted from device 2 to device 1 (T2, T3), Fig. 5 a, b and c show respective operation waveforms when data is transmitted from device 2 to device 1 (T4), and then 2-word data is transmitted from device 1 to device 2 (T5, T6).

As explained above, according to the present invention, when transmitting data from device 2 to device 1, device 2 confirms that both data signal transmission line 4 and clock transmission signal 5 are in the standby state, The level of the control signal on the signal line 3 is changed to low level. Then, data transmission processing from device 2 to device 1 is performed in synchronization with a clock sent from device 1 for a predetermined period in response to this level change. When transmitting data from device 1 to device 2, the data transmission process is performed in synchronization with the clock output for a predetermined period by device 1, which confirms that the level of the control signal on signal line 3 is high. will be carried out. In this way, devices 1 and 2 monitor the states of signal lines 3 and 5 and data transmission line 4 to determine whether data transmission from their own devices is possible, and depending on this judgment, transmit signals from device 1 to signal lines 4. By transmitting and receiving data through the data transmission line 4 in synchronization with a clock output on the data transmission line 5 for a predetermined period, a simple three-wire digital signal transmission system is provided. For example, miniaturization of connectors and connection cables between a pair of devices;
Further, it is possible to simplify the circuit inside the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
Figures a, b, and c are time charts for data transmission from device 2 to device 1 in Figure 1, and Figures 3 a, b, and c are time charts for data transmission from device 1 to device 2 in Figure 1. Time chart when performing, Figure 4a,
b, c are time cheats when 2-word data is transmitted from device 2 to device 1 after data transmission from device 1 to device 2 in FIG. 1; FIG. 5 a,
b and c are time charts when data is transmitted from device 2 to device 1 in FIG. 1, and then 2-word data is transmitted from device 1 to device 2. In the figure, 1, 2... device, 3... data transmission request signal line, 4... data signal transmission line, 5...
Clock transmission signal line, 11, 15...Microprocessor, 12, 13, 16...Open collector driver, R1, R2...Pull-up resistor, r1
~r5...protective resistance.

Claims (1)

[Claims] 1. A control signal line for transmitting a control signal having at least two different levels, a data transmission line for transmitting data, and a clock transmission line for transmitting a clock are connected to the first and second devices. and when transmitting data from the second device to the first device, the second device confirms that both the data transmission line and the clock transmission line are in a standby state. Setting a control signal to a predetermined level for indicating the direction of data transmission from the second device to the first device, and outputting a control signal from the first device onto the clock transmission line for a predetermined period in response to the level setting. transmitting the data to the first device in synchronization with the clock, the first device reading the transmitted data in synchronization with the clock, and transmitting the data from the first device to the second device. When transmitting data, when the first device confirms that the control signal is at a level other than the predetermined level, it outputs the clock on the clock transmission line for a predetermined period of time, and then outputs the clock on the clock transmission line at a predetermined clock to start clock output. A digital signal transmission system characterized in that the data is transmitted to the second device in synchronization with this clock after a cycle, and the second device reads the transmitted data in synchronization with the clock.