JPH0473263U - - Google Patents
Info
- Publication number
- JPH0473263U JPH0473263U JP11389490U JP11389490U JPH0473263U JP H0473263 U JPH0473263 U JP H0473263U JP 11389490 U JP11389490 U JP 11389490U JP 11389490 U JP11389490 U JP 11389490U JP H0473263 U JPH0473263 U JP H0473263U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- transistors
- input terminals
- emitters
- whose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplitude Modulation (AREA)
Description
第１図は本考案の実施例に係るアナログ掛算器
を示す回路図、第２図は従来のアナログ掛算器の
一例を示す回路図、第３図は従来例および本考案
の実施例の特性を表わす図である。
Ｑ１〜Ｑ６……トランジスタ、Ｒ１〜Ｒ４……
抵抗、１１……定電流源、Ｃ１……コンデンサ。
Fig. 1 is a circuit diagram showing an analog multiplier according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a conventional analog multiplier, and Fig. 3 shows the characteristics of the conventional example and the embodiment of the present invention. FIG. Q1~Q6...transistor, R1~R4...
Resistor, 11... constant current source, C1... capacitor.
Claims (1)
記第１および第２の信号入力端子がそれぞれのベ
ースに接続され、かつ抵抗を介して、それぞれの
エミツタが第１の定電流源に接続された第１およ
び第２のトランジスタと、前記第３および第４の
入力端子がそれぞれのベースに接続され、それぞ
れのエミツタは共通に接続されかつ前記第１のト
ランジスタのコレクタに接続された第３および第
４のトランジスタと、前記第４および第３の入力
端子がそれぞれのベースに接続され、それぞれの
エミツタは共通に接続されかつ前記第２のトラン
ジスタのコレクタに接続された第５および第６の
トランジスタと、前記第３および第５のトランジ
スタのコレクタの接続点または前記第４および第
６のトランジスタのコレクタの接続点の少なくと
も一方から出力信号を取り出す手段とを備えたア
ナログ掛算器において、 前記第１のトランジスタのベースと前記第２の
トランジスタのエミツタ間、または前記第２のト
ランジスタのベースと前記第１のトランジスタの
エミツタ間のどちらか一方にコンデンサを設けた
ことを特徴とするアナログ掛算器。[Claims for Utility Model Registration] The first, second, third and fourth input terminals and the first and second signal input terminals are connected to their respective bases, and the respective first and second transistors whose emitters are connected to a first constant current source, whose third and fourth input terminals are connected to their respective bases, whose emitters are connected in common and whose emitters are connected to the first constant current source; third and fourth transistors connected to the collector of the transistor, the fourth and third input terminals connected to their respective bases, and their respective emitters connected in common and connected to the collector of the second transistor. means for extracting an output signal from at least one of a connection point between the collectors of the third and fifth transistors and a connection point between the collectors of the fourth and sixth transistors; In the analog multiplier, a capacitor is provided either between the base of the first transistor and the emitter of the second transistor, or between the base of the second transistor and the emitter of the first transistor. An analog multiplier characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11389490U JPH0473263U (en) | 1990-10-30 | 1990-10-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11389490U JPH0473263U (en) | 1990-10-30 | 1990-10-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0473263U true JPH0473263U (en) | 1992-06-26 |
Family
ID=31861522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11389490U Pending JPH0473263U (en) | 1990-10-30 | 1990-10-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0473263U (en) |
-
1990
- 1990-10-30 JP JP11389490U patent/JPH0473263U/ja active Pending