JPH0473360B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a color video signal reproducing device suitable for application to integrated video and the like.

BACKGROUND TECHNOLOGY AND PROBLEMS There is a recording and reproducing apparatus for color video signals such as integrated video, in which the color video signal is divided into a luminance signal and a pair of component color signals and recorded simultaneously on separate tracks.

In this case, for a luminance signal S _Y as shown in FIG. 1A, a pair of component color signals shown in FIG. As shown in Figure D, in this example, the time axis is compressed to 1/2 and the compressed color difference signal is sequentially and alternately arranged in time every 0.5 horizontal period.
S _C ′ is formed, and this compressed color difference signal S _C ′ and the luminance signal
S _Y are simultaneously recorded on adjacent tracks as shown in FIG. 2A.

In such a recording and reproducing apparatus, it is necessary to align the time axes of the luminance signal S _Y and the pair of compressed color difference signals S _C ' that are simultaneously reproduced from separate tracks during reproduction. Synchronization signals (in this example, synchronization pulses) P _R1 and P _R2 are inserted into each of the luminance signal S _Y and the compressed color difference signal S _C '. The first synchronization signal P _R1 inserted into the luminance signal S _Y is a horizontal synchronization pulse P _H as shown in A of the same figure.
In this example, it is inserted as a positive pulse with a pulse width of _1/2 of the horizontal synchronizing pulse in the second half of the period _of A second synchronization signal _PR2 of negative polarity is inserted on the time axis.

During playback, the time axes of the color difference signal S _C with respect to the luminance signal S _Y are aligned based on the pair of synchronization signals P _R1 and P _R2 , but in order to correctly align the respective time axes, the playback system requires considerable complexity. Currently, a time axis adjustment circuit is inserted. Therefore, such a recording/reproducing apparatus has the disadvantage that the circuit scale of the time axis adjustment circuit increases. In order to eliminate this drawback, it is sufficient to consider a time axis expansion system for the compressed color difference signal S _C '. For example, instead of writing the compressed color difference signal S _C ' in synchronization with the write zero pulse P _W formed based on the second synchronization signal P _R2 , its reading is performed based on the first synchronization signal P _R1 . This is done in synchronization with the readout zero pulse _PR .

In this way, the time axis of the expanded color difference signal S _C coincides with the time axis of the luminance signal Y, so that the time axis adjustment circuit and the like can be greatly simplified.

However, when the compressed color difference signal S _C ' is read out asynchronously with its writing, the writing operation and the reading operation may partially overlap.

That is, the reason why the write zero pulse P _W and the read zero pulse P _R are obtained at the same timing as shown in FIG. 3D is because the rotating magnetic heads H _Y and H _C contact the magnetic tape as shown in FIG. 2 B. This is when the inter-gap spacing W _H of is as designed. Therefore, due to manufacturing variations, the gap between the gaps
If W _H fluctuates, this interval W _H differs depending on the video used, or jitter occurs between Y/C, write zero pulse PW
and the read zero pulse P _R cannot be obtained at the same timing.

For example, if the inter-gap interval W _H is wider than a specified value, the reproduced luminance signal S _Y and compressed color difference signal S _C ' will be as shown in FIGS. 4A and B, and the writing zero pulse The readout zero pulse P _R is obtained in a temporally earlier state than P _W (Fig. 4C, D).

In such a case, the read mode for the memory element starts regardless of the write mode, so reading may start before the writing is completely completed, or the reading may be completely completed, as shown in FIG. 4F. There is a drawback that writing may start before the program is started.

Purpose of the Invention Therefore, in the present invention, when aligning the time axes of both based on a pair of synchronization signals, it is possible to align the time axes of both accurately with an extremely simple configuration, and it is possible to adjust the write timing. This is so that the read timings do not overlap.

SUMMARY OF THE INVENTION Therefore, in the present invention, data is written to a memory element for compressed color difference signals provided in a reproduction system based on a second synchronization signal P _R2 inserted into the compressed color difference signal S _C '. , the readout is performed based on the first synchronization signal P _R1 inserted into the luminance signal S _Y. By doing so, the time axes of the pair of color difference signals relative to the luminance signal S _Y can be easily and accurately aligned.

The memory elements include three pairs of memory elements, e.g.
When CCD memories are used and the first pair of CCD memories is in the write state, the second pair of CCD memories
CCD memory is put into hibernation state and the third
The pair of CCD memories is controlled to be in the read state, and the read clock is set to 1/n of the write clock (n is the compression ratio, in this example, n = 2), so that the write timing and read The time axis is expanded with the timings completely separated to obtain a pair of color difference signals.

Embodiment Next, an example of a reproducing apparatus according to the present invention will be described in detail with reference to FIG. 5 and subsequent figures.

The luminance signal S _Y and the compressed color difference signal S _C ' to be recorded on the tape are each inserted with synchronization signals P _R1 and P _R2 as shown in FIG. It is what was done. Since the specific configuration of the recording system for producing such a signal format is not directly related to the present invention, a description thereof will be omitted.

In FIG. 5, reference numeral 10 indicates an example of a reproduction system, which is a main part thereof.

FM luminance signal S _Y − reproduced from the reproduction head H _Y
The FM signal is supplied to the FM demodulator 12 via the preamplifier 11 to demodulate the luminance signal S _Y , and then supplied to the delay means 40.

In this example, the configuration is such that it can also be used as dropout compensation means, and has a pair of cascade-connected delay elements, CCDs 41 and 42 in the figure, one of which
While CCD41 is selected with a delay time of 1H,
The other CCD 42 is selected to have a delay time of 1H+T _D (FIG. 6B).

When forming the compressed color difference signal S _C ', there is a time difference of 1H with respect to the luminance signal Y, as shown in FIGS. 4A and B, and during reproduction, as shown in FIGS. 4E and F, Since the relative time relationship of the color difference signal S _C is further shifted by 1H, the reproduced luminance signal Y is changed by 2H.
By delaying the signal by the amount of time, the relative time relationship with the color difference signal S _C whose time axis has been expanded is made to match.

Further, the reason why the luminance signal Y is further delayed by T _D is to create a predetermined pause period between the end of writing and the start of reading, as shown in FIGS. 7D to I. In this example, the delay time T _D is selected to be about 15 μsec in consideration of variations in the inter-head spacing W _H and jitter between Y and C.

Oscillators 43 and 44 supply predetermined clocks to the CCDs 41 and 42. Further, 45 is a switching circuit, which is used for compensating for the luminance signal 1H before when a dropout occurs, and hence for compensating for the output dropout of the CCD 41. A dropout detection pulse is supplied to terminal 46.

The luminance signal Y delayed by a predetermined time is supplied to the mixer 13, where it is time-axis expanded as will be described later, and is converted into a color difference signal whose time axis is aligned with respect to the luminance signal S _Y.
A normal color video signal S _V is obtained from the terminal 14 by being mixed with S _C .

On the other hand, the FM compressed color difference signal S _C '-FM reproduced by the reproduction head H _C is supplied to the FM demodulator 17 via the preamplifier 16, and the compressed color difference signal S _C ' is demodulated. The compressed color difference signal S _C ' is supplied to a dropout compensation circuit 50 to compensate for dropout. As shown in the figure, the compensation circuit 50 is composed of a 1H delay CCD 51 and a switching circuit 52.

The compressed color difference signal S _C ' after dropout compensation is supplied to the time axis expander 20.

The time axis expander 20 includes a memory element 2 to expand the time axis of the compressed color difference signal S _C ' to the original time axis.
1 is provided. The memory element 21 is three pairs of CCDs.
It is composed of memories 21A to 21F. The write and read clocks for driving the memory element 21 will now be described.

The luminance signal S _Y is supplied to the synchronization separation circuit 22, from which the first synchronization signal P _R1 is separated.
In this example, the VCO 23 is controlled based on the first synchronization signal P _R1 and is synchronized with the first synchronization signal P _R1 .
A clock having a frequency of 720f _H (f _H is one horizontal frequency) is formed, and this is further divided in half by the counter 24 to form a read clock of 360 f _H. This read clock is sent to the clock generator 25.
is supplied to The first synchronization signal P _R1 is further supplied as a reference signal to the clock generator 25 to form a write zero pulse P _R as shown in FIG. 3D.

On the other hand, the demodulated compressed color difference signal S _C ' is supplied to the sync separation circuit 26 to sync-separate the second sync signal P _R2 , which is then supplied to the VCO 27 to generate 720f _H synchronized with the second sync signal P _R2 . A clock having a frequency of 1 is generated and is supplied to clock generator 25 as a write clock. Based on this, the second synchronizing signal P _R2 , which is also synchronously separated, is sent to the clock generator 25 in order to form the write zero pulse P _W (in this example, the same timing as the read zero pulse P _R ) shown in FIG. 3D. Supplied.

Next, the writing and reading operations of the compressed color difference signal S _C ' will be explained with reference to FIG.

Among the three pairs of CCD memories 21A to 21F,
The CCD memories 21A, 21C, and 21E are memories for writing and reading only the red compressed color difference signal (RY)', and the other CCD memories 21B, 21D, and 21F are for reading and writing the red compressed color difference signal (B-Y)'. It is a write/read only memory. When the first pair of CCD memories 21A and 21B are in the write mode, the second pair of CCD memories 21C and 21D are in the sleep mode, and the third pair of CCD memories 21E and 21F are in the read mode. The timing of sending the write and read clocks is controlled. The write, pause, and read modes are sequentially rotated in the above-mentioned order with a period of 3H.

Therefore, the timing charts of the CCD memories 21A to 21F are as shown in FIG. There is.

Note that during the horizontal blanking period, the color difference signal R-
Since Y and B-Y do not exist, there are some no-signal sections (shown with diagonal lines in Fig. 4B) in the line-sequential compressed color difference signals (R-Y)' and (B-Y)'. , this section is omitted in FIG.

Now, the compressed color difference signal S _C ′ is the writing zero pulse P _W
(B in the same figure), the writing clock of _720fH corresponds to the sequence shown in D to G in the same figure alternately.
Written into CCD memories 21A to 21F.

That is, in this example, the red compressed color difference signal (R-Y)' on the n-1 line is the first one for a period of 0.5H.
is written to the CCD memory 21A (D in the same figure), and the next
In the 0.5H interval, the compressed blue color difference signal (B-
Y)' (E in the same figure) is written. And the third
In the CCD memory 21C, the red compressed color difference signal (R-Y)' on the n line is written over the first half 0.5H period (FIG. compressed color difference signal (B-
Y)' is written (G in the same figure).

The fifth and sixth CCD memories 21E and 21F have n+1 lines of compressed color difference signals (R-Y)' and (B-
Y)' is written.

For example, a second pair of CCD memories 21
When the CCD memories 21E and 21D are in the write mode, the third pair of CCD memories 21E and 21F are in the sleep mode.
Since the first pair of CCD memories 21A and 21B are in the readout mode, the first pair of CCD memories 21A and 21B are simultaneously in the readout mode, and the time-axis expanded color difference signal ( R-Y) and (B-Y) are read out.

As mentioned above, write, read and sleep modes follow this order in each CCD memory.
Since it changes every 3H period, if a pause period T _D is provided between the write mode and the read mode, reading will not start before writing is completed. Furthermore, since there is a 1H pause period after the read mode, writing is not started before reading is completed.

When time axis expansion is performed using two pairs of CCD memories, the read mode is followed by the write mode, so there is a possibility that writing will start before the read is finished, but as mentioned above, three pairs of CCD memories When executing time axis expansion using
There is never any overlap between reading and writing.
The same applies to the first pair of CCD memories 21A, 21B and the third pair of CCD memories 21E, 21F.

These red and blue color difference signals R-Y and B-Y whose time axes have been expanded are supplied to a switching means 31. The switching means 31 includes first and second switching parts 31A and 31B as shown in FIG.
Switching control is performed such that the first switching section 31A outputs a red color difference signal RY, and the second switching section 31B outputs a blue color difference signal B-Y.

In this way, in the time axis expansion circuit 20, the time axis compressed red and blue color difference signals (R-Y)',
(B-Y)' is expanded on the time axis, sequentially converted into signals, and output. These are respectively supplied to the encoder 33, and after being encoded, the color difference signal is
S _C is supplied to the mixer 13, where it is combined with the luminance signal S _Y and converted into a commonly known color video signal S _V.

In this way, the compressed color difference signal S _C ′ is stored in the memory element 21.
When writing, it is written at the timing of the write zero pulse P _W formed based on the second synchronization signal P _R2 , and also formed based on the first synchronization signal P _R1 inserted into the luminance signal S _Y. read zero pulse
If read at the timing of P _R , the time axis of the luminance signal S _Y and the time axis of the color difference signal _SC whose time axis has been expanded can be made to completely match. Therefore, the time axis expansion circuit 20 can also be used as a time axis adjustment circuit, and the circuit configuration of the reproduction system is simplified.

And between write mode and read mode
By providing a pause mode called T _D and a 1H pause mode between the read mode and the write mode, writing and reading can be performed even if there are variations in the head spacing W _H or jitter occurs between Y and C. There is no longer any possibility that the respective timings of the signals partially overlap, and a complete color difference signal S _C whose time axis has been expanded can be obtained at all times.

Effects of the Invention As explained above, according to the structure of this invention,
The first synchronization signal inserted into the luminance signal S _Y controls the reading of the compressed color difference signal S _C ' to the memory element 21.
Since this is performed based on P _R1 , the time axes of the color difference signals RY and BY with respect to the luminance signal S _Y can be perfectly aligned without increasing the circuit scale.

In addition, the memory element 21 is connected to three pairs of CCD memories 2.
1A to 21F, it is possible to completely eliminate partial overlap between writing and reading even if mechanical errors in the rotating magnetic head or jitter occur between Y and C.

[Brief explanation of the drawing]

1 to 4 are diagrams for explaining the invention, FIG. 5 is a block diagram showing an example of a reproduction system in a color video signal reproduction apparatus according to the invention, and FIGS. A diagram for the invention,
FIG. 8 is a connection diagram showing an example of the switching means. H _Y and H _C are rotating magnetic heads, S _Y is a brightness signal,
S _C ' is a compressed color difference signal, 20 is a time axis expander, 21
is a memory element, 21A to 21F are CCD memories,
25 is a clock generator, 33 is an encoder, P _R1 ,
P _R2 is a first and second synchronization signal, and S _V is a color video signal.

Claims (1)

[Claims] 1. When reproducing a recording medium in which a pair of component color signals and a luminance signal that have been time-axis compressed within one horizontal section are simultaneously recorded on separate tracks, the pair of component color signals A signal is written to a memory element based on a second synchronization signal inserted into the component color signal, and the pair of component color signals are written based on a first synchronization signal inserted into the luminance signal. In the color video signal reproducing apparatus, the color video signal is read out from the memory element, the time axis is expanded, and a pair of component color signals whose time axes are aligned with respect to the luminance signal are obtained, wherein the memory element In this case, three pairs of memory elements are used, and when the first pair of memory elements is in a write state, the second pair of memory elements is in a dormant state, and the third pair of memory elements is in a read state. 1. A color video signal reproducing device, comprising a control means for controlling the color video signal so that the color video signal is reproduced.