JPH0474718B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument using program control. FIG. 1 is a block diagram showing an example of the configuration of a conventional electronic organ. In this figure, when a key on a keyboard 1 is operated, a key press detection circuit 2 detects this and outputs the key code of the operated key to a musical tone generator 3. Further, the timbre detection circuit 4 outputs a tone code corresponding to the timbre set by the timbre setting operator section 5 to the musical tone generating section 3. The musical tone generator 3 generates a waveform (timbre) corresponding to the tone code.
A musical tone signal (digital signal) having a frequency corresponding to the key code is formed and output to a D/A (digital/analog) converter 6. The D/A converter 6 converts the supplied musical tone signal into an analog signal and supplies it to the speaker 8 via the amplifier 7. As a result, the musical tone of the operated key is generated from the speaker 8. By the way, each circuit part of such a conventional electronic musical instrument was constructed from hardware. This has the drawback that the overall configuration of the electronic musical instrument is complex and large-scale, which makes it expensive.Also, when it is desired to expand the number of keys or tone setting controls, the configuration of each part of the circuit has to be changed. It also has the disadvantage that it is more complicated and cannot be easily expanded. Therefore, this invention not only simplifies the configuration, but also
To provide an electronic musical instrument in which the number of keys or the number of tone setting operators can be easily changed, and includes a keyboard section,
Each element of the tone setting controller section and the tone generating section is connected to a control means by program control via a common information transmission path, and the control means detects the operation status of the keyboard section and tone setting operator section, respectively. At the same time, based on this detection, a predetermined data signal that determines the frequency and waveform is supplied to the musical tone generator. Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of an electronic organ (electronic musical instrument) according to the present invention.The electronic organ shown in this diagram can be roughly divided into keyboard circuit 1.
1, an assigner 12, and a tone generator 13. The assigner 12 is the controller 1
4, a calculation control unit 19 including a calculation unit 15, an interrupt control circuit 16, a pulse generator 17, and a data port 18; a ROM (read only memory) 20;
It is composed of a RAM (random access memory) 21 and a first storage section 23 having a register 22, and the musical tone generating section 13 is a wave generator (hereinafter referred to as WG) having 32 channels.
25, an envelope generator 26 that sends envelope information to this WG 25, and a D/A
It is composed of a (digital/analog) conversion circuit 27, an amplifier 28, and a speaker 29. In addition,
The control section 14 and calculation section 15 described above are usually constructed using a microcomputer. Furthermore, the above-mentioned envelope is the envelope of the musical tone signal. That is, a normal musical tone signal has an envelope consisting of three states: a rising state (attack state) B1, a sustaining state B2, and a falling state (decay state) B3, as indicated by the symbol B in FIG. . This electronic organ operates under program control, and its program is composed of a processing program stored in the ROM 20 and various microprograms stored in the microprogram memory 45 in the control section 14. Also,
Various tone data and frequency data necessary for forming musical tone signals (digital signals) in the WG 25 are stored in the ROM 20. Based on the above processing program and microprogram, the system operates as follows. That is, when a key is pressed, the keyboard circuit 11 first
supplies key switch information corresponding to the pressed key to the assigner 12 via the data bus 30. The assigner 12 outputs frequency data and tone data corresponding to the supplied key switch information.
Read from ROM20 and transfer read data to WG25
Assign to multiple channels. WG25
Each channel forms a musical tone signal (digital signal) based on data assigned to the channel and envelope information supplied from the envelope generator 26. The musical tone signals formed by each of these channels are converted into analog signals by the D/A converter 27, and then the amplifier 2
A musical tone is emitted from the speaker 29 via the 8. The outline of this electronic organ has been described above, and now the details of this electronic organ will be explained. First, the keyboard circuit 11 includes an address decoder 34,
Buffer bus driver 35, matrix circuit 3
Consists of 6. The address decoder 34 decodes the switch address signal supplied via the address bus 37.
Each of these output terminals is connected to each column line of the matrix circuit 36, respectively. The matrix circuit 36 is a matrix with 12 rows and 5 columns, and each fulcrum of this matrix has a
The contacts of each switch of the tone lever (a lever for setting tones such as "Violin" and "Flute") 38 and the contacts of each key switch of the keyboard key 39 are connected together with diodes as shown by symbol A in the figure. It is inserted. In this embodiment, for convenience of explanation, it is assumed that the tone lever 38 consists of six tone levers, and each tone lever is capable of adjusting the volume in four stages (therefore, the information regarding each tone lever is 2
The tone lever switches correspond to these 2 bits, 2 for each tone lever, for a total of 12), and the keyboard keys 39 consist of 4 octaves (12 x 4 = 48 keys). shall be carried out. The switches for each tone lever are arranged in one row on the left side of the matrix circuit 36 (in the figure) (the two switches surrounded by broken lines in the figure correspond to one tone lever), and each key switch of the keyboard key 39 is arranged in one row (in the figure). Matrix circuit 36
They are placed in the 4th column on the right. The buffer bus driver 35 is a bus driver for outputting on/off information of each of the switches to the data bus 30, and has 12 input terminals and an output terminal, and each input terminal is connected to each row line of the matrix circuit 36. The output terminal is connected to the data bus 30. The control unit 14 is an instruction register 4
2, an instruction decoder 43, a microprogram/address sequencer 44, a microprogram memory 45 (second storage section), and a pipeline register 46. The instruction register 42 temporarily stores each instruction of the processing program read from the ROM 20, and the instructions temporarily stored in the instruction register 42 are sent to the instruction decoder 4.
3 and supplied to the microprogram address sequencer 44. The microprogram address sequencer 44 specifies the address of the microprogram memory 45 based on the output of the instruction decoder 43, and as a result, the processing program temporarily stored in the instruction register 42 is transferred from the microprogram memory 45. The microprogram corresponding to the instruction is read and the pipeline register 4
6. The calculation unit 15 includes a microfunction decoder (hereinafter abbreviated as MFD) 48 and a calculation circuit 4.
9, etc., and decodes each instruction of the microprogram supplied from the control unit 14 and executes a predetermined process. That is, MFD4
8 decodes each instruction of the microprogram supplied from the pipeline register 46, and based on the decoding result, register group 50, multiplexers 51, 52, arithmetic circuit 49, memory address register 53, data register 54, output Control signals are output to buffers 55 and 56, respectively. The register group 50 is a working register used in the process of processing each instruction of the microprogram, and the output of the arithmetic circuit 49 is read by the control signal from the MFD 48. is supplied to the input end of The multiplexer 51
The input terminal of is connected to the data bus 30, the third input terminal is connected to the output terminal of the data register 54, and the first to third input terminals are connected to the output terminal of the data register 54.
The data obtained at the third input terminal is selectively outputted to the arithmetic circuit 49. multiplexer 5
2 has its first input terminal connected to the data bus 30 and its second input terminal connected to the output terminal of the data register 54, respectively, and selectively transmits data obtained at these first and second input terminals. is output to the arithmetic circuit 49. The arithmetic circuit 49 receives various data supplied from the multiplexers 51 and 52 (this data includes address data specifying the address of each memory in the first storage section 23 and data used when allocating the above-mentioned keys to channels). ) is calculated based on the control signal from the MFD 48, and the calculation result is supplied to the memory address register 53 or data register 54. The memo address register 53 temporarily stores address data supplied from the arithmetic circuit 49.
The output of No. 3 is output to the address bus 37 via the output buffer 55. data register 5
4 temporarily stores data supplied from the arithmetic circuit 49 (data used when assigning keys to channels), and the output of this data register 54 is output to the data bus 30 via an output buffer 56. Ru. The interrupt control circuit 16 performs various processes when an interrupt occurs. Here, the interrupt signal of this electronic organ will be explained. This electronic organ has three interrupt signals INTR1, INTR2, and INTR3. Interrupt signal INTR1 is pulse generator 1
Based on the output of 7, the interrupt control circuit 16
This is an interrupt signal that is periodically generated every sec, and when this interrupt signal INTR1 is generated, on/off information of each key switch of the keyboard keys 39 is read into the RAM 21. The interrupt signal INTR2 is an interrupt signal generated by frequency-dividing the output of the pulse generator 17 by a frequency divider in the interrupt control circuit 16, and has a frequency of several 100 msec.
Occurs periodically. And this interrupt signal
When INTR2 occurs, on/off information for each switch of the tone lever 38 is read into the RAM 21. Note that the period of interrupt signal INTR2 is the interrupt signal
The reason why the cycle is much larger than that of INTR1 is that normally each key is operated frequently, but
This is because each tone lever is not operated as frequently as each key. The interrupt signal INTR3 is an interrupt signal supplied from the WG 25, and is generated when the musical tone signal formed in each channel within the WG 25 becomes 0. Note that this interrupt signal
INTR3 will be described later. And these interrupt signals INTR1 to INTR3
When any of the above occurs, the control unit 14 detects this, reads the interrupt instruction into the instruction register 42, and decodes it when the currently executing microprogram module is completed.
The priority order of interrupt signals INTR1 to INTR3 is as follows:
In the interrupt control circuit 16, INTR3>INTR1>INTR2 is determined. As mentioned above, the ROM 20 stores processing programs, frequency data, tone data, etc., and is supplied with an address signal from the output buffer 55 via the address bus 37, and read out using the same address signal. Each instruction or various data of the processing program is transferred to the data bus 3.
Output to 0. The RAM 21 stores various data tables, data files, etc. used in channel assignment, and is supplied with address signals from the output buffer 55, and its input/output ends are connected to the data bus 30. . The register 22 stores various statuses or commands (described later), and is supplied with an address signal from an output buffer 55, and its input end is connected to the data bus 30. Data port 18 is connected to frequency data, tone data stored in ROM 20, and register 2.
This is a register for outputting various commands stored in WG 25 and envelope generator 26 to WG 25 and envelope generator 26. Addresses are supplied from output buffer 55, and its input end is connected to data bus 30. In addition, the above
The contents stored in the ROM 20, RAM 21, register 22 and data port 18 are shown in FIG. Next, the operation of the electronic organ shown in FIG.
The explanation will be based on the flowchart shown in the figure. In the following description, "1" indicates a binary logic level "1" signal, and "0" indicates a binary logic level "0" signal. FIG. 3A is a flowchart showing the flow of the program, and FIG. 3B is an interrupt processing routine. As shown in this figure, the program of this electronic organ consists of eight main routines R1 to R8 and three interrupt processing routines I1 to I3. Each routine is converted into a plurality of microprogram modules and stored in the microprogram memory 45, and macro instructions for calling these microprogram modules are stored in the ROM 20 as processing programs.
Each of the above routines will be sequentially explained below. (1) Processing Reset Routine R1 When power is turned on in this electronic organ, the program first enters this initial reset routine R1, and initial resets of each part are performed. (2) Tone lever on/off detection routine I1 This interrupt processing routine is executed every time the interrupt signal INTR2 is generated at an interval of several 100 msec, and the keyboard circuit 11 at the time when the interrupt signal INTR2 is generated. The on/off state of each tone lever switch is detected. That is, when the interrupt signal INTR2 is generated in the interrupt control circuit 16, a switch address signal is supplied to the address decoder 34, and based on this switch address signal, the on/off information of each tone lever switch is sent to the buffer bus driver 35 and Read into register 22 via data bus 30. Then, based on the read tone lever switch on/off information, a new tone lever status table (hereinafter referred to as
(abbreviated as NTS) 60 is created. In this case, in this NTS60, the volume setting of each tone lever 1-6 is indicated by a binary number. That is, in the example shown in the figure, tone levers 1, 4, 5, and 6 request a volume of "0", and tone lever 2 requests a volume of "3".
, the tone lever 3 requests a volume of "2". (3) Tone lever position and change detection routine R2 When the above-mentioned initial reset routine R1 is completed, the program advances to this routine R2. This routine R2 detects whether the contents of the current NTS60 are different from the contents of the same NTS60 at the time when this routine R2 was executed last time.
The above detection is performed by comparing the contents of the old tone lever status table (hereinafter abbreviated as OTS; see FIG. 4) 61 created in the RAM 21. In addition
OTS61 indicates the contents of NTS60 at the time this routine R2 was executed last time.
It is created in Routine 3, which will be explained next.
If the result of executing routine R2 is "YES" (change), the program proceeds to routine R3, and if "NO" (no change), the program proceeds to routine R4. (4) Tone Lever Processing Routine R3 This routine R3 creates a tone request file 62 shown in FIG. 4 in the RAM 21 based on the contents of the NTS60.
In this electronic organ, tone data in the ROM 20 is assigned to each channel of the WG 25 based on the tone request file 62 created in this routine R3. That is, as shown in FIG. 4, a volume table 63, a tone lever index table 64, and a tone data bank 65 are provided in the ROM 20 in advance. The volume table 63 stores in advance volume coefficients (each channel of WG 25 sets the volume based on this volume coefficient) corresponding to the volume "1" to "3" set by the tone lever. , the tone data bank 65 contains a plurality of tone data, namely...tone data i-1, tone data i, tone data i+1, tone data i
+2... are stored in the tone lever index table 64, and each tone lever 1 to 6 is stored in the tone lever index table 64.
An address pointer of tone data for configuring a tone corresponding to the tone is stored. In this case, to explain the example shown in the figure, the tone corresponding to tone lever 1
is composed of tone data i-1 and i,
Therefore, the tone data bank 6 is stored in the slot (storage area) 64a corresponding to the tone lever 1 of the tone lever index table 64.
The leading addresses of tone data i-1 and i in 5 are stored, that is, address A and address B, and the tone corresponding to tone lever 2 is constituted by tone data i+2, therefore, address D is stored in slot 64b. is memorized,
Further, the tone corresponding to the tone lever 3 is composed of tone data i and i+1, and therefore an address B and an address C are stored in the slot 64c. In this embodiment, the maximum number of tone data constituting the tone corresponding to each tone lever is two, but it is possible to have a plurality of pieces of tone data, and there is no need to limit the number to two. When the program enters this tone lever processing routine R3 (a flowchart of this routine R3 is shown in FIG. 5), first, the tone lever 1 volume information stored in the NTS60 in the register 22 (FIG. 4) is read into the register group 50 of the arithmetic unit 15. However, since the volume is "0" in this case, no processing is performed. Then, the volume information of the tone lever 2 is read into the register group 50. in this case,
Volume "3" is specified. Therefore, first, the address pointer in the slot 64b of the tone lever index table 64 (i.e.,
address D) is tone request file 62
Then, the volume coefficient "1111111" corresponding to the volume "3" in the volume table 63 is written in the area 62c (see FIG. 4). Next, the volume information of the tone lever 3 is read into the register group 50. In this case, the volume "2" is specified, so first the first address pointer (i.e., address B) in slot 64c of table 64 is written in area 62d of tone request file 62, Next, the volume coefficient ("0100000") corresponding to the volume "2" is written in the same area 62d, and then the second address pointer (i.e., address c) in the slot 64c is written in the area 62e. Next, the volume coefficient ("0100000") corresponding to volume "2" is 62 in the same area.
written in e. In this way, NTS6
The volume information of each tone lever within 0 is sequentially read out and processed. Finally, the number of address pointers written in the tone request file 62, that is, the number of tone data registered in the tone request file 62, is written in the header (i.e., area 62a) of the tone request file 62. Then, the creation of the tone request file 62 is completed. After creating the tone request file 62
The contents of NTS60 are transferred into OTS61 and the program exits this routine R3. In this way, in this electronic organ, a tone request file 62 as shown in FIG. 4 is created in this routine R3. In this case, each tone lever corresponds only to the address pointer of the tone lever index table 64, so by changing the address pointer of this table 64, arbitrary tone data (timbre) can be made to correspond to each tone lever. be able to. Note that in this tone request file 62, information for tone processing common to this file 62, such as vibrato frequency, vibrato depth, decay length, etc., is stored in area 62b. That is, although a detailed explanation will be omitted, information for these tone processing is stored in the ROM 20 in advance, and the tone processing information is stored in accordance with the operation position of the tone processing lever.
By reading out the data from the ROM 20 and registering it in this file 62, it becomes possible to perform timbre processing on the musical tone signals formed in each channel of the WG 25. By the way, in the process of creating the tone request file 62 described above, the number of address pointers written in the header 62a is normally detected by providing a counter called a tone request counter in the register 22, and detecting the number of address pointers written in the header 62a every time an address pointer is written in the file 62. This is done by incrementing this tone request counter and finally referring to the count result of this tone request counter. In addition, in the above process, sequential reading of the contents of the NTS 60, sequential reading of address pointers in each slot of the tone lever index table 64, sequential writing to each area in the tone request file 62, etc. are normally performed by following the corresponding pointers. Each time one process is completed, the contents of this pointer are advanced, and execution is performed based on the contents of this pointer. For example, the tone request file 62
When writing the address pointer to the tone request file pointer, first set the entry address (address E) of the area 62c in the tone request file pointer, write into the area 62c based on this tone request file pointer, and then write the address pointer to the tone request file pointer. The contents are advanced to the entry address (address F) of the area 62d, and written into the area 62d based on this entry address (address F), and so on. However, these treatments are quite common in this industry, and therefore, description of these treatment steps is omitted in this specification. (5) Key on/off detection routine I2 This interrupt processing routine I2 uses the interrupt signal INTR
1 is generated at an interval of several milliseconds, and detects the on/off state of each key switch of the keyboard circuit 11 at the time when the interrupt signal INTR1 is generated. That is, in the interrupt control circuit 16, the interrupt signal
When INTR1 occurs, the address decoder 34
A switch address signal is supplied to the switch address signal, and on/off information of the key switch is read into the register 22 via the buffer bus driver 35 and the data bus 30 based on this switch address signal. New keyboard status table (see below)
(abbreviated as NKS) 70 is created. In the NKS 70 shown in this figure, "1" indicates that the key corresponding to this "1" is pressed down at the time when the interrupt signal INTR1 is generated. That is, in this example, currently the first octave's C note, E note, the second octave's D# note, and the third note.
This indicates that keys corresponding to the F# note of the octave and the A note of the fourth octave are being pressed. Note that in this figure, no mark indicates "0". (6) Pressed key position/change detection routine R4 When the tone lever processing routine R3 is completed, the program advances to this routine R4. This routine R4 detects whether the current state of the NKS 70 is different from the state of the NKS 70 at the time when this routine R4 was executed last time. The above-mentioned detection is performed by comparing the contents of 71 (hereinafter abbreviated as OKS). In this case, OKS71 indicates the state of the key switch at the time when this routine R4 was executed last time, and is created in routine R6, which will be described later. If the result of executing this routine R4 is "YES" (change), the program proceeds to routine R5, and if "NO" (no change), the program returns to routine R2. (7) Key-on request file creation routine R5 This routine R5 detects a key that should generate a new musical tone, in other words, a newly pressed key, and based on this detection result, creates a key-on request as shown in FIG. file (hereinafter referred to as ON・
RQ) 72 is created on the RAM 21. In this routine R5, first OKS7
An exclusive OR is taken between each bit of 1 and each corresponding bit of NKS 70 (OKSNKS). As a result, only the bit corresponding to the key switch whose state has changed becomes "1". Next, the above calculation result and each bit of NKS 70 are ANDed. [(NKS∧
(OKSNKS)]. As a result, only the bit whose key switch is newly turned on becomes "1".
Finally, the result of the AND operation above and ON・RQ7
The OR between each bit of 2 is taken, and the result is newly written to ON.RQ72. ON・RQ =ON・RQ∨{NKS∧(OKSNKS)}
...(1) Here, we will explain the meaning of the last OR operation. In the key-on channel assignment routine R7, which will be explained later, this electronic organ executes a process of assigning a key to generate a musical tone to each channel of WG25 based on the ON-RQ72 created here, and this assignment process is completed. Sequentially ON/RQ72 “1” at the time
It is designed to erase bits. By the way, at the time when this routine R5 is executed, when the routine R5 was executed last time, ON・RQ72
Not all "1" bits written in the channel are necessarily erased, and "1" bits may remain that should be subjected to channel allocation processing. The final OR operation is performed to leave unprocessed "1" bits on the ON.RQ 72. In FIG. 6, the circle marked on the first octave C note indicates this processing bit. (8) Key-off request file creation routine R6 This routine R6 detects a key that should stop generating musical tones, that is, a key that has been released, and based on this detection result, creates a key-off request file (hereinafter referred to as (abbreviated as OF・RQ)
73 on the RAM 21. In this routine R6, first, like routine R5, CKS71, NKS70, OF・RQ
Between each corresponding bit of 3, OF・RQ =OF・RQ∨{∧(OKSNKS)}
...(2) The following calculation is performed, and the result of this calculation is OF・RQ7
Written within 3. Note that in this formula,
NKS means the inversion of each bit of NKS70. Furthermore, the meaning of the OR operation is the same as in routine R5. Next, the contents of NKS70 are OK.
71. That is, by this process, the table used as NKS this time will be used as OKS7 in the next process of routines R4 to R6.
It will be used as 1. (9) Key-on channel assignment routine R7 This routine R7 is based on ON-RQ72 created in routine R5 and tone request file 6 created in routine R3.
Based on WG25, the frequency data and tone data corresponding to the newly pressed key are
This process executes the process of assigning to an empty channel. The execution process of this routine R7 will be explained below with reference to FIGS. 7 to 9. In addition, ON・RQ72 in FIG. 7 is ON・RQ in FIG.
It is the same as 72. When the program enters this routine R7, it first proceeds to step S1 shown in FIG.
A "1" bit on RQ72 is detected. This detection first shifts the slot corresponding to the first octave of ON/RQ 72 to the left (in Fig. 7) one bit at a time, and then shifts the slot corresponding to the first octave to the left (in Fig.
This is done by shifting the slots corresponding to the octave one bit at a time to the left, and then sequentially shifting the slots corresponding to the third and fourth octaves to the left, and when a "1" bit is detected ( Step S2) The program proceeds to step S3. In the example shown in FIG. 7, the "1" bit of the first octave C note is first detected, so at this point the program proceeds to step S3. In step S3,
Frequency data corresponding to the first octave C note is read from the frequency table written in the ROM 20 and transferred to the frequency data area 75 (preset) in the register 22. Next, when proceeding to step S4, the RAM
Busy key table 7 prepared on 21
The entry address (address X) of the slot 76a corresponding to the first octave C note of No. 6 is calculated, and the calculated entry address (address X) is temporarily stored in the register 22. Note that the busy key table 76 is
It is prepared in the RAM 21 and has 48 slots 76a, which are provided corresponding to each key.
It consists of 76b, 76c... next,
When proceeding to step S5, the channel assignment table (hereinafter abbreviated as CAT) 77
Detection of empty areas within is performed. here,
CAT77 will be explained. This CAT77 is prepared in advance in RAM21,
Consists of 15 areas, E ₁ , E ₂ ...E ₁₅ ,
Furthermore, these areas E ₁ , E _{2 .} . . E ₁₅ each have three slots a1, b1, c1, and 16 bits.
It is composed of a2, b2, c2, . This CAT77 is a table that shows which channel the musical tones currently being produced (including musical tones in decay state) are assigned to.As explained below, the pronunciation of musical tones corresponding to a certain key is assigned. and each area E ₁ , E ₂ ,...E ₁₅
headers, i.e. slots a1, a2, a
3 Busy key table 7 representing the corresponding key
6 entry addresses are registered, and used channels are registered in slots b1, c1, slots b2, c2, . . . . In this case, each bit in slots b and c is
Compatible with 32 channels of WG25,
Furthermore, it corresponds to the channel to which the pronunciation is assigned, and "1" is registered in the bit corresponding to the channel to which the pronunciation is further assigned. Now, when the program advances to step S5, an empty area is detected by searching the header of each area of CAT77. For example, if area E ₂ is detected as an empty area, the entry address (address Y) of area E ₂ is stored in the register 22, and the process proceeds to step S6. step
At S6, the number of "0" bits in the busy status register 78 provided in the register 22 is calculated. This busy status register 78 is a 32-bit register, each bit corresponding to 32 channels, and "1" is registered in the bit corresponding to the channel in use. Therefore, this step S6
The number of "0" bits calculated by is equal to the current number of empty channels. When the number of “0” bits (the number of empty channels) of the busy status register 78 is calculated in step S6,
The program proceeds to step S7, where the calculated number of "0" bits and the number of tone data registered in the tone request file 62 (see FIG. 4) (that is, the number stored in the header 62a of the tone request file 62) are calculated. number)
are compared. In this case, if the number of "0" bits is greater than or equal to the number of tone data (YES), the program proceeds to step S8. In step S8, the channel number of the empty channel is detected by searching for the "0" bit in the busy status register 78. In the example of FIG. 7, the second bit of slot 78a is first searched for "0", thereby detecting that the second channel is an empty channel. Note that in the busy status register 78, the first to the first slots of the slot 78a are
The 16 bits correspond to the 1st to 16th channels, respectively, and the 1st to 16th bits of slot 78b correspond to the 17th to 32nd channels, respectively. When an empty channel of the second channel is detected,
The program advances to step S9, and the channel number "2" is stored in the channel register 79. Next, when proceeding to step S10, the tone request file 62 is used.
Tone data in ROM 20 is transferred to tone data area 80 in register 22. That is, to explain the example of FIG. 4, first, the address D stored in the area 62c is read out into the register group 50, and then, based on this address D, the tone data i in the ROM 20 is read out.
+2 is read and transferred to tone data area 80. Next, the volume coefficient in area 62c is transferred to area 80. The program then proceeds to step S11, where the tone data is modified (timbre processing). This modification of the tone data is performed based on the information for timbre processing stored in the area 62b of the tone request file 62, and by this modification, the tone data is subjected to timbre processing (for example, addition of vibrato). Ru. The program then proceeds to step S12. In step S12, the entry address of the area corresponding to the second channel of the data port 18 (FIG. 2) is calculated based on the channel number of the empty channel ("2" in this case) stored in the channel register 79. Ru. Next, proceeding to step S13 (FIG. 9), the frequency data in the frequency data area 75, the tone data in the tone data area 80, and the volume coefficient are output to the corresponding area of the data boat 18 based on the entry address. .
Next, when proceeding to step S14, first, the bit corresponding to the second channel of the 32-bit start command register 81 provided in the register 22 (the second bit of the slot 81a) is set to "1".
The contents of this start command register 81 are then transferred to the data boat 18. In this way, the frequency daughter, tone data, volume coefficient, and start command transferred to the data port 18 are supplied to the corresponding channel (second channel) of the WG 25, so that the corresponding channel (second channel) of the WG 25 is A musical tone signal is formed based on the frequency data, tone data, etc. supplied from the data port 18 in the second channel. The program then steps
Proceeding to S15, based on the channel number "2" stored in the channel register 79, "1" is written in the second bit of slot b2 in area _E2 detected in step S5.
(Note that the second bit of this slot b2 is the second
Channel compatible. ) then step
Proceeding to S16, "1" is written into the second bit of the slot 78a of the busy status register 78 based on the channel number "2" in the channel register 79. And step S17
Proceed to. At step S17, it is determined whether all the tone data registered in the tone request file 62 have been allocated to channels.
In this case, since only the tone data registered in area 62c (FIG. 4) has been allocated, the determination result is "NO" and the program returns to step S8. and,
The process of steps S8 to S16 described above is repeated again. That is, the fourth channel is detected as an empty channel in step S8, the channel number "4" is stored in the channel register 79 in step S9, and the fourth channel is detected as an empty channel in step S9.
, the tone data i is sent from the tone data bank 65 based on the address B written in the area 62d of the tone request file 62.
is transferred to the read tone data area 80, the volume coefficient in the area 62d is transferred to the tone data area 80, and the tone data is modified in step S11.
In step S12, the area entry address corresponding to the fourth channel of the data port 18 is calculated, and in step S13, the frequency data in the frequency data area 75 and the tone data and volume coefficient in the tone data area 80 are output to the data port 18. In step S14, "1" is set in the bit corresponding to the fourth channel of the start command register 81, and as a result, the fourth channel of WG 25 is started.
In steps S15 and S16, "1" is written in the fourth bit of slot b2 of the CAT 77 and the fourth bit of slot 78a of the busy status register 78, and then the process advances to step S17. In step S17, it is determined again whether all tone data has been allocated, but in this case, the tone data corresponding to address C stored in area 62e of tone request file 62 has not yet been allocated. Since there is no,
The judgment result is "NO", so the program returns to step S8 again and continues from step S8 to step S8.
The process of S16 is executed again. When steps S8 to S16 are executed, tone data i+1 corresponding to address C stored in area 62e of tone request file 62 is assigned to the fifth channel, and WG2
The 5th channel of 5 has started, and CAT
77 slot b2 and the fifth bit of slot 78a of busy status register 78 are respectively written with "1". In this way, the channel assignment of the first octave/C note is completed, and the speaker 29 outputs three types of tones at the pitch of the C note of the first octave and corresponding to the tone data i, i+1, and i+2, respectively. musical tones are sounded simultaneously. Also, at this point, busy status register 7
8. “1” is registered in the bits corresponding to the 2nd, 4th, and 5th channels of the start command register 81, and also corresponds to the 2nd, 4th, and 5th channels of area E ₂ of CAT77. "1" is also registered in the bit. The program then proceeds to step S17, but the determination result at this step is naturally "YES", so the program proceeds to step S18. In this step S18,
Slot 7 of the busy key table 76 corresponding to the first octave/C note that has been assigned
The entry address (address X) of 6a is
CAT77 area E ₂ header (i.e.
is written to slot a2). Next, when the process advances to step S19, the entry address (address Y) of area _E2 is stored in the busy key table 7.
6 slot 76a. and,
Proceeding to step S20, the "1" bit corresponding to the first octave C note of ON.RQ 72 is set to "0". In this way, the first octave
All assignment processing based on the C sound is completed. Then the program returns to step S1 again and
A "1" bit on ON.RQ 72 is detected. In this case, in the example shown in FIG. 7, the "1" bit corresponding to the second octave D# tone is detected (step S2), and the program therefore proceeds to step S3, and the following is completely different from the case described above. A similar allocation process is performed. Then, when the second octave/D# note assignment process is completed, the "1" bit on the ON/RQ72 is detected again, and the next detected "1" bit (third octave/F# note) is A corresponding allocation process is performed. In this way, ON・RQ72
When all the processing of the above "1" bit is completed, the determination result in step S2 becomes "NO", and all the processing in routine R7 is completed. Next, step S21 in FIG. 8 will be explained. In the above explanation, the steps
The explanation has been given assuming that the judgment result in S7 is "YES", but this may also be "NO". That is, the busy status register 78
If the number of "0" bits in the tone request file 62 is smaller than the number registered in the header 62a of the tone request file 62, in other words, even if tone data is to be assigned to a channel, the number of empty channels is small and cannot be assigned. ,
The determination result at step S7 is "NO", and the program advances to step S21. This step
In S21, the channel number of the channel in the decay state is loaded into the dump command register 85 (see FIG. 10), which will be described later, and the contents of this dump command register 85 are output to the data boat 18, so that the WG 25 enters the decay state. This will force the channel to stop. Then, the routine exits from R7. When such processing is performed, the corresponding "1" bit of the busy status register 78 is set to "0" in the WG termination processing routine I3, thereby increasing the number of empty channels.
It becomes possible to allocate tone data. The meaning of this processing is that the sounding of the musical tone corresponding to the newly pressed key is given priority over the sounding of the musical tone in the decay state. Also,
To perform this process, a decay status register 82 provided within the register 22 and storing the channel number of the decay state is utilized. Next, the sixth bit "1" (marked with a circle) of slot b2 of CAT77 will be explained. The sixth bit "1" is not assigned when the first octave/C key was pressed this time, but was assigned when the same key was pressed last time. In other words, when the previously pressed key is released, the generation of the musical tone signal stops after a predetermined decay time in each channel to which that key is assigned (note that the generation of musical tone signals does not necessarily stop at the same time for each channel). (No), the "1" bit in CAT77 corresponding to the channel where musical tone signal generation has stopped is set to "0", but if the decay time of a certain allocated channel is long, the time when the same key is pressed this time in that channel is set to "0". The previous musical tone signal may continue to be generated until then. In this case, when the same key is pressed anew, the entry address (address Y) of area E ₂ of the CAT 77 is registered in slot 76 a of the busy key table 76, and a musical tone signal is not generated in area E ₂ . "1" remains in the bit (sixth bit of slot b2) corresponding to the continuing channel. Therefore, the channel assignment for the key pressed this time is registered in area E ₂ ,
Furthermore, the sixth bit of slot b2, which is "1", is also left as is in the same area _E2 . (For processing when the generation of musical tone signals stops, please refer to interrupt processing routine I3 described later.) In this embodiment, a channel is started for each tone data in the tone request file 62. However, it is also possible to start all channels at the same time. (10) Key-off channel management routine R8 This routine R8 consists of the OF・RQ73 created in routine R6, the busy key table 76 created in routine R7,
Based on CAT77, the musical tone corresponding to the released key (key whose pressed state is released) is erased. The execution process of this routine R6 will be explained below with reference to FIGS. 10 and 11. Note that OF·RQ 73 in FIG. 10 is the same as OF·RQ 73 in FIG. 6. When the program enters this routine R8, it first proceeds to step S1 shown in FIG.
A "1" bit on RQ73 is detected. This detection is based on ON・RQ72 mentioned above.
Detection of the upper “1” bit (step in Figure 8)
This is done in exactly the same way as in case S1). and,
In the example shown in FIG. 10, the "1" bit of the first octave A# note is first detected (step S2), and the program proceeds to step S3. In step S3, based on the position of the detected "1" bit (position on the OF/RQ 73), the entry address (address V) of the slot 76m corresponding to the first octave/A# note of the busy key table 76 is determined. ) is calculated. Next, in step S4, the contents of the slot 76m are read out based on the calculated entry address (address V) and transferred into the register group 50. In this case, slot 76
The content of m is the entry address (assumed to be address U) of area En, assuming that the channel assignment for the first octave/A# note is registered in area En of CAT77. Next, in step S5, the contents of slots bn and cn of area En are read out based on the contents of slot 76m (address U), and loaded into either Decay command register 84 or dump command register 85. Note that which one is loaded is controlled by a changeover switch provided in the operating section of this electronic organ. Then, when proceeding to step S6, the contents of the register (84 or 85) into which the contents of area En were loaded in step S5 are output to the data port 18, thereby producing the musical tone corresponding to the A# note in the first octave. The generation of musical tone signals of the channels to which are assigned (in the example shown in FIG. 10, the first, seventh, and eighth channels) is stopped. In this case, if the musical tone is loaded into the decay command register 84 in step S5, the musical tone is gradually erased as it decays, and if it is loaded into the dump command register 85, the musical tone is erased immediately. Next, when proceeding to step S7, the first octave A on OF RQ73
#The “1” bit of the note is erased and the step starts again.
Return to S1. Then, in step S1, the third
When the “1” bit of the octave/F note is detected, the judgment result in step S2 becomes “YES”.
As in the case described above, steps S3 to S6 are executed, and the musical tone signal of the channel to which the third octave/F note is assigned is stopped or put into a decay state. And step
At S7, the "1" bit of the third octave F note is deleted, and the process returns to step S1. In this way, when all the "1" bits on the OF.RQ 73 are processed, the determination result at step S2 becomes "NO" and the processing in this routine R8 is completed. (11) WG end processing routine I3 This interrupt processing routine I3 is executed when the generation of musical tone signals in the channel of WG25 has completely stopped (when the decay state has ended).
The main purpose is to set the bit corresponding to the channel in the busy status register 78 (Figs. 7 and 12) to "0". To make the same channel an empty channel, it is possible to newly assign the generation of a musical tone corresponding to another key. In other words, in response to one pressed key, multiple channels (see FIGS. 4 and 7 above)
Musical sound signals generated in three channels (in the example shown in the figure) do not necessarily stop at the same timing; for example, in the case of percussive sounds, they may stop even though a key is pressed. Sometimes. In such a case, if the channel whose musical tone generation has already stopped is made to wait until all musical tone signals of other channels corresponding to the same key have stopped, then
Channel usage becomes very inefficient. Taking these points into consideration, this electronic organ is provided with this interrupt processing routine I3 so that the channel in which musical tone generation has stopped can be immediately released to other keys. The execution process of this interrupt processing routine I3 will be explained below with reference to FIGS. 12 and 13. In the following explanation, it is assumed that the generation of musical tone signals has now stopped in the seventh channel, and that this seventh channel is registered in area _E6 of the CAT77. The generation of the musical tone signal stops in the seventh channel, and as a result, the interrupt signal INTR is sent from WG25.
3 occurs, the program first proceeds to step S1 shown in FIG. Then, in this step S1, the seventh bit (corresponding to the seventh channel) of the slot 78a of the busy status register 78 is set to "0", and the process then proceeds to step S2. This step S2 and the next step S3 are the 7th step registered in CAT77.
Erase a channel, specifically an area
Slot b6 corresponding to the 7th channel of E ₆
This is for erasing the 7th bit of "1". The reason why this process must be performed is as follows. For example, the musical tone signal that has been generated until now in the seventh channel is a percussive musical tone signal, and at the time when the generation of the musical tone signal has stopped, the key corresponding to the musical tone signal (referred to as the first key) is still Assume that the button remains pressed down. Then, when the musical tone signal stops, the busy status register 78
By setting the bit corresponding to the seventh channel to "0" (step S1), the musical tone corresponding to the newly pressed key (referred to as the next key) is generated before the first key is released. There is a possibility that it will be assigned to this seventh channel. If the above-mentioned process is not performed in such a case, when the first key is released, the contents of the CAT77 area corresponding to the first key are transferred to, for example, the Decay command register 84, and
Furthermore, the contents of this Decay command register 84 are output to the data port 18, and the seventh key is assigned to generate a musical tone corresponding to the next key.
This will also cause the channel to enter the day-care state. In order to eliminate such inconvenience, processing in steps S2 and S3 is required. Now, when the program advances to step S2, it is determined whether the header (slot a1) of area _E1 of CAT77 is "0". In this case, for example, if the answer is "NO" (not "0"), the program proceeds to step S3. In step S3, first slot b1 in area _E1 ,
Each bit of c1 and busy status register 7
A logical AND is performed with the corresponding bits of
stored within. As a result, if "1" is found in the seventh bit of slot b1, that "1" is erased. Note that in this example, the area
Since the 7th bit of slot b6 in area _E6 has a "1", there is no "1" in the 7th bit of slot b1 in area _E6 . Therefore, the result of the above AND operation is the same as the content of area _E1 before the operation. When the execution of step S3 is finished, step S4
Proceed to. In this step S4, area E ₁
It is determined whether the contents of (the contents of slots b1 and c1) are all "0" or not. In this case, the area
Since " ₁ " remains in E1, the judgment result is "NO" and the program proceeds to step S6. In this step S6, the above-mentioned step S3
It is determined whether the processing in step 1 has been performed in all areas (E ₁ to E ₁₅ ) whose headers are not "0". In this case, since only area E ₁ has been processed, the judgment result is "NO" and the program returns to step S2.
Return to In step S2, it is determined whether the header (slot a2) of area _E2 is "0" or not. In this case, if the header is set to "0"("YES"), the program proceeds to step S6. The judgment result at step S6 is "NO", and the program proceeds to step S2 again.
The header in Area E ₃ can be examined. Assume that the areas E ₁ , E ₂ , . . . are examined in this way, and the processing at step S3 is performed, and the header (slot a6) of area E ₆ is examined at step S2. In this case, the determination result in step S2 is "NO" and the process advances to step S3. Then, in this step S3, the busy status register 7
By logically ANDing the contents of 8 and the contents of slots b6 and c6 of area _E6 , the seventh bit "1" of slot b6 is erased (set to "0"). Next, when the program advances to step S4, it is determined whether or not the contents of slots b6 and c6 in area _E6 are all "0". In this case, if "1" remains, the program advances to step S6. proceed. In this way, when the processing for all areas _E1 to _E15 is completed, the program exits from this interrupt processing routine I3. Next, for example, the 8th channel has just ended,
Also, this 8th channel is the CAT77 area.
A case will be described in which the decay time of the musical tone signal registered in channel E ₇ and generated in the eighth channel is relatively long. When the interrupt signal INTR3 is generated and the program proceeds to step S1, "1" in the eighth bit (corresponding to the eighth channel) of the slot 78a of the busy status register 78 is erased.
Then, in the same way as above, area E ₁
~ _E6 is processed, the 8th bit of slot b7 in area _E7 is set to “1” in step S3.
is erased, and the process advances to step S4. Here, it is assumed that because the decay time of the musical tone signal of the eighth channel was relatively long, all other "1" bits in area _E7 had been erased by the time the eighth channel ended. In this case, by executing step S3, the determination result in step S4 becomes "YES", and the program proceeds to step S5. Then, in this step S5,
First, based on the entry address of the busy key table 76 (see FIG. 10) stored in the header of area E ₇ , the busy key table 7 specified by the entry address is
The contents of slot 6 are erased, and then the area
E ₇ header is deleted. In other words, the connection between the area and the busy key table is released.
Through this process, area _E7 is released for other keys. For reference, the ROMs explained so far
20, RAM 21 The contents of the register 22 are summarized in FIG. 14. Finally, the encoder switch used as the tone lever 38 shown in FIG. 2 will be explained using the principle diagram shown in FIG. 15. On the substrate 38a, there is a contact point 38b in which a conductor (indicated by diagonal lines in the figure) is formed continuously between the four regions a, b, c, and d shown in the figure, a conductor is formed in the regions a and c, and a conductor is formed in the region b. , a contact 38c in which an insulator (shown as a white part in the figure) is formed, and a contact 38d in which a conductor is formed in areas a and b and an insulator is formed in areas c and d are provided, respectively. Each area a, b on each of these contact points 38b, 38c, 38d,
A contact slider 38 made of a conductor can be slid in the direction of the arrow e or f in the figure while contacting these contacts 38b to 38d on c and d.
e is arranged. In addition, each of the contacts 38b,
38c and 38d are the corresponding terminals 38
It is connected to f, 38g, and 38h. Further, a scan strobe signal is applied to the terminal 38f. On the other hand, the terminals 38g and 38h are connected to the cathodes of the corresponding diodes D ₀ and D ₁ , respectively, and the anodes of the diodes D ₀ and D ₁ are connected to the corresponding buffer amplifiers B ₀ and D 1 , respectively.
Connected to the input end of _B1 . Furthermore, the anodes of the diodes D ₀ and D ₁ are also connected to the other ends of the resistors R ₀ and R ₁ whose one end is connected to the power supply +Vcc, and the output terminals of the buffer amplifiers B ₀ and B ₁ are connected to the signal. BIT<0> or BIT<1>
is configured so that it is output. The scan strobe signal is a signal for scanning the encoder switch described above, and in this embodiment is output from the address decoder 34 of FIG. 2 when the switch address signal is supplied to the address decoder 34 of FIG. Since the encoder switch is constructed as described above, for example, when the encoder switch shown in FIG. 15 is used as the tone lever 1 in FIG. It is set at the position of area d shown by. In other words, since the contacts 38c and 38d are electrically disconnected from the contact 38b in each region d, even if a scan strobe signal is input to the terminal 38f, the anodes of the diodes D ₀ and D ₁ are at the voltage level of the power supply +Vcc. Therefore, the output signal BIT<0> of each buffer amplifier _B0 , _B1 ,
Both output levels of BIT<1> are binary logic level "0". Therefore, the tone lever 1 is in the request line with a volume of 0. Although the encoder switch described above is used for changing the volume in four stages using a 2-bit binary code, it can easily be used for changing the volume in multiple stages using a binary code such as 3-bit or 4-bit. Furthermore, as an encoder switch, not only binary code but also other codes such as Gray code can be used. As described in detail above, according to the present invention, each element of the keyboard section, tone setting operator section, and musical tone generating section is connected to the control means by program control via a common information transmission path, and the control means is controlled. The means detects the operating states of the keyboard section and the tone setting operator section, respectively, and supplies a predetermined data signal determining the frequency and waveform to the musical tone generating section based on this detection.
Compared to conventional electronic musical instruments, it has the advantage of being simpler in configuration, and when converting the number of keys or tone levers, it can be handled simply by changing the program. This has the advantage that the number of can be easily changed.
Furthermore, since the present invention has the first means and the second means separately, it can be operated efficiently according to the type of operator (key, tone lever, etc.) and the general operation frequency of each operator. This has the effect of being able to detect the state.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a conventional digital electronic organ, FIGS. 2 to 14 are diagrams showing an embodiment of an electronic organ according to the present invention, and FIG. 2 is a diagram showing the overall configuration. 3A is a flowchart showing the flow of the program, FIG. 3B is a diagram showing the interrupt processing routine, and FIG. , the memory contents of the RAM 21 and the register 22, FIG. 5 is a flowchart of the above routine R3, and FIG. 6 is the key-on request file creation routine R shown in FIG. 3.
5. A diagram showing the stored contents of the RAM 21 and register 22 that are involved when executing the key-off request file creation routine R6. FIG. 7 shows the RAM 21 that is involved when executing the key-on channel assignment routine R7 shown in FIG. 3. FIGS. 8 and 9 are diagrams showing the contents of the register 22, and FIGS. 8 and 9 are flowcharts of the routine R7, and FIG.
21, a diagram showing the contents of the register 22, FIG. 11 is a flowchart of the above routine R8, and FIG. 12 is a diagram showing the contents of the RAM 21 and register 22 related to the execution of the WG termination processing routine I3 shown in FIG. 3. , FIG. 13 is a flowchart of the above routine I3, and FIG. 14 is a flowchart of the ROM 20, RAM 21,
FIG. 15 is a diagram illustrating the contents of the register 22 and data port 18, and is a diagram illustrating the configuration of an encoder switch used as a tone lever. 12... Assigner, 13... Musical sound generation section, 14
...control section, 15 ... calculation section, 19 ... calculation control section, 23 ... first storage section, 30 ... data bus, 37 ... address bus, 38 ... tone lever, 39 ... keyboard key , 45...Second storage unit (microprogram memory).

Claims (1)

[Claims] 1. A keyboard having a plurality of keys; a timbre setting operator section having a timbre setting operator for selecting and setting a timbre; and a musical tone generator having a plurality of musical tone generation channels that generate musical tone signals corresponding to the waveforms; a data memory that stores data defining the waveform; and the data memory that is assigned to the tone setting operator of the tone setting operator section. A timbre setting storage means for storing index information indicative of data defining the stored waveform, and the timbre setting storage means, the data memory, the musical tone generation section, the keyboard section, and the timbre setting operator section are respectively connected. a common information transmission path; and a control means that is connected to the common information transmission path and operates under program control; a first means for scanning a key to capture a signal indicating the state of each key and detecting a pressed key; a second means for detecting the operation state of the tone setting controller; and a second means for detecting the operating state of the tone setting operator; Data regarding the waveform is supplied to the musical tone generating section via the common information transmission path for each musical tone generation channel, and is referenced according to the operating state detected by the second means. and third means for forming data regarding the waveform by reading data defining the waveform from the data memory based on the index information stored in the tone color setting storage means, whereby the keyboard section An electronic musical instrument, characterized in that it generates a musical tone with a frequency and tone corresponding to a key pressed and a tone setting operator operated.