JPH0474730B2 - - Google Patents
Info
- Publication number
- JPH0474730B2 JPH0474730B2 JP10863583A JP10863583A JPH0474730B2 JP H0474730 B2 JPH0474730 B2 JP H0474730B2 JP 10863583 A JP10863583 A JP 10863583A JP 10863583 A JP10863583 A JP 10863583A JP H0474730 B2 JPH0474730 B2 JP H0474730B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- terminal
- current
- base
- control transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 24
- 230000003321 amplification Effects 0.000 description 9
- 238000003199 nucleic acid amplification method Methods 0.000 description 9
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/573—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
- G05F1/5735—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector with foldback current limiting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Emergency Protection Circuit Devices (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は定電圧電源回路おける電流制限保護回
路に係り、特に過大電流の制限および負荷端の短
絡を検出して通常の制限電流より数分の１に押
へ、制御トランジスタを保護することができる電
流制限保護回路に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a current limit protection circuit in a constant voltage power supply circuit, and in particular, the present invention relates to a current limit protection circuit in a constant voltage power supply circuit, and in particular to a current limit protection circuit for limiting excessive current and detecting a short circuit at the load end. The present invention relates to a current limit protection circuit that can protect a control transistor.
従来のこの種の保護回路の一例を第１図に示し
説明すると、図において、１は電源が印加される
電源入力端子、３は第１の制御用PNPトランジ
スタ（以下、第１の制御トランジスタと呼称す
る）で、そのエミツタは電源入力端子１に接続さ
れ、コレクタは定電圧出力端子１９に接続され、
ベースは抵抗２を介してエミツタに接続されてい
る。６，７はベースおよびエミツタをそれぞれ共
通接続した第３，第４のPNPトランジスタで、
そのエミツタは第１の制御トランジスタ３のベー
スと抵抗２の接続点に接続され、トランジスタ６
のベースとコレクタは共通接続されてカレントミ
ラー回路を構成している。８，９はエミツタを共
通接続し、その接続点をエミツタ抵抗１０を介し
て接地したNPNトランジスタ（以下、誤差増幅
用トランジスタと呼称する）で、これらは誤差増
幅回路１１を構成している。そして、この誤差増
幅用トランジスタ８のコレクタはトランジスタ６
のコレクタに接続され、ベースは基準電圧源５に
接続され、また、誤差増幅用トランジスタ９のコ
レクタはトランジスタ７のコレクタに接続され、
ベースは出力端子１９と接地１８間に直列接続さ
れた第１の抵抗１６と第２の抵抗１７の接続点で
ある出力電圧調整端子２０に接続されている。
An example of a conventional protection circuit of this kind is shown in FIG. 1 and explained. In the figure, 1 is a power input terminal to which power is applied, and 3 is a first control PNP transistor (hereinafter referred to as the first control transistor). ), its emitter is connected to the power input terminal 1, its collector is connected to the constant voltage output terminal 19,
The base is connected to the emitter via resistor 2. 6 and 7 are third and fourth PNP transistors whose bases and emitters are commonly connected, respectively.
Its emitter is connected to the connection point between the base of the first control transistor 3 and the resistor 2, and the transistor 6
The base and collector of are commonly connected to form a current mirror circuit. 8 and 9 are NPN transistors (hereinafter referred to as error amplification transistors) whose emitters are commonly connected and whose connection point is grounded via an emitter resistor 10, and these constitute an error amplification circuit 11. The collector of this error amplification transistor 8 is connected to the transistor 6.
The collector of the error amplification transistor 9 is connected to the collector of the transistor 7, the base of which is connected to the reference voltage source 5, and the collector of the error amplification transistor 9 is connected to the collector of the transistor 7.
The base is connected to an output voltage adjustment terminal 20 which is a connection point between a first resistor 16 and a second resistor 17 connected in series between an output terminal 19 and a ground 18.
１２，１３はダーリントン接続された第２の制
御用NPNトランジスタ（以下、第２の制御トラ
ンジスタと呼称する）で、その共通接続されたコ
レクタは第１の制御トランジスタ３のベースに接
続され、ベースはトランジスタ７のコレクタに接
続され、エミツタは電流検出抵抗１５を介して接
地されている。１４は電流制限検出用のNPNト
ランジスタ（以下、電流制限検出トランジスタと
呼称する）で、そのコレクタは第２の制御トラン
ジスタ１２のベースに接続され、ベースおよびエ
ミツタは上記電流検出抵抗１５の両端に接続され
ている。２１は負荷端である定電圧出力端子１９
と接地間に挿入された負荷である。 12 and 13 are Darlington-connected second control NPN transistors (hereinafter referred to as second control transistors), whose commonly connected collectors are connected to the base of the first control transistor 3; It is connected to the collector of the transistor 7, and its emitter is grounded via the current detection resistor 15. 14 is an NPN transistor for current limit detection (hereinafter referred to as a current limit detection transistor), the collector of which is connected to the base of the second control transistor 12, and the base and emitter connected to both ends of the current detection resistor 15. has been done. 21 is a constant voltage output terminal 19 which is a load end.
This is the load inserted between the ground and ground.
このように構成された回路の動作は一般によく
知られているので、その詳細な説明は省略する
が、電流制限検出トランジスタ１４のベース・エ
ミツタ間に電流検出抵抗１５を接続することによ
り、この電流検出抵抗１５に流れる電流によつて
発生した電圧で電流制限検出トランジスタ１４を
オンさせ、第２の制御トランジスタ１２，１３へ
流れる電流を押え、ある設定値以上の電流が流れ
ないように電流制限保護をかけている。 Since the operation of the circuit configured in this way is generally well known, a detailed explanation thereof will be omitted, but by connecting the current detection resistor 15 between the base and emitter of the current limit detection transistor 14, this current The voltage generated by the current flowing through the detection resistor 15 turns on the current limit detection transistor 14, suppresses the current flowing to the second control transistors 12 and 13, and provides current limit protection so that the current does not exceed a certain set value. is being applied.
しかしながら、このような電流制限保護回路に
おいては、電流制限は可能であるが、負荷端（定
電圧出力端子１９と接地１８間）短絡のような異
常な状態でも同じ電流制限レベルとなり、制御ト
ランジスタ３のコレクタには、その制限の設定値
の電流のの電流増幅率hFE倍の電流が流れること
になり、非常に大きな電力が印加され、破壊する
という欠点があつた。 However, in such a current limit protection circuit, although current limit is possible, even in an abnormal state such as a short circuit at the load end (between constant voltage output terminal 19 and ground 18), the current limit level remains the same, and the control transistor 3 A current that is equal to the current amplification factor h FE times the current of the limit set value flows through the collector of the collector, which has the drawback that an extremely large amount of power is applied, leading to destruction.
本発明は以上の点に鑑み、このような問題を解
決すると共にかかる欠点を除去すべくなされたも
ので、その目的は部品点数を増加することなく電
流制限を負荷端短絡という異常な状態に対して通
常の電流制限値の数分の１のレベルに下げ、制御
トランジスタを保護することができる電流制限保
護回路を提供することにある。
In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The purpose of the present invention is to improve current limiting to prevent abnormal conditions such as short-circuits at the load end without increasing the number of parts. An object of the present invention is to provide a current limit protection circuit that can protect a control transistor by reducing the current limit value to a fraction of the normal current limit value.
このような目的を達成するため、本発明は電流
制限検出トランジスタのエミツタを出力電圧調整
端子に接続し、コレクタを第２の制御トランジス
タ１２のベースに接続し、ベースを電流検出抵抗
に接続するようにしたものである。 To achieve this purpose, the present invention provides a current limit sensing transistor whose emitter is connected to the output voltage adjustment terminal, whose collector is connected to the base of the second control transistor 12, and whose base is connected to the current sensing resistor. This is what I did.
以下、図面に基づき本発明の実施例を詳細に説
明する。
Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第２図は本発明による電流制限保護回路の一実
施例を示す回路図である。 FIG. 2 is a circuit diagram showing one embodiment of the current limit protection circuit according to the present invention.
この第２図において第１図と同一符号のものは
相当部分を示し、２２は電流制限検出用NPNト
ランジスタ（以下、電流制限検出トランジスタと
呼称する）で、そのコレクタは第２の制御トラン
ジスタ１２のベースに接続され、エミツタは出力
電圧調整端子２０に接続され、ベースは第２の制
御トランジスタ１３のエミツタと接地間に接続さ
れた電流検出抵抗１５との接続点に接続されてい
る。 In FIG. 2, the same reference numerals as in FIG. The emitter is connected to the output voltage adjustment terminal 20, and the base is connected to a connection point between the emitter of the second control transistor 13 and a current detection resistor 15 connected between the ground.
つぎにこの第２図に示す実施例の動作を説明す
る。 Next, the operation of the embodiment shown in FIG. 2 will be explained.
いま、基準電圧源５の電圧Vrを1.2V，第２の
制御トランジスタ１３の電流制限値ILnaxを
100mAとすると、電流検出抵抗１５の値は、電
流制限検出トランジスタ２２がオンするに必要な
ベース・エミツタ電圧VBE＝500mVとし、誤差増
幅用トランジスタ８，９のベース・エミツタ電圧
が等しいとすると、
Vr＋VBE／ILnax＝1.2V＋500mV／100mA＝17Ω
となる。この電流検出抵抗１５の値１７Ωにより
過大電流が防止され、100mAで電流制限検出ト
ランジスタ２がオンし、第２の制御トランジスタ
１２，１３へ流れ込む電流を押え、同トランジス
タ１３から流れ出る電流が100mAで保持される
ことになる。 Now, the voltage Vr of the reference voltage source 5 is 1.2V, and the current limit value I Lnax of the second control transistor 13 is
Assuming that the value of the current detection resistor 15 is 100 mA, the base-emitter voltage V BE required to turn on the current limit detection transistor 22 is 500 mV, and the base-emitter voltages of the error amplification transistors 8 and 9 are equal. Vr + V BE /I Lnax = 1.2V + 500mV/100mA = 17Ω. The current detection resistor 15's value of 17Ω prevents excessive current, and the current limit detection transistor 2 turns on at 100mA, suppresses the current flowing into the second control transistors 12 and 13, and maintains the current flowing from the transistor 13 at 100mA. will be done.
また、負荷端が短絡された場合には、出力電圧
調整端子２０がほぼ接地電位（アース電位）に下
がるので、電流制限検出トランジスタ２２のエミ
ツタ電位も下がることになり、電流検出抵抗１５
の電圧降下は500mV程度で、電流制限検出トラ
ンジスタ２２を十分オン状態にすることができる
ことになる。すなわち、負荷端短絡時の電流制限
値は
500mV／17Ω＝29.4mA
と、通常の過大電流制限値の100mAの1/3程度に
押えられるので、第１の制御トランジスタ３のコ
レクタ電流も第１図に示す従来の回路に比して押
えられるという利点がある。そして、基準電圧源
５の電圧Vr値が大きいほど、その利点が大きい。
すなわち、通常の電流制限値と負荷端短絡時の電
流制限値との比率を大きくすることができる。 Furthermore, when the load end is short-circuited, the output voltage adjustment terminal 20 drops to approximately the ground potential (earth potential), so the emitter potential of the current limit detection transistor 22 also drops, and the current detection resistor 15
The voltage drop is approximately 500 mV, which is sufficient to turn on the current limit detection transistor 22. In other words, the current limit value when the load end is short-circuited is 500mV/17Ω=29.4mA, which is about 1/3 of the normal overcurrent limit value of 100mA, so the collector current of the first control transistor 3 is also as shown in Figure 1. It has the advantage of being more compact than the conventional circuit shown in FIG. The larger the voltage Vr value of the reference voltage source 5, the greater the advantage.
That is, it is possible to increase the ratio between the normal current limit value and the current limit value when the load end is short-circuited.
なお、上記実施例においては、電流制限検出ト
ランジスタ２２のコレクタを第２の制御トランジ
スタ１２のベースへ接続した場合を例にとつて説
明したが、本発明はこれに限定されるものではな
く、これをそのエミツタへ接続しても同様の利点
が得られる。また、電流検出抵抗１５に直列にダ
イオードを接続することにより、負荷端短絡時の
電流をを最小限に押えることもできる。 In the above embodiment, the collector of the current limit detection transistor 22 is connected to the base of the second control transistor 12, but the present invention is not limited to this. A similar advantage can be obtained by connecting a to its emitter. Furthermore, by connecting a diode in series with the current detection resistor 15, the current when the load end is short-circuited can be suppressed to a minimum.
以上説明したように、本発明によれば、複雑な
手段を用いることなく、電流制限検出トランジス
タのエミツタを出力電圧調整端子に、コレクタを
第２の制御トランジスタのベースに、ベースを電
流検出抵抗にそれぞれ接続するという接続変更の
みで部品点数を増やさない簡単な回路構成によつ
て、電流制限を負荷端短絡という異常な状態に対
して通常の電流制限値の数分の１のレベルに下げ
ることができ、これに伴つて制御トランジスタを
保護することができるので、実用上の効果は極め
て大である。また、構成の簡素化にともなつて電
流制限保護回路を安価に提供することができると
いう点において極めて有効である。
As explained above, according to the present invention, the emitter of the current limit detection transistor can be used as the output voltage adjustment terminal, the collector can be used as the base of the second control transistor, and the base can be used as the current detection resistor, without using complicated means. By using a simple circuit configuration that does not increase the number of parts by simply changing the connections, the current limit can be lowered to a level that is a fraction of the normal current limit value in the case of an abnormal condition such as a short circuit at the load end. This has an extremely large practical effect because the control transistor can be protected accordingly. Further, it is extremely effective in that the current limit protection circuit can be provided at low cost due to the simplified configuration.
第１図は従来の電流制限保護回路の一例を示す
回路図、第２図は本発明による電流制限保護回路
の一実施例を示す回路図である。
１……電源入力端子、３……第１の制御用
PNPトランジスタ、５……基準電圧源、６……
第３のトランジスタ、７……第４のトランジス
タ、８，９……誤差増幅用トランジスタ、１０…
…エミツタ抵抗、１１……誤差増幅回路、１２，
１３……第２の制御用NPNトランジスタ、１５
……電流検出用抵抗、１６……第１の抵抗、１７
……第２の抵抗、１８……接地、１９……定電圧
出力端子、２０……出力電圧調整端子、２１……
負荷、２２……電流制限検出用NPNトランジス
タ。
FIG. 1 is a circuit diagram showing an example of a conventional current limit protection circuit, and FIG. 2 is a circuit diagram showing an embodiment of the current limit protection circuit according to the present invention. 1...Power input terminal, 3...For first control
PNP transistor, 5... Reference voltage source, 6...
Third transistor, 7... Fourth transistor, 8, 9... Error amplification transistor, 10...
...Emitter resistance, 11...Error amplification circuit, 12,
13...Second control NPN transistor, 15
... Current detection resistor, 16 ... First resistor, 17
... Second resistor, 18 ... Ground, 19 ... Constant voltage output terminal, 20 ... Output voltage adjustment terminal, 21 ...
Load, 22... NPN transistor for current limit detection.
Claims (1)
ツタ・コレクタを直列に接続した第１の制御トラ
ンジスタと、第３のトランジスタのベースとコレ
クタを第４のトランジスタのベースに接続したカ
レントミラー回路と、一方の入力を基準電圧源
に、他方の入力を定電圧出力端子と接地間に直列
接続された第１の抵抗と第２の抵抗の接続点であ
る出力電圧調整端子にそれぞれ接続された差動増
幅器と、その差動増幅器にバイアス電流を供給す
るための抵抗とで構成される誤差増幅器を有し、
この誤差増幅器の出力となる前記カレントミラー
回路の出力端子より次段の増幅器として用いる第
２の制御トランジスタのベース端子に電流を駆動
し、この第２の制御トランジスタのコレクタ端子
を前記第１の制御トランジスタのベース端子に接
続して、そのベース端子を制御することにより電
源入力端子へ加えられる入力電圧を一定に保持し
て定電圧出力端子へ出力するようにした定電圧電
源回路において、エミツタを前記出力電圧調整端
子に、コレクタを前記第２の制御トランジスタの
ベースに、ベースを前記第２の制御トランジスタ
のエミツタにそれぞれ接続した電流制限検出用ト
ランジスタと、さらに前記第２の制御トランジス
タのエミツタと接地間に接続した電流検出抵抗を
備えたことを特徴とする電流制限保護回路。1. A first control transistor whose emitter and collector are connected in series between a power supply input terminal and a constant voltage output terminal, and a current mirror circuit whose base and collector of a third transistor are connected to the base of a fourth transistor. , one input is connected to the reference voltage source, and the other input is connected to the output voltage adjustment terminal, which is the connection point of the first resistor and second resistor connected in series between the constant voltage output terminal and ground. an error amplifier including a dynamic amplifier and a resistor for supplying a bias current to the differential amplifier;
A current is driven from the output terminal of the current mirror circuit, which is the output of the error amplifier, to the base terminal of a second control transistor used as the next stage amplifier, and the collector terminal of the second control transistor is connected to the first control transistor. In a constant voltage power supply circuit that is connected to the base terminal of a transistor and controls the base terminal, the input voltage applied to the power supply input terminal is held constant and outputted to the constant voltage output terminal. A current limit detection transistor whose collector is connected to the base of the second control transistor and whose base is connected to the emitter of the second control transistor is connected to the output voltage adjustment terminal, and further connected to the emitter of the second control transistor and grounded. A current limit protection circuit comprising a current detection resistor connected between the circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10863583A JPS60520A (en) | 1983-06-15 | 1983-06-15 | Current limit protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10863583A JPS60520A (en) | 1983-06-15 | 1983-06-15 | Current limit protecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60520A JPS60520A (en) | 1985-01-05 |
| JPH0474730B2 true JPH0474730B2 (en) | 1992-11-27 |
Family
ID=14489792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10863583A Granted JPS60520A (en) | 1983-06-15 | 1983-06-15 | Current limit protecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60520A (en) |
-
1983
- 1983-06-15 JP JP10863583A patent/JPS60520A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60520A (en) | 1985-01-05 |
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