JPH0475420U - - Google Patents
Info
- Publication number
- JPH0475420U JPH0475420U JP11906890U JP11906890U JPH0475420U JP H0475420 U JPH0475420 U JP H0475420U JP 11906890 U JP11906890 U JP 11906890U JP 11906890 U JP11906890 U JP 11906890U JP H0475420 U JPH0475420 U JP H0475420U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- state driver
- resistance value
- predetermined number
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は、本考案の一実施例に係るサインコン
バータの構成を示す回路図、第２図は、この実施
例の動作を示すタイミングチヤート図、第３図は
、一従来例に係るサインコンバータの構成を示す
回路図である。
１０……制御回路、１２……ローパスフイルタ
、Ｂ１，Ｂ２，Ｂ３，Ｂ４……スリーステートド
ライバ、Ｒ１，Ｒ２，Ｒ６……抵抗、Ｖ１……直
流電源の電圧。
FIG. 1 is a circuit diagram showing the configuration of a sine converter according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of this embodiment, and FIG. 3 is a sine converter according to a conventional example. FIG. 10... Control circuit, 12... Low pass filter, B1, B2, B3, B4... Three-state driver, R1, R2, R6... Resistor, V1... DC power supply voltage.
Claims (1)
ステートドライバと、 それぞれ異なる抵抗値を有し、一端がそれぞれ
各スリーステートドライバの出力側に接続され、
他端が集合結線される所定個数の分圧抵抗と、 一端が分圧抵抗の集合結線点に、他端が直流電
源に接続され、自己の抵抗値及びオンしているス
リーステートドライバに係る分圧抵抗の抵抗値に
より直流電源の電圧を分圧するプルアツプ抵抗と
、 各スリーステートドライバに対応した制御パル
スを含む所定個数の信号を所定のタイミングで発
生させ、これらの信号をそれぞれスリーステート
ドライバに供給することにより、分圧抵抗及びプ
ルアツプ抵抗により分圧して得られる電圧が正弦
波に近似した階段波となるよう所定順序でスリー
ステートドライバをオンさせる制御回路と、 前記階段波を低域濾波して正弦波の電圧を出力
するローパスフイルタと、 を有することを特徴とするサインコンバータ。[Claims for Utility Model Registration] A predetermined number of three-state drivers that turn on in response to control pulses, each having a different resistance value, one end of which is connected to the output side of each three-state driver,
A predetermined number of voltage dividing resistors whose other ends are connected collectively, one end connected to the collective connection point of the voltage dividing resistors, and the other end connected to a DC power supply, and whose resistance value and the voltage of the turned-on three-state driver are Generates a predetermined number of signals at a predetermined timing, including a pull-up resistor that divides the voltage of the DC power supply according to the resistance value of the piezoresistor, and a control pulse corresponding to each three-state driver, and supplies these signals to each three-state driver. A control circuit turns on the three-state driver in a predetermined order so that the voltage obtained by dividing the voltage by the voltage dividing resistor and the pull-up resistor becomes a staircase wave approximating a sine wave; and a control circuit that low-pass filters the staircase wave. A sine converter comprising: a low-pass filter that outputs a sine wave voltage;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11906890U JPH0543527Y2 (en) | 1990-11-13 | 1990-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11906890U JPH0543527Y2 (en) | 1990-11-13 | 1990-11-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0475420U true JPH0475420U (en) | 1992-07-01 |
| JPH0543527Y2 JPH0543527Y2 (en) | 1993-11-02 |
Family
ID=31867049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11906890U Expired - Lifetime JPH0543527Y2 (en) | 1990-11-13 | 1990-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0543527Y2 (en) |
-
1990
- 1990-11-13 JP JP11906890U patent/JPH0543527Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543527Y2 (en) | 1993-11-02 |
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