JPH0476030U - - Google Patents

Info

Publication number
JPH0476030U
JPH0476030U JP1990119597U JP11959790U JPH0476030U JP H0476030 U JPH0476030 U JP H0476030U JP 1990119597 U JP1990119597 U JP 1990119597U JP 11959790 U JP11959790 U JP 11959790U JP H0476030 U JPH0476030 U JP H0476030U
Authority
JP
Japan
Prior art keywords
semiconductor
utility
model registration
semiconductor device
back sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990119597U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990119597U priority Critical patent/JPH0476030U/ja
Publication of JPH0476030U publication Critical patent/JPH0476030U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例としての半導体装置
の断面図である。第２図は従来例の半導体素子の
断面図である。 １，５，２１……半導体基板、２……半導体基
板１上の表面電極、３……半導体基板１の裏面電
極、４……半導体基板１のバイアホール、６，７
……半導体基板５上の表面電極、８……半導体基
板５の裏面電極、９……半導体基板１のバイアホ
ール、１０，１２，２６……パツケージ電極、１
１，２７……ワイヤ、１３，２５……パツケージ
、２２……半導体基板２１上の表面電極、２３…
…半導体基板２１の裏面電極、２４…半田等の接
着材料。 FIG. 1 is a sectional view of a semiconductor device as an embodiment of the present invention. FIG. 2 is a sectional view of a conventional semiconductor element. 1, 5, 21... Semiconductor substrate, 2... Surface electrode on semiconductor substrate 1, 3... Back electrode on semiconductor substrate 1, 4... Via hole in semiconductor substrate 1, 6, 7
...Surface electrode on semiconductor substrate 5, 8...Back surface electrode of semiconductor substrate 5, 9... Via hole of semiconductor substrate 1, 10, 12, 26... Package electrode, 1
1, 27...Wire, 13, 25...Package, 22...Surface electrode on semiconductor substrate 21, 23...
... Back electrode of semiconductor substrate 21, 24... Adhesive material such as solder.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体基板の中に、表裏を貫通するバイア
ホールを有し、かつ異なる機能を持つ半導体ペレ
ツト一組を、それぞれのペレツトの裏面電極を共
通電極として上下・裏表に貼り合わせて用いるこ
とを特徴とする半導体装置。 ２ 実用新案登録請求の範囲の記載において、半
導体ペレツト一組を、３個以上の多層積層に形成
したことを特徴とする半導体装置。[Claims for Utility Model Registration] (1) A set of semiconductor pellets each having a via hole penetrating the front and back sides and having different functions in a semiconductor substrate, with the back surface electrode of each pellet as a common electrode, A semiconductor device characterized by being used by bonding the front and back sides together. 2. A semiconductor device as claimed in the claims for utility model registration, characterized in that a set of semiconductor pellets is formed into a multilayer stack of three or more.
JP1990119597U 1990-11-14 1990-11-14 Pending JPH0476030U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990119597U JPH0476030U (en) 1990-11-14 1990-11-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990119597U JPH0476030U (en) 1990-11-14 1990-11-14

Publications (1)

Publication Number Publication Date
JPH0476030U true JPH0476030U (en) 1992-07-02

Family

ID=31867543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990119597U Pending JPH0476030U (en) 1990-11-14 1990-11-14

Country Status (1)

Country Link
JP (1) JPH0476030U (en)

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