JPH0476714U - - Google Patents
Info
- Publication number
- JPH0476714U JPH0476714U JP12061190U JP12061190U JPH0476714U JP H0476714 U JPH0476714 U JP H0476714U JP 12061190 U JP12061190 U JP 12061190U JP 12061190 U JP12061190 U JP 12061190U JP H0476714 U JPH0476714 U JP H0476714U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- type flip
- signal
- detection circuit
- direction signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Stereo-Broadcasting Methods (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は、従来のアツプダウンカウンタを備えたバ
ランス調整回路、第３図イ乃至リ及び第４図イ乃
至リは、第１図の説明に供する為の波形図である
。
２７……方向信号発生回路、２８……検出回路
、３２……計数回路、３５……第５Ｄ−ＦＦ。
FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a conventional balance adjustment circuit equipped with an up-down counter, and FIGS. FIG. 3 is a waveform diagram for explaining the figure. 27...Direction signal generation circuit, 28...Detection circuit, 32...Counting circuit, 35...5th D-FF.
Claims (1)
方向信号を発生する方向信号発生回路と、 該方向信号発生回路からの方向信号の状態変移を
検出する検出回路と、 該検出回路の検出出力を計数する計数回路と、 該計数回路のカウントアツプ信号を出力する出
力回路と、 から成り、前記アツプダウンカウンタのロツク状
態を検出することを特徴とするロツク検出回路。 (2) 前記検出回路は、 前記方向信号がデータ端子に、クロツク信号が
クロツク端子に印加される第１Ｄ型フリツプフロ
ツプと、 該第１Ｄ型フリツプフロツプの出力信号がデー
タ端子に、前記クロツク信号がクロツク端子に印
加される第２Ｄ型フリツプフロツプと、 前記第１及び第２Ｄ型フリツプフロツプの出力
信号の論理積を取るゲート手段と、 から成ることを特徴とする請求項第１項記載のロ
ツク検出回路。[Claims for Utility Model Registration] (1) A direction signal generation circuit that generates a direction signal according to the counting direction of an up-down counter, a detection circuit that detects a state change of the direction signal from the direction signal generation circuit, A lock detection circuit comprising: a counting circuit that counts the detection output of the detection circuit; and an output circuit that outputs a count-up signal of the counting circuit, and detects a lock state of the up-down counter. (2) The detection circuit includes a first D-type flip-flop to which the direction signal is applied to a data terminal and a clock signal to a clock terminal; an output signal of the first D-type flip-flop is applied to a data terminal, and the clock signal is applied to a clock terminal. 2. The lock detection circuit according to claim 1, further comprising: a second D-type flip-flop applied to said first and second D-type flip-flops; and gate means for performing an AND operation of the output signals of said first and second D-type flip-flops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12061190U JPH0476714U (en) | 1990-11-16 | 1990-11-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12061190U JPH0476714U (en) | 1990-11-16 | 1990-11-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0476714U true JPH0476714U (en) | 1992-07-03 |
Family
ID=31868510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12061190U Pending JPH0476714U (en) | 1990-11-16 | 1990-11-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0476714U (en) |
-
1990
- 1990-11-16 JP JP12061190U patent/JPH0476714U/ja active Pending
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