JPH0476783B2 - - Google Patents

Info

Publication number
JPH0476783B2
JPH0476783B2 JP59197488A JP19748884A JPH0476783B2 JP H0476783 B2 JPH0476783 B2 JP H0476783B2 JP 59197488 A JP59197488 A JP 59197488A JP 19748884 A JP19748884 A JP 19748884A JP H0476783 B2 JPH0476783 B2 JP H0476783B2
Authority
JP
Japan
Prior art keywords
metal foil
foil
circuit
film
electrodeposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59197488A
Other languages
Japanese (ja)
Other versions
JPS6174842A (en
Inventor
Koji Ookawa
Sadao Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Cable Industries Ltd
Original Assignee
Mitsubishi Cable Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Cable Industries Ltd filed Critical Mitsubishi Cable Industries Ltd
Priority to JP19748884A priority Critical patent/JPS6174842A/en
Publication of JPS6174842A publication Critical patent/JPS6174842A/en
Publication of JPH0476783B2 publication Critical patent/JPH0476783B2/ja
Granted legal-status Critical Current

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Landscapes

  • Laminated Bodies (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Non-Insulated Conductors (AREA)

Description

【発明の詳細な説明】 〔従来技術〕 本発明は、回路用絶縁金属箔の製法に関するも
のである。従来フレキシブルプリント回路用に使
用されている基板材料として、ポリイミドフイル
ム又はポリエステルフイルムに銅箔を貼り合わせ
てなるものが一般に用いられている。しかし、こ
れらの基板材料は導電性金属箔、たとえば、銅箔
に接着剤を介して上記フイルム材料を貼り合わせ
た後、接着剤を完全に硬化し、更に、要求特性を
満足させるため、長時間にわたる(6〜10時間)
ポストキユアーが必要となる。
DETAILED DESCRIPTION OF THE INVENTION [Prior Art] The present invention relates to a method for manufacturing an insulating metal foil for circuits. As a substrate material conventionally used for flexible printed circuits, a material made by bonding copper foil to a polyimide film or a polyester film is generally used. However, after bonding the film material to a conductive metal foil, such as a copper foil, using an adhesive, these substrate materials require a long period of time to fully cure the adhesive and satisfy the required characteristics. (6-10 hours)
Post cure is required.

これらラミネート法にかわる方法として、本発
明者等は金属箔の片面に電着により絶縁層を形成
し、回路用絶縁金属箔を製造する方法を提案して
いる。この方法によれば金属箔の片面に任意の膜
厚がコーテイングできしかも、従来のラミネート
法において見られた長時間を要するポストキユア
ーが必要ないため、生産効率が著しく改善される
ものである。
As an alternative to these laminating methods, the present inventors have proposed a method of manufacturing an insulating metal foil for circuits by forming an insulating layer on one side of a metal foil by electrodeposition. According to this method, one side of the metal foil can be coated with any desired thickness, and the time-consuming post-curing required in conventional lamination methods is not required, so production efficiency is significantly improved.

しかし、電着法で絶縁を形成する方法において
は、焼付工程において、皮膜の焼付を行うため、
焼付時に、皮膜の架橋反応にともなつて生ずる残
留応力が焼付後の皮膜中に存在するため、回路を
書き、エツチングすると、金属が除去され、残つ
た皮膜がわずかに収縮し、高密度パターンの場
合、寸法が合わなくなる欠点があつた。殊に金属
箔の厚さが150μm以下、殊に100μm以下の場合に
皮膜の収縮が大きかつた。
However, in the method of forming insulation by electrodeposition, the film is baked in the baking process, so
Residual stress generated by the crosslinking reaction of the film during baking is present in the film after baking, so when the circuit is written and etched, the metal is removed and the remaining film shrinks slightly, creating a dense pattern. In this case, there was a drawback that the dimensions did not match. In particular, when the thickness of the metal foil was 150 μm or less, especially 100 μm or less, the shrinkage of the film was large.

〔発明の要旨〕[Summary of the invention]

本発明は、これら電着により片面絶縁金属箔を
製造する方法において、従来みられた寸法安定性
における欠点を改良する目的でなされたものであ
る。
The present invention was made for the purpose of improving the conventional drawbacks in dimensional stability in methods for manufacturing single-sided insulated metal foils by electrodeposition.

即ち、金属箔の片面に電着により絶縁してなる
片面絶縁金属箔の絶縁面に金属箔を貼り合わせて
なる回路用絶縁金属箔をつくる方法である。
That is, this is a method of making an insulated metal foil for a circuit by bonding a metal foil to the insulating surface of a single-sided insulated metal foil that is insulated by electrodeposition on one side of the metal foil.

本発明によれば、従来、エツチング時又は、半
田付時に見られた、収縮による寸法法安定性の悪
さもなくラミネート法によるポリイミドタイプの
フレキシブルプリント回路と同等の特性を有し、
かつ、金属箔を裏面に貼り合わせたことにより、
熱伝導性が向上するものである。
According to the present invention, there is no poor dimensional stability due to shrinkage that was conventionally seen during etching or soldering, and it has characteristics equivalent to polyimide type flexible printed circuits made by lamination.
And by pasting metal foil on the back side,
This improves thermal conductivity.

本発明に使用する金属箔としては、銅、アルミ
ニウム、ニツケルなどの良導電性金属、殊に圧延
又は電解銅のほかアルマイト加工アルミニウム、
鉄、Znメツキ鉄あるいはその他の熱伝導性の優
れたものの箔が用いられる。箔の厚さは150μm以
下、殊に10〜100μmのものが適している。なお、
本発明における2層の金属箔のうちの少なくとも
一方は、回路形成のため、良導電性金属箔が用い
られる。
The metal foil used in the present invention includes highly conductive metals such as copper, aluminum, and nickel, especially rolled or electrolytic copper, as well as anodized aluminum,
Foils of iron, Zn-plated iron, or other materials with excellent thermal conductivity are used. The thickness of the foil is preferably 150 μm or less, particularly 10 to 100 μm. In addition,
At least one of the two layers of metal foil in the present invention is a highly conductive metal foil for forming a circuit.

その場合、良導電性金属箔又は熱伝導性金属箔
に電着し、次いでその電着絶縁層の上に熱伝導性
金属箔又は良導電性金属箔が貼合わされてよい。
In that case, it may be electrodeposited on a highly conductive metal foil or a thermally conductive metal foil, and then the thermally conductive metal foil or the thermally conductive metal foil may be laminated on the electrodeposited insulating layer.

以下実施例、比較例にて本発明の効果を記す。 The effects of the present invention will be described below in Examples and Comparative Examples.

比較例 1 アクリル系アニオン型電着ワニスであるV551
−20(菱電化成社製)を使用し、巾250mm厚さ50μ
の銅箔の片面にマスキングテープを貼つた圧延銅
箔に銅箔を陽極として、連続的(線速3.0m/分)
に電着後ジメチルホルムアミドに浸漬し、温度
200℃の焼付炉中を通過させ片面絶縁金属箔(膜
厚50μ)を得た。
Comparative example 1 V551, an acrylic anionic electrodeposited varnish
-20 (manufactured by Ryoden Kasei), width 250mm thickness 50μ
Continuously (line speed 3.0 m/min) using the copper foil as an anode on a rolled copper foil with masking tape pasted on one side of the copper foil.
After electrodeposition, immersion in dimethylformamide and temperature
The film was passed through a baking oven at 200°C to obtain a single-sided insulated metal foil (thickness: 50μ).

上記のようにして得られた片面絶縁金属箔に回
路巾及び回路間長さ各々1mmで回路をスクリーン
印刷後、エツチングし、回路間の長さを測定した
ところ、0.05mm回路間隔が収縮していた。
After screen-printing a circuit on the single-sided insulating metal foil obtained as above with a circuit width and inter-circuit length of 1 mm, etching and measuring the length between the circuits, it was found that the circuit interval had shrunk by 0.05 mm. Ta.

実施例 1 比較例1と同様にして得られた片面絶縁金属箔
を長さ500mm、巾250mmに切断後厚さ100μmの同サ
イズのアルミ箔をパイララツクス 接着剤(Du
Pont社製)を介して、圧力40Kg/cm2温度×時間
190℃×10分の条件で熱プレスし、アルミ箔を貼
り合わせた銅張回路用絶縁金属箔を得た。
Example 1 A single-sided insulated metal foil obtained in the same manner as Comparative Example 1 was cut into pieces of 500 mm in length and 250 mm in width, and aluminum foil of the same size with a thickness of 100 μm was coated with Pyralax adhesive (Du
(manufactured by Pont), pressure 40Kg/cm 2 temperature x time
Heat pressing was performed at 190°C for 10 minutes to obtain an insulating metal foil for copper-clad circuits with aluminum foil attached.

これを比較例1に同じ寸法で回路形成を行ない
回路間寸法を測定したところ寸法変化は見られな
かつた。
When this was formed into a circuit with the same dimensions as Comparative Example 1 and the inter-circuit dimensions were measured, no dimensional change was observed.

実施例 2 厚さ100μmの亜鉛メツキ鉄箔に実施例1と同じ
ワニス及び同様の条件で片面電着を行ない皮膜厚
50μmの片面絶縁金属箔を得た。これを巾250mm、
長さ500mmに切断した後接着剤としてパイララツ
クス (Du Pont社)を用い、絶縁層と銅箔とを
実施例1と同様の条件で貼り合わせた。同時に回
路形成後、エツチングしたがエツチング前後で寸
法変化はなかつた。
Example 2 Electrodeposition was performed on one side of galvanized iron foil with a thickness of 100 μm using the same varnish as in Example 1 under the same conditions.
A 50 μm single-sided insulated metal foil was obtained. This width is 250mm,
After cutting into a length of 500 mm, the insulating layer and copper foil were bonded together under the same conditions as in Example 1 using Pyralax (Du Pont) as an adhesive. At the same time, etching was performed after circuit formation, but there was no dimensional change before and after etching.

Claims (1)

【特許請求の範囲】[Claims] 1 金属箔の片面に電着により絶縁してなる片面
絶縁金属箔の絶縁面に金属箔を貼り合わせてなる
回路用絶縁金属箔の製法。
1. A method for manufacturing an insulating metal foil for circuits, which is obtained by bonding a metal foil to the insulating surface of a single-sided insulated metal foil that is insulated by electrodeposition on one side of the metal foil.
JP19748884A 1984-09-20 1984-09-20 Manufacture of insulating metallic foil for circuit Granted JPS6174842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19748884A JPS6174842A (en) 1984-09-20 1984-09-20 Manufacture of insulating metallic foil for circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19748884A JPS6174842A (en) 1984-09-20 1984-09-20 Manufacture of insulating metallic foil for circuit

Publications (2)

Publication Number Publication Date
JPS6174842A JPS6174842A (en) 1986-04-17
JPH0476783B2 true JPH0476783B2 (en) 1992-12-04

Family

ID=16375302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19748884A Granted JPS6174842A (en) 1984-09-20 1984-09-20 Manufacture of insulating metallic foil for circuit

Country Status (1)

Country Link
JP (1) JPS6174842A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102394A (en) * 1986-10-20 1988-05-07 松下電器産業株式会社 Manufacture of flexible printed circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5929198B2 (en) * 1977-08-24 1984-07-18 三菱レイヨン株式会社 Protein collection method

Also Published As

Publication number Publication date
JPS6174842A (en) 1986-04-17

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