JPH0479150B2 - - Google Patents
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- Publication number
- JPH0479150B2 JPH0479150B2 JP57143702A JP14370282A JPH0479150B2 JP H0479150 B2 JPH0479150 B2 JP H0479150B2 JP 57143702 A JP57143702 A JP 57143702A JP 14370282 A JP14370282 A JP 14370282A JP H0479150 B2 JPH0479150 B2 JP H0479150B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- mosix
- semiconductor device
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はゲート電極を改良したMOS型半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MOS type semiconductor device with an improved gate electrode.
〔発明の技術的背景〕
最近、MOS型半導体装置の高集積度化、高速
化を目的として、ゲート電極として多結晶シリコ
ンの代りに比較的抵抗の低い金属シリサイドを用
いることが行なわれている。かかる金属シリサイ
ド(例えばモリブデンシリサイド)からなるゲー
ト電極を有するMOSトランジスタは、従来、次
のような方法により製造されている。[Technical Background of the Invention] Recently, metal silicide, which has a relatively low resistance, has been used as a gate electrode instead of polycrystalline silicon for the purpose of increasing the degree of integration and speed of MOS semiconductor devices. A MOS transistor having a gate electrode made of such metal silicide (for example, molybdenum silicide) has conventionally been manufactured by the following method.
まず、p型シリコン基板1にボロンの選択ドー
ピング、選択酸化により周囲にp−型反転防止層
2を有するフイールド酸化膜3を形成する。つづ
いて、フイールド酸化膜3で分離された島状の基
板1領域表面に熱酸化によりゲート酸化膜4を形
成した後、全面にスパツタ法により例えば厚さ
3000ÅのMoSix膜5を堆積する(第1図a図
示)。 First, a field oxide film 3 having a p-type anti-inversion layer 2 around it is formed on a p-type silicon substrate 1 by selective doping with boron and selective oxidation. Subsequently, a gate oxide film 4 is formed by thermal oxidation on the surface of the island-shaped substrate 1 region separated by the field oxide film 3, and then a gate oxide film 4 is formed on the entire surface by sputtering to a thickness of, for example,
A MoSix film 5 of 3000 Å is deposited (as shown in FIG. 1a).
次いで、MoSix膜5をパターニングしてゲー
ト電極6を形成する(第1図b図示)。つづいて、
ゲート電極6をマスクとしてn型不純物、例えば
砒素をゲート酸化膜4を通して基板1にイオン注
入し、活性化してn+型のソース、ドレイン領域
7,8を形成する(第1図c図示)。ひきつづき、
全面にCVD−SiO2膜9を堆積し、コンタクトホ
ール10…を開孔した後、Al膜を蒸着、パター
ニングによりソース、ドレイン領域7,8及びゲ
ート電極6とコンタクトホール10…を介して接
続したAl配線11〜13を形成してMOSトラン
ジスタを製造する(第1図d図示)。 Next, the MoSix film 5 is patterned to form a gate electrode 6 (as shown in FIG. 1b). Continuing,
Using the gate electrode 6 as a mask, n-type impurities such as arsenic are ion-implanted into the substrate 1 through the gate oxide film 4 and activated to form n + -type source and drain regions 7 and 8 (as shown in FIG. 1c). Continuing,
After depositing a CVD-SiO 2 film 9 on the entire surface and opening contact holes 10, an Al film was evaporated and patterned to connect the source and drain regions 7 and 8 and the gate electrode 6 through the contact holes 10. A MOS transistor is manufactured by forming Al wirings 11 to 13 (as shown in FIG. 1d).
しかしながら、MoSixをゲート電極とする
MOSトランジスタは次のような問題があつた。
即ち、MoとSiの組成比xを小さくすると、
MoSixの耐薬品が低下し、製造上多くの問題が
生じる。一方、MoとSiの組成比xを大きくする
と、比抵抗が大きくなり過ぎる。このため、前記
組成比xは2<x≦3の範囲に設定することが望
ましいが、この範囲ではMoSixのゲート電極を
有するMOSトランジスタのフラツトバンド電圧
(VFB)は第2図の点線に示す如く不安定となり、
制御性が悪化する。その結果、MOSトランジス
タの閾値電圧の制御性が悪化するという重大な問
題を生じる。こうした現象は他の金属硅化物の場
合にもみられる。
However, using MoSix as the gate electrode
MOS transistors had the following problems.
That is, when the composition ratio x of Mo and Si is decreased,
The chemical resistance of MoSix deteriorates, leading to many manufacturing problems. On the other hand, if the composition ratio x of Mo and Si is increased, the specific resistance becomes too large. Therefore, it is desirable to set the composition ratio x in the range of 2<x≦3. In this range, the flat band voltage (V FB ) of a MOS transistor having a MoSix gate electrode will be as shown by the dotted line in Figure 2. It becomes unstable,
Controllability deteriorates. As a result, a serious problem arises in that the controllability of the threshold voltage of the MOS transistor deteriorates. This phenomenon is also seen in the case of other metal silicides.
本発明はゲート電極を形成する金属硅化物の仕
事関数を安定化させ、閾値電圧を安定的に制御し
得るMOS型半導体装置を提供しようとするもの
である。
The present invention aims to provide a MOS type semiconductor device in which the work function of metal silicide forming the gate electrode can be stabilized and the threshold voltage can be stably controlled.
本発明者は、MoSixからなるゲート電極がそ
のMoとSiの組成比xの変動によりゲート電極か
らなるMOS構造のフラツトバンド電圧(VFB)が
不安定となる原因について種々検討した結果、
MoSixが熱処理工程においてMoSi2とSiとに分離
することによりそのVFBの不安定性を生じること
を究明した。即ち、MoSix膜(但しx>2)を
堆積した後、熱処理を施すと、第3図に示す如く
MoSi2領域とSi領域とに分離し、MoSi2領域を囲
むようにSi領域が形成される。このようにMoSi2
領域とSi領域の分離が起こると、膜界面において
はSi領域が多いため、膜(ゲート電極)の仕事関
係は主としてSi領域の仕事と関数で決まる。この
ため、前記従来例の如くMoSixのゲート電極6
をマスクとして砒素のイオン注入を行う工程(第
1図c参照)があると、第3図のSi領域は砒素が
少量含まれたものとなり、これがフラツトバンド
電圧(VFB)の低下原因となる。
As a result of various studies on the causes of instability of the flat band voltage (V FB ) of a MOS structure made of a gate electrode made of MoSix due to fluctuations in the Mo to Si composition ratio x of the gate electrode made of MoSix, the present inventor found that
We found that MoSix separates into MoSi 2 and Si during the heat treatment process, causing instability in its V FB . That is, when a MoSix film (x>2) is deposited and then heat treated, the result is as shown in Figure 3.
It is separated into a MoSi 2 region and a Si region, and the Si region is formed to surround the MoSi 2 region. Like this MoSi 2
When separation occurs between the Si region and the Si region, there are many Si regions at the film interface, so the work relationship of the film (gate electrode) is mainly determined by the work and function of the Si region. Therefore, as in the conventional example, the MoSix gate electrode 6
If there is a step of implanting arsenic ions using a mask as shown in FIG. 1c, the Si region shown in FIG. 3 contains a small amount of arsenic, which causes a decrease in the flat band voltage (V FB ).
このようなことから、本発明者は上記知見に基
づき更に鋭意研究を重ねた結果、MoSix膜中の
分離したSi領域にボロン等のアクセプタ原子をド
ーピングすることによつて、分離したSi領域の仕
事関数をMoSi2の仕事関数に近似させ、第2図の
実線に示す如く、MoSixの組成比xの変化に関
係なくフラツトバンド電圧(VFB)を安定化さ
せ、ひいては閾値電圧の制御性が良好なMOS型
半導体装置を見い出したものである。 Based on the above knowledge, the inventors of the present invention conducted further intensive research and found that by doping acceptor atoms such as boron into the separated Si regions in the MoSix film, the work of the separated Si regions can be improved. By approximating the work function to the work function of MoSi 2 , the flat band voltage (V FB ) is stabilized regardless of changes in the composition ratio x of MoSix, as shown by the solid line in Figure 2, and the threshold voltage can be well controlled. This is the discovery of a MOS type semiconductor device.
次に、本発明の実施例を第4図a〜dの製造工
程を併記して説明する。
Next, an embodiment of the present invention will be described with reference to manufacturing steps shown in FIGS. 4a to 4d.
() まず、比抵抗5〜10Ω・cmのp型シリコン
基板21にバツフア酸化膜を介してシリコン窒
化膜パターン(いずれも図示せず)を形成し、
該パターンをマスクとしてボロンを基板21表
面にイオン注入した後高温酸素雰囲気中で熱処
理してフイールド酸化膜22を形成すると共に
フイールド酸化膜22周辺の基板21にp−型
反転防止層23を形成した。つづいて、シリコ
ン窒化膜パターン及びバツフア酸化膜を順次除
去した後、再度、熱酸化処理を施してフイール
ド酸化膜22で分離された島状の基板21領域
表面に例えば厚さ500Åのゲート酸化膜24を
形成した。ひきつづき、全面にスパツタ法によ
り厚さ3000ÅのMoSi2.5膜25を堆積した後、
該MoSi2.5膜25全面にアクセプタ原子として
のボロンをドーズ量1×1016/cm2の条件でイオ
ン注入した(第4図a図示)。() First, a silicon nitride film pattern (none of which is shown) is formed on a p-type silicon substrate 21 with a specific resistance of 5 to 10 Ω·cm via a buffer oxide film.
Boron was ion-implanted into the surface of the substrate 21 using the pattern as a mask, and then heat-treated in a high-temperature oxygen atmosphere to form a field oxide film 22, and at the same time, a p-type anti-inversion layer 23 was formed on the substrate 21 around the field oxide film 22. . Subsequently, after sequentially removing the silicon nitride film pattern and the buffer oxide film, thermal oxidation treatment is performed again to form a gate oxide film 21 with a thickness of, for example, 500 Å on the surface of the island-shaped substrate 21 area separated by the field oxide film 22. was formed. Subsequently, after depositing a MoSi 2.5 film 25 with a thickness of 3000 Å on the entire surface by sputtering,
Boron ions were implanted as acceptor atoms into the entire surface of the MoSi 2.5 film 25 at a dose of 1×10 16 /cm 2 (as shown in FIG. 4a).
() 次いで、ボロンドープMoSi2.5膜25をフ
オトエツチング技術によりパターニングしてゲ
ート電極26を形成した(第4図b図示)。つ
づいてゲート電極26及びフイールド酸化膜2
2をマスクとしてn型不純物、例えば砒素をド
ーズ量5×1015/cm2の条件でゲート酸化膜24
を通して基板21表面にイオン注入した後、
1000℃の酸素雰囲気中で10分間活性化してn+
型のソース、ドレイン領域27,28を形成し
た(第4図c図示)。この場合、ゲート電極2
6中への砒素濃度を前記ホウ素濃度より低くす
るために、砒素のイオン注入量は前述したボロ
のイオン注入量より低く設定した。なお、前記
ゲート電極26のパターニング時に用いたレジ
ストパターンをそのままゲート電極26に形成
した状態で、砒素のイオン注入を行なえば、砒
素のドーズ量は前記ボロンのドーズ量に関係な
く自由に設定できる。() Next, the boron-doped MoSi 2.5 film 25 was patterned by photoetching to form a gate electrode 26 (as shown in FIG. 4b). Next, the gate electrode 26 and the field oxide film 2
2 as a mask, the gate oxide film 24 is coated with an n-type impurity, such as arsenic, at a dose of 5×10 15 /cm 2 .
After implanting ions into the surface of the substrate 21 through the
Activate for 10 minutes in an oxygen atmosphere at 1000 °C to n +
Type source and drain regions 27 and 28 were formed (as shown in FIG. 4c). In this case, gate electrode 2
In order to make the arsenic concentration in the oxide film 6 lower than the boron concentration, the amount of arsenic ions implanted was set to be lower than the amount of ions implanted into the boron described above. Note that if arsenic ions are implanted while the resist pattern used in patterning the gate electrode 26 is directly formed on the gate electrode 26, the dose of arsenic can be freely set regardless of the dose of boron.
() 次いで、全面に例えば厚さ8000ÅのCVD−
SiO2膜29を堆積し、フオトエツチング技術
によりソース、ドレイン領域27,28及びゲ
ート電極26の一部に対応するSiO2膜29を
選択的に除去してコンタクトホール30…を開
孔した後、全面にAl膜を蒸着し、パターニン
グして前記ソース、ドレイン領域27,28及
びゲート電極26とコンタクトホール30…を
介して接続したAl配線31〜33を形成して
nチヤンネルMOSトランジスタを製造した
(第4図d図示)。() Next, the entire surface is coated with a CVD film with a thickness of, for example, 8000 Å.
After depositing the SiO 2 film 29 and selectively removing the SiO 2 film 29 corresponding to the source and drain regions 27, 28 and part of the gate electrode 26 using photoetching technology to open contact holes 30, An N-channel MOS transistor was manufactured by depositing an Al film on the entire surface and patterning it to form Al wirings 31 to 33 connected to the source and drain regions 27 and 28 and the gate electrode 26 via contact holes 30. (Illustrated in Figure 4d).
しかして、本発明のMOSトランジスタはホウ
素がドーピングされたMoSi2.5からなるゲート電
極26を有するため、ゲート電極26は分離した
Si領域のフラツトバンド電圧がMoSi2のそれに近
似し、安定したフラツトバンド電圧を有する。そ
の結果、閾値電圧の制御性が良好となり、設計値
通りの安定した動作が可能となる。 Therefore, since the MOS transistor of the present invention has the gate electrode 26 made of MoSi 2.5 doped with boron, the gate electrode 26 is separated.
The flat band voltage of the Si region is close to that of MoSi 2 and has a stable flat band voltage. As a result, the controllability of the threshold voltage is improved, and stable operation according to the designed value is possible.
また、ゲート電極26がMoSi2.5からなるため、
ゲート抵抗の低減化が可能となり、ひいては高速
動作を達成できる。 Furthermore, since the gate electrode 26 is made of MoSi 2.5 ,
It becomes possible to reduce gate resistance and, in turn, achieve high-speed operation.
更に、前記製造方法の如くMoSi2.5膜25の堆
積後にボロンのイオン注入を行なうことにより、
MoSi2.5膜25中のストレスを緩和できる。 Furthermore, by performing boron ion implantation after depositing the MoSi 2.5 film 25 as in the manufacturing method described above,
Stress in the MoSi 2.5 film 25 can be alleviated.
なお、上記実施例ではMoSixとしてその組成
比xが2.5のものを用いたが、組成比xが2より
大きければ同様な効果を発揮できる。 In the above embodiment, MoSix having a composition ratio x of 2.5 was used, but if the composition ratio x is larger than 2, the same effect can be achieved.
また、ゲート電極の材料としてはMoSixの他
にTaSix、WSix、PtSix、TiSix(但し、いずれ
もxは2よりも大きい)等の金属硅化物を用いて
もよい。 Further, as the material for the gate electrode, other than MoSix, metal silicides such as TaSix, WSix, PtSix, TiSix (where x is larger than 2 in all cases) may be used.
更に、上記実施例ではアクセプタ原子としてホ
ウ素を用いたが、これに限定されずガリウム、イ
ンジユウム等でもよい。 Furthermore, although boron was used as the acceptor atom in the above embodiment, the acceptor atom is not limited to this, and gallium, indium, etc. may also be used.
本発明に係るMOS型半導体装置はnチヤンネ
ルMOSトランジスタに限らず、pチヤンネル
MOSトランジスタ、CMOS等にも同様に適用で
きる。 The MOS type semiconductor device according to the present invention is not limited to an n-channel MOS transistor, but also a p-channel MOS transistor.
It can be similarly applied to MOS transistors, CMOS, etc.
以上詳述した如く、本発明によればゲート電極
を形成する金属硅化物の仕事関数を安定化させる
ことにより、閾値電圧を安定的に制御された高性
能で高速動作が可能なMOS型半導体装置を提供
できるものである。
As described in detail above, according to the present invention, by stabilizing the work function of the metal silicide forming the gate electrode, a MOS type semiconductor device with stable threshold voltage control and capable of high performance and high speed operation is achieved. It is possible to provide
第1図a〜dは従来のnチヤンネルMOSトラ
ンジスタの製造工程を示す断面図、第2図は
MoSixからなるゲート電極のxの変動とMOS構
造のフラツトバンド電圧との関係、並びにボロン
ドープMoSixからなるゲート電極のxの変動と
MOS構造のフラツトバンド電圧との関係、を示
す線図、第3図はMoSix膜の熱処理後における
MoSi2領域とSi領域とし、分離した状態を示す説
明図、第4図a〜dは本発明の一実施例であるn
チヤンネルMOSトランジスタを得るための製造
工程を示す断面図である。
21……p型シリコン基板、22……フイール
ド酸化膜、24……ゲート酸化膜、26……ボロ
ンドープMoSi2.5からなるゲート電極、27……
n+型ソース領域、28……n+型ドレイン領域、
31〜33……Al配線。
Figures 1a to d are cross-sectional views showing the manufacturing process of a conventional n-channel MOS transistor, and Figure 2 is a cross-sectional view showing the manufacturing process of a conventional n-channel MOS transistor.
The relationship between the variation of x of the gate electrode made of MoSix and the flat band voltage of the MOS structure, and the variation of x of the gate electrode made of boron-doped MoSix.
A diagram showing the relationship between the flat band voltage of the MOS structure, and Figure 3 shows the relationship between the flat band voltage of the MoSix film after heat treatment.
An explanatory diagram showing a separated state of two MoSi regions and a Si region, FIGS. 4a to 4d are one embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a manufacturing process for obtaining a channel MOS transistor. 21... p-type silicon substrate, 22... field oxide film, 24... gate oxide film, 26... gate electrode made of boron-doped MoSi 2.5 , 27...
n + type source region, 28...n + type drain region,
31-33...Al wiring.
Claims (1)
数)にて表わされ、かつアクセプタ原子を含む金
属硅化物からなるゲート電極を備えたことを特徴
とするMOS型半導体装置。 2 金属硅化物がMoSix、TaSix、TiSix、
WSix及びPtSix(但し、xは2よりも大きい数)
から選ばれるものであることを特徴とする特許請
求の範囲第1項記載のMOS型半導体装置。 3 アクセプタ原子がホウ素、インジウム、ガリ
ウムのうちから選ばれる1種又は2種以上の混合
物であることを特徴とする特許請求の範囲第1項
記載のMOS型半導体装置。 4 ゲート電極と構成する金属硅化物中にアクセ
プタ原子とドナー原子とを含み、かつアクセプタ
原子の濃度がドナー原子のそれより大きいことを
特徴とする特許請求の範囲第1項記載のMOS型
半導体装置。[Claims] 1. A MOS type represented by MSix (where M is a metal and x is a number larger than 2) and is characterized by having a gate electrode made of a metal silicide containing an acceptor atom. Semiconductor equipment. 2 Metal silicides include MoSix, TaSix, TiSix,
WSix and PtSix (however, x is a number larger than 2)
2. The MOS type semiconductor device according to claim 1, wherein the MOS type semiconductor device is selected from the following. 3. The MOS semiconductor device according to claim 1, wherein the acceptor atom is one or a mixture of two or more selected from boron, indium, and gallium. 4. The MOS semiconductor device according to claim 1, wherein the metal silicide constituting the gate electrode contains acceptor atoms and donor atoms, and the concentration of the acceptor atoms is higher than that of the donor atoms. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57143702A JPS5933875A (en) | 1982-08-19 | 1982-08-19 | Mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57143702A JPS5933875A (en) | 1982-08-19 | 1982-08-19 | Mos type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5933875A JPS5933875A (en) | 1984-02-23 |
| JPH0479150B2 true JPH0479150B2 (en) | 1992-12-15 |
Family
ID=15344978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57143702A Granted JPS5933875A (en) | 1982-08-19 | 1982-08-19 | Mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933875A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7091569B2 (en) | 2001-03-02 | 2006-08-15 | National Institute For Materials Science | Gate and CMOS structure and MOS structure |
| US6991948B2 (en) | 2003-11-05 | 2006-01-31 | Solid State Measurements, Inc. | Method of electrical characterization of a silicon-on-insulator (SOI) wafer |
| US7327155B2 (en) | 2005-11-17 | 2008-02-05 | Solid State Measurements, Inc. | Elastic metal gate MOS transistor for surface mobility measurement in semiconductor materials |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55121667A (en) * | 1979-03-13 | 1980-09-18 | Seiko Epson Corp | Integrated circuit |
-
1982
- 1982-08-19 JP JP57143702A patent/JPS5933875A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5933875A (en) | 1984-02-23 |
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