JPH0479228A - Formation of semiconductor layer - Google Patents

Formation of semiconductor layer

Info

Publication number
JPH0479228A
JPH0479228A JP19326290A JP19326290A JPH0479228A JP H0479228 A JPH0479228 A JP H0479228A JP 19326290 A JP19326290 A JP 19326290A JP 19326290 A JP19326290 A JP 19326290A JP H0479228 A JPH0479228 A JP H0479228A
Authority
JP
Japan
Prior art keywords
layer
semiconductor substrate
semiconductor layer
semiconductor
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19326290A
Other languages
Japanese (ja)
Inventor
Yasaburo Kato
加藤 弥三郎
Shunichi Yoshikoshi
吉越 俊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP19326290A priority Critical patent/JPH0479228A/en
Publication of JPH0479228A publication Critical patent/JPH0479228A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable effective prevention of lamination defects in a semiconductor layer by carrying out ion implantation and heat treatment of impurities and neutral element to a surface part of a semiconductor substrate before growth of the semiconductor layer. CONSTITUTION:An amorphous-processed layer 2 is formed on a surface part of a semiconductor substrate 1 through ion implantation of silicon as a neutral element. A high concentration impurity layer 3 is formed on a surface part of the semiconductor substrate 1 through ion implantation of impurities such as boron B, phosphorus P or arsenic As. Thereafter, crystal of the amorphous layer 2 is recovered by annealing. Then, an oxide film is formed by sacrificial oxidation, a sacrificial oxide film 4 is removed, metallic impurities, etc., which are produced on the surface part of the semiconductor substrate 1 are removed, and a silicon epitaxial growth layer 5 is formed.

Description

【発明の詳細な説明】 以下の順序に従って本発明を説明する。[Detailed description of the invention] The present invention will be described in the following order.

A、産業上の利用分野 B0発明の概要 C1従来技術 り0発明が解決しようとする問題点 E1問題点を解決するための手段 F6作用 G 実施例[第1図、第2図〕 H9発明の効果 (A、産業上の利用分野) 本発明は半導体層の形成方法、特に半導体基板の表面上
に半導体層を成長させる半導体層の形成方法に関する。
A. Industrial field of application B0 Overview of the invention C1 Prior art 0 Problems to be solved by the invention E1 Means for solving the problems F6 Effects G Examples [Figures 1 and 2] H9 Of the invention Effects (A, Industrial Application Field) The present invention relates to a method for forming a semiconductor layer, and particularly to a method for forming a semiconductor layer in which the semiconductor layer is grown on the surface of a semiconductor substrate.

(B、発明の概要) 本発明は、上記の半導体層の形成方法において、 半導体層に積層欠陥が生じることを防止するため、 半導体層の成長前に、半導体基板の表面部への不純物及
び中性元素のイオン注入と、熱処理を行うものである。
(B. Summary of the Invention) In the method for forming a semiconductor layer described above, the present invention includes the steps of removing impurities and intermediates from the surface of the semiconductor substrate before growing the semiconductor layer, in order to prevent stacking faults from occurring in the semiconductor layer. This method involves ion implantation of a chemical element and heat treatment.

(C,従来技術) 半導体集積回路の製造技術として、半導体装置にイオン
注入により不純物を高濃度に注入し、その後、この不純
物注入層の表面にエピタキシャル成長層を形成し、該エ
ピタキシャル成長層の表面部に半導体素子を形成・する
という技術が多(用いられている。
(C, Prior Art) As a manufacturing technology for semiconductor integrated circuits, impurities are injected into a semiconductor device at a high concentration by ion implantation, and then an epitaxially grown layer is formed on the surface of this impurity implanted layer. Many techniques are used to form and manufacture semiconductor devices.

(D、発明が解決しようとする問題点)しかしながら、
上述したように半導体基板表面部上にエピタキシャル成
長層を形成するとエピタキシャル成長層表面に積層欠陥
が高密度に発生するという問題があった。
(D. Problem that the invention seeks to solve) However,
As described above, when an epitaxial growth layer is formed on the surface of a semiconductor substrate, there is a problem in that stacking faults occur at a high density on the surface of the epitaxial growth layer.

この積層欠陥は、半導体基板表面部が不純物のイオン注
入によって結晶破壊されることによって、また半導体基
板表面部とエピタキシャル成長層との界面に金属不純物
や注入不純物が析比し、それが核となってエピタキシャ
ル成長層の成長に伴って欠陥が成長することによって発
生する。
These stacking faults are caused by the crystal destruction of the semiconductor substrate surface by impurity ion implantation, and by the precipitation of metal impurities and implanted impurities at the interface between the semiconductor substrate surface and the epitaxial growth layer, which become the nucleus. This occurs due to the growth of defects as the epitaxial growth layer grows.

そのため、エピタキシャル成長層の形成前に不純物注入
層の表面部を犠牲酸化し、該犠牲により生じた酸化膜を
除去することにより金属不純物や注入不純物の析出を少
な(することが試みられた。
Therefore, attempts have been made to reduce the precipitation of metal impurities and implanted impurities by performing sacrificial oxidation on the surface of the impurity implantation layer before forming the epitaxial growth layer and removing the oxide film produced by the sacrifice.

しかしながら、積層欠陥の密度を充分に低くすることに
は成功するに至っていないのが実状である。
However, in reality, it has not been possible to sufficiently lower the density of stacking faults.

そこで、本発明は半導体層に積層欠陥が生じることを有
効に防止することを目的とする。
Therefore, an object of the present invention is to effectively prevent stacking faults from occurring in semiconductor layers.

(E、問題点を解決するための手段) 本発明半導体層の形成方法は上記問題点を解決するため
、半導体層の成長前に、半導体基板の表面部への不純物
及び中性元素のイオン注入と、熱処理を行うことを特徴
とする。
(E. Means for Solving the Problems) In order to solve the above problems, the method for forming a semiconductor layer of the present invention includes ion implantation of impurities and neutral elements into the surface portion of the semiconductor substrate before the growth of the semiconductor layer. It is characterized by performing heat treatment.

(F、作用) 本発明半導体層の形成方法によれば、半導体層の成長前
に半導体基板表面部に不純物イオン注入だけでなく中性
元素のイオン注入も行うので、半導体基板の表面部を一
旦アモルファス化することができる。そして、その後、
熱処理するので一旦アモルファス化した半導体基板の表
面部の結晶を回復することができ、また、熱処理中に半
導体基板表面近傍の金属不純物等を中性元素注入層中の
欠陥によりゲッタすることができる・そして・その結晶
回復し金属不純物のゲッタが為された半導体基板上に半
導体層を形成するので、半導体層の積層欠陥を相当に少
なくすることができるのである。
(F, Effect) According to the method for forming a semiconductor layer of the present invention, not only impurity ion implantation but also neutral element ion implantation is performed into the semiconductor substrate surface before the growth of the semiconductor layer. Can be made amorphous. And after that,
Because heat treatment is performed, it is possible to recover the crystals on the surface of the semiconductor substrate that has once become amorphous, and during the heat treatment, metal impurities near the surface of the semiconductor substrate can be gettered by defects in the neutral element injection layer. Since the semiconductor layer is formed on the semiconductor substrate on which the crystals have been recovered and the metal impurities have been gettered, stacking defects in the semiconductor layer can be considerably reduced.

(G、実施例)[第1図、第2図] 以下、本発明半導体層の形成方法を図示実施例に従って
詳細に説明する。
(G, Example) [FIGS. 1 and 2] Hereinafter, a method for forming a semiconductor layer of the present invention will be described in detail according to the illustrated example.

第1図(A)乃至(E)は本発明半導体層の形成方法の
一つの実施例を工程順に示す断面図である。
FIGS. 1A to 1E are cross-sectional views showing one embodiment of the method for forming a semiconductor layer of the present invention in the order of steps.

(A)同図(A)に示すように、半導体基板1の表面部
に中性元素としてシリコンをイオン注入することにより
アモルファス化する。2はこのイオン注入により半導体
基板1の表面部に形成されたアモルファス化層である。
(A) As shown in FIG. 2A, the surface of the semiconductor substrate 1 is made amorphous by ion-implanting silicon as a neutral element. Reference numeral 2 denotes an amorphous layer formed on the surface of the semiconductor substrate 1 by this ion implantation.

シリコンの注入濃度は例えば2 X 1015cm−2
程度が良い。
The implantation concentration of silicon is, for example, 2 x 1015 cm-2
Good condition.

(B)次に、同図(B)に示すように、半導体基板1表
面部に、例えばホウ素BあるいはリンPもしくは砒素A
s等の不純物をイオン注入することにより高濃度不純物
層3を形成する。不純物の注入濃度は例えば2 X 1
0 ”cm−2程度である。
(B) Next, as shown in the same figure (B), for example, boron B, phosphorus P, or arsenic A
A high concentration impurity layer 3 is formed by ion-implanting impurities such as s. The impurity implantation concentration is, for example, 2×1
It is about 0"cm-2.

(C)次に、同図(C)に示すように、例えば1200
℃の温度でアニールすることにより上記のシリコンがイ
オン注入されたアモルファス化層2を結晶回復する。
(C) Next, as shown in the same figure (C), for example, 1200
By annealing at a temperature of .degree. C., the amorphous layer 2 into which silicon ions have been implanted is crystallized.

(D)次に、同図(D)に示すように、半導体基板1表
面を犠牲酸化(加熱温度1200℃)する。4はこの犠
牲酸化によって形成された酸化膜である。
(D) Next, as shown in the figure (D), the surface of the semiconductor substrate 1 is subjected to sacrificial oxidation (heating temperature: 1200° C.). 4 is an oxide film formed by this sacrificial oxidation.

(E)その後、上記犠牲酸化膜4を除去することにより
半導体基板1の表面部に生じている金属不純物等を除去
し、しかる後、同図(E)に示すようにシリコンエピタ
キシャル成長層5を形成する。
(E) After that, metal impurities generated on the surface of the semiconductor substrate 1 are removed by removing the sacrificial oxide film 4, and then a silicon epitaxial growth layer 5 is formed as shown in FIG. do.

第2図は積層欠陥の密度のシリコンドーズ量依浮性を示
すもので、横軸にシリコンドーズ量[×1015cm−
2]をとり、縦軸に積層欠陥の密度[cm−2]をとっ
たものである。
Figure 2 shows the dependence of the density of stacking faults on the silicon dose, where the horizontal axis shows the silicon dose [×1015cm-
2] and the stacking fault density [cm-2] is plotted on the vertical axis.

この図から明らかなように、従来の場合、即ち工程(A
)を設けず従ってシリコンドーズ量が0の場合には欠陥
密度が10’cm−2程度もあるのに対して、本実施例
のようにシリコンを2×1 () 15cm−2程度打
込むと欠陥密度を10”CD1−2以下、即ち100分
の1以下に低減できるのである。実際には、欠陥数が1
0cm−2以下にすることもできた。
As is clear from this figure, in the conventional case, that is, the process (A
) is not provided, and therefore the silicon dose is 0, the defect density is about 10'cm-2, whereas if silicon is implanted at about 2 x 1 () 15cm-2 as in this example, The defect density can be reduced to less than 10" CD1-2, that is, less than 1/100. In reality, the number of defects is reduced to 1
It was also possible to make it less than 0 cm-2.

このように、本半導体層の形成方法によれば、半導体基
板1の表面部をシリコンのイオン注入によりアモルファ
ス化したうえで活性化アニールするので不純物のイオン
注入による結晶破壊を回復することができるし、また、
半導体基板1表面近傍の金属不純物等も活性化アニール
中にシリコン注入層2内の欠陥によりゲッタすることが
でき、上述したように欠陥密度の低減を図ることができ
る。
As described above, according to the present method for forming a semiconductor layer, since the surface portion of the semiconductor substrate 1 is made amorphous by silicon ion implantation and then activated and annealed, crystal destruction caused by impurity ion implantation can be recovered. ,Also,
Metal impurities in the vicinity of the surface of the semiconductor substrate 1 can also be gettered by defects in the silicon injection layer 2 during activation annealing, and the defect density can be reduced as described above.

尚、上記実施例においてはシリコンのイオン注入工程の
方が不純物のイオン注入工程よりも先であったが、その
逆でも良いし、シリコンと不純物を同時にイオン注入し
ても良い。また、シリコンのイオン注入により形成され
たアモルファス化層の厚さは高濃度不純物層の厚さより
も薄くても良いし厚(でも良い。また、上記実施例にお
いてはアモルファス化のための中性元素としてシリコン
をイオン注入していたが、シリコンの結晶性等に悪い影
響をほとんど与えない元素ならほかの元素、例えば炭素
をイオン注入するようにしても良い。
In the above embodiment, the silicon ion implantation step was performed before the impurity ion implantation step, but the reverse may be used, or silicon and impurity ions may be implanted simultaneously. Further, the thickness of the amorphous layer formed by silicon ion implantation may be thinner or thicker than the thickness of the high concentration impurity layer. Although silicon is ion-implanted as a material, other elements, such as carbon, may be ion-implanted as long as they have little negative effect on the crystallinity of silicon.

(H,発明の効果) 以上に述べたように、本発明半導体層の形成方法は、半
導体基板表面部に不純物と中性元素をイオン注入し、次
いで、熱処理し、その後、上記半導体基板上に半導体層
を成長させることを特徴とするものである。
(H, Effects of the Invention) As described above, the method for forming a semiconductor layer of the present invention involves ion-implanting impurities and neutral elements into the surface of a semiconductor substrate, followed by heat treatment, and then forming a layer on the semiconductor substrate. It is characterized by growing a semiconductor layer.

従って、本発明半導体層の形成方法によれば、半導体層
の成長前に半導体基板表面部に不純物イオン注入だけで
な(中性元素のイオン注入も行うので、半導体基板の表
面部を一旦アモルファス化することができる。その後、
熱処理するので一旦アモルファス化した半導体基板の表
面部の結晶を回復することができ、また、半導体基板表
面近傍の金属不純物等を熱処理中に中性元素注入層中の
欠陥によりゲッタすることができる。そして、その結晶
回復し金属不純物のゲッタが為された半導体基板上に半
導体層を形成するので、半導体層の積層欠陥を相当に少
なくすることができるのであ乙。
Therefore, according to the method for forming a semiconductor layer of the present invention, before the growth of the semiconductor layer, not only impurity ions are implanted into the surface of the semiconductor substrate (ion implantation of neutral elements is also performed, so the surface of the semiconductor substrate is once made amorphous). You can then
Since the heat treatment is performed, the crystals on the surface of the semiconductor substrate that have been once amorphous can be recovered, and metal impurities near the surface of the semiconductor substrate can be gettered by defects in the neutral element injection layer during the heat treatment. Since the semiconductor layer is formed on the semiconductor substrate on which the crystals have been recovered and the metal impurities have been gettered, stacking defects in the semiconductor layer can be considerably reduced.

1・・・半導体基板、 2・・・中性元素注入層。1... semiconductor substrate, 2...Neutral element injection layer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)乃至(E)は本発明半導体層の形成方法の
一つの実施例を工程順に示す断面図、第2図は欠陥密度
のシリコンドーズ量依存性を示す図である。 符号の説明 一
FIGS. 1A to 1E are cross-sectional views showing step-by-step an embodiment of the method for forming a semiconductor layer of the present invention, and FIG. 2 is a diagram showing the dependence of defect density on silicon dose. Explanation of symbols 1

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板表面部に不純物と中性元素をイオン注
入し、 次いで、熱処理し、 その後、上記半導体基板上に半導体層を成長させる ことを特徴とする半導体層の形成方法
(1) A method for forming a semiconductor layer, which comprises ion-implanting impurities and neutral elements into the surface of a semiconductor substrate, then performing heat treatment, and then growing a semiconductor layer on the semiconductor substrate.
JP19326290A 1990-07-21 1990-07-21 Formation of semiconductor layer Pending JPH0479228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19326290A JPH0479228A (en) 1990-07-21 1990-07-21 Formation of semiconductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19326290A JPH0479228A (en) 1990-07-21 1990-07-21 Formation of semiconductor layer

Publications (1)

Publication Number Publication Date
JPH0479228A true JPH0479228A (en) 1992-03-12

Family

ID=16305021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19326290A Pending JPH0479228A (en) 1990-07-21 1990-07-21 Formation of semiconductor layer

Country Status (1)

Country Link
JP (1) JPH0479228A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426380B1 (en) * 2001-03-30 2004-04-08 주승기 Method of crystallizing a silicon layer and method of fabricating a semiconductor device using the same
KR100525436B1 (en) * 2001-05-25 2005-11-02 엘지.필립스 엘시디 주식회사 Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD
JP2011077066A (en) * 2009-09-29 2011-04-14 Shin Etsu Handotai Co Ltd Method of manufacturing semiconductor substrate
JP2014041866A (en) * 2012-08-21 2014-03-06 Fujitsu Semiconductor Ltd Semiconductor device manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426380B1 (en) * 2001-03-30 2004-04-08 주승기 Method of crystallizing a silicon layer and method of fabricating a semiconductor device using the same
KR100525436B1 (en) * 2001-05-25 2005-11-02 엘지.필립스 엘시디 주식회사 Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD
JP2011077066A (en) * 2009-09-29 2011-04-14 Shin Etsu Handotai Co Ltd Method of manufacturing semiconductor substrate
JP2014041866A (en) * 2012-08-21 2014-03-06 Fujitsu Semiconductor Ltd Semiconductor device manufacturing method

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