JPH0479360A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0479360A JPH0479360A JP2194524A JP19452490A JPH0479360A JP H0479360 A JPH0479360 A JP H0479360A JP 2194524 A JP2194524 A JP 2194524A JP 19452490 A JP19452490 A JP 19452490A JP H0479360 A JPH0479360 A JP H0479360A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package
- lsi chip
- lsi
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に２個のＬＳＩチップを
上下に重ね合わせ、１個のバ・・Ｉクージに搭載する半
導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a semiconductor device in which two LSI chips are stacked one on top of the other and mounted on one bag.
近年の半導体装置は、ＬＳＩチップの大型化とパッケー
ジの小型化、超多端子化という相矛盾する要求が出され
ている。In recent years, contradictory demands have been made for semiconductor devices: larger LSI chips, smaller packages, and an extremely large number of terminals.
しかし、従来、この種の半導体装置では、第７図および
第８図に示すように、パッケージ３１内のチップ接合面
３２上に、ＬＳＩチップ接合剤３６ （Ａｕ−３ｉ等）
を介して、ＬＳＩチップ３５を固定し、ＬＳＩチップ３
５とパッケージ３１との間の回路接続は、ワイヤーリー
ド３４を用いてＬＳＩチップ３５上に設けられた接続パ
ッドとパッケージ３１の引出し回路３３に設けられた接
続パッドとの間をワイヤーボンディング方式により１２
続し、１個のＬＳＩチップと１個のパッケージとで１個
の半導体装置を形成していた。However, conventionally, in this type of semiconductor device, as shown in FIGS. 7 and 8, an LSI chip bonding agent 36 (such as Au-3i) is used on the chip bonding surface 32 in the package 31.
The LSI chip 35 is fixed through the LSI chip 3.
5 and the package 31 is made by wire bonding between the connection pads provided on the LSI chip 35 and the connection pads provided on the lead-out circuit 33 of the package 31 using wire leads 34.
Subsequently, one LSI chip and one package formed one semiconductor device.
前述の半導体装置において、餡多端子を必要とする半導
体装置のワイヤーリード間隔は、１５０μｍ前後がボン
ディング装置の標準であり、ワイヤーリード間隔を狭め
ることは現状では困難であった。この現状において、超
多端子の半導体装置を実現するには、ワイヤーボンディ
ング可能な間隔を確保するために、ＬＳＩチ・Ｖプの大
型化、延いては半導体装置用パッケージを大型化しなけ
れば実現できないという問題点があった。In the above-mentioned semiconductor device, the wire lead spacing of a semiconductor device requiring multiple terminals is approximately 150 μm as a standard for bonding equipment, and it is currently difficult to narrow the wire lead spacing. Under this current situation, in order to realize a semiconductor device with an extremely large number of terminals, it is necessary to increase the size of the LSI chips and, by extension, the size of the semiconductor device package in order to secure the spacing that allows wire bonding. There was a problem.
本発明の目的は、前記欠点を解決し、チップを大型化せ
ずとも、超多端子を実現できるようにした半導体装置を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that solves the above-mentioned drawbacks and can realize a large number of terminals without increasing the size of the chip.
本発明の半導体装置の精成は、第１の機能を受持つ第１
のＬＳＩチ・・ツブと、第２の機能を受持つ第２のＬＳ
Ｉシップとを上下に重ね合せ、パッケージに；載し、前
記第１のＬＳＩチップの電極と前記パッケージの電極と
を電気的に接続し、前記第２のＬＳＩチップの裏面上の
Ｔ；、極と前記パッケージの接続部とを電気的に接続し
ていることを特徴とする。The refinement of the semiconductor device of the present invention involves the first semiconductor device having the first function.
LSI chip and a second LS that handles the second function
The I-ships are stacked vertically and placed on a package, the electrodes of the first LSI chip and the electrodes of the package are electrically connected, and the T-ships on the back surface of the second LSI chip are and a connecting portion of the package are electrically connected to each other.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の半導体装置の平面図、
第２図は第１図のＡ−Ａ’線の断面図である。第１図、
第２図において、本実施例のパッケージ１は、ワイヤー
リード４をボンディングするボンディング段に、ポンデ
ィングパッドが付加された引出し回路３が形成され、通
常ではＬＳＩチップを固定するチップ接合面２にＬＳＩ
チップ接続部８（半田付用パ・ソド）が形成されている
。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a sectional view taken along line AA' in FIG. 1. Figure 1,
In FIG. 2, the package 1 of this embodiment has an extraction circuit 3 with bonding pads added at the bonding stage for bonding the wire leads 4, and an LSI chip on the chip bonding surface 2 which normally fixes the LSI chip.
A chip connection portion 8 (soldering pad/sod) is formed.
第２ＬＳ Ｉチップ７は、フェースダウンでパ・・ｌケ
ージ１に形成されたＬＳＩチップ接続部８の千・ツブパ
ッドとフリップチ・ツブ方式により、ケースパッドとが
接続される。The second LSI chip 7 is connected face-down to the case pads of the LSI chip connection portion 8 formed in the package 1 by a flip-chip method.
第１ＬＳＩチ・ツブ５は、第２ＬＳＩチ・ツブ７と、物
理的に接続するＬＳＩチ・ツブ接合剤６（シリコン樹脂
等）を介してフェースアップでパッケージ１に固定し、
その後ワイヤボンディング方式で、ＬＳＩ内チップに設
けられたパッドとバ・ｌケージ１に設けられた引比し回
路３上のべ・ソドとを接続する。The first LSI chip 5 is fixed face-up to the package 1 via an LSI chip bonding agent 6 (silicon resin, etc.) that physically connects the second LSI chip 7.
Thereafter, a wire bonding method is used to connect the pads provided on the chip inside the LSI and the bases on the comparison circuit 3 provided on the cage 1.
以上により、１個のパッケージ１に２個のＬＳＩチ・・
ｌプ５，７を重ね合わせて搭載し、半導体装置の小型化
、高累積化の実現を可能とした。As a result of the above, two LSI chips are included in one package 1...
By mounting the lp 5 and 7 on top of each other, it is possible to downsize the semiconductor device and achieve high integration.
第３図は本発明の第２の実施例の半導体装置を示す平面
図、第４図は第３図のＢ−Ｂ’線の断面図である。第３
図、第４図において、本実施例は、第２図と異なり、断
面の段差がない。パラゲージ１１上の引出し回路（上）
（下）１３゜１９、およびＬＳＩチップ接続部１８の回
路パターンを薄膜技術により形成したパッケージと、第
１、第２のＬＳＩチップ１５．１７を組み合わすことに
より１本実施例は、前記第１の実施例に比べて、パッケ
ージ回路の微細化工が可能となり、薄型パッケージの実
現が可能となった。3 is a plan view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 4 is a sectional view taken along line BB' in FIG. 3. Third
4, unlike FIG. 2, this embodiment has no step difference in cross section. Drawer circuit on para gauge 11 (top)
(Bottom) By combining the first and second LSI chips 15 and 17 with a package in which the circuit pattern of the 13° 19 and LSI chip connection portion 18 is formed by thin film technology, this embodiment Compared to the embodiment described above, it has become possible to miniaturize the package circuit and realize a thin package.
第５図は本発明の第３の実施例の半導体装置を示す平面
図、第６図は第５図のＣ−Ｃ’Ｆｙの断面図である。第
５図、第６図において、本実施例では、ＬＳＩチップの
回路面に信号および電源引出し用の接続パッド、裏面側
に回路面から貫通した電源バスの接続パッドを有した第
２ＬＳＩチツプ２７と、リードフレーム剛接続パ・ソド
とフリップチップ用接続パッドをＬＳＩチップ回路面に
有した第１ＬＳＩチ・ツブ２５と、それらを搭載するパ
ッケージ２１とを含み、精成される。ここで、第２ＬＳ
Ｉチツプ２７は、フェースダウンでパッケージ２１に形
成されたＬＳＩチップ接続部２８と、フリップチップ方
式によりチップパッドとケースパッドとが接続される。FIG. 5 is a plan view showing a semiconductor device according to a third embodiment of the present invention, and FIG. 6 is a sectional view taken along line CC'Fy in FIG. 5 and 6, in this embodiment, the second LSI chip 27 has a connection pad for signal and power extraction on the circuit surface of the LSI chip, and a connection pad for a power bus penetrating from the circuit surface on the back side. , a first LSI chip 25 having lead frame rigid connection pads and flip-chip connection pads on the LSI chip circuit surface, and a package 21 on which they are mounted. Here, the second LS
The I-chip 27 has an LSI chip connection portion 28 formed face down on the package 21, and the chip pad and case pad are connected by a flip-chip method.
第１ＬＳＩチツプ２５の周縁部には予めリードフレーム
を接続しておき、このチップ回路内側に設けられた電源
バス接続部・ソドは、第２ＬＳ Ｉチップ２７の貫通電
源バス２９を通して、接続部２８に接続される。第１Ｌ
ＳＩチツプ２５と第２ＬＳＩチツプ２７との対向面の各
々の接続パッド部を、開口した絶縁材２６を挟み、フリ
・・ｌブチツブ方式にて接続する。A lead frame is connected to the periphery of the first LSI chip 25 in advance, and the power supply bus connection section provided inside this chip circuit is connected to the connection section 28 through the through power supply bus 29 of the second LSI chip 27. Connected. 1st L
The connection pad portions of the opposing surfaces of the SI chip 25 and the second LSI chip 27 are connected in a free-button manner with an open insulating material 26 in between.
本実施例は、前記第１および第２の実施例に比べて、電
源バスを２個のＬＳＩチップで共用することができ、よ
り多くの信号線引き圧しが可能となり、超多端子の半導
体装置が実現できる。In this embodiment, compared to the first and second embodiments, the power supply bus can be shared by two LSI chips, more signal lines can be drawn, and a semiconductor device with a large number of terminals can be used. realizable.
以上説明したように、本発明は、２種類のＬＳＩチップ
を重ね合わせ、個々のＬＳＩチ・ツブに対応する接続部
を半導体装置用パッケージに設け、１つのパッケージに
２個のＬＳＩチップを搭載し接続する工法により半導体
装置を精成することにより、次のような効果がある。既
存の接続技術および装置を用い、例えばＬＳＩチップ寸
法を５ ＋ｘｍ口、外部引き呂し専有部を３割とした場
合の引き比しパッド数は、■ＬＳＩチップ外線から引き
８す場合は約１１２個！ （５ｍｍ−０，８ａｍ） Ｘ
４ ／ ０．１５ａｍ ｌ 、■フリップチップ方式で
は約３０個（（２５ｍｍ”Ｘｏ、３ ） ／’ （０，
５＋ｕ＋Ｘ０．５ ＩＩｍ＋）となる、前記■のみで精
成する従来技術に比べて、■と■のＬＳＩチップを組み
合せた場合でｌｊ倍、■を２個組み合わせた場合は２倍
の高集積化した半導体装置の実現ができるという効果を
有する。As explained above, the present invention stacks two types of LSI chips, provides a connection portion corresponding to each LSI chip in a semiconductor device package, and mounts two LSI chips in one package. By refining the semiconductor device using the connection method, the following effects can be achieved. Using existing connection technology and equipment, for example, if the LSI chip size is 5 + xm openings and the external lead line is 30% of the dedicated area, the number of pads to be compared is approximately 112 if the external line of the LSI chip is subtracted by 8. Individual! (5mm-0.8am)
4 / 0.15am l, ■Approximately 30 pieces ((25mm"Xo, 3) /' (0,
5 + u + This has the effect that a semiconductor device can be realized.
また、本発明は、半導体装置の外部引き比しリード線を
固定した場合には、ＬＳＩチップの小型化、延いては半
導体装置の小型化が実現できる効果もある。Further, the present invention has the effect that when the external reference lead wire of the semiconductor device is fixed, the size of the LSI chip and, by extension, the size of the semiconductor device can be reduced.
第１図は本発明の第１の実施例の半導体装置を示す平面
図、第２図は第１図のＡ−Ａ′線の断面図、第３図は本
発明の第２の実施例の半導体装置を示す平面図、第４図
は第３図のＢ−Ｂ’線の断面図、第５図は本発明の第３
の実施例の半導体装置を示す平面図、第６図は第５図の
ｃ−（′線の断面図、第７図は従来技術を示す半導体装
置の平面図、第８図は第７図のＤ−Ｄ’断面図である。
１．１１．２１．３１・・・パッケージ、２，１２．２
２．３２・・・チップ接合面、３ 、２３ 、３３・・
・引き出し回路、４，１４．３４・・・ワイヤーリード
、５，１５．２５・・・第１ＬＳＩチツプ、６，１６．
３６・・・ＬＳＩチ・ツブ接合材、７．１７．２７・・
・第２ＬＳＩチツプ、８．１８．２８・・・ＬＳＩチ・
ツブ接続部、１３・・・引比し回８〈上）、１つ・弓出
し回路（下）、３５・・・ＬＳＩチップ、２４・・リー
ドフレーム、２６・・・絶縁材、２９・・・貫通電源ハ
ス。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. 1, and FIG. FIG. 4 is a plan view showing the semiconductor device, FIG. 4 is a sectional view taken along line BB' in FIG. 3, and FIG.
FIG. 6 is a sectional view taken along line c-(' in FIG. It is a DD' sectional view. 1.11.21.31... Package, 2, 12.2
2.32...Chip bonding surface, 3, 23, 33...
- Extraction circuit, 4, 14. 34... Wire lead, 5, 15. 25... 1st LSI chip, 6, 16.
36...LSI chip/tube bonding material, 7.17.27...
・2nd LSI chip, 8.18.28...LSI chip
Tube connection part, 13... Drawing ratio 8 (top), one bow circuit (bottom), 35... LSI chip, 24... Lead frame, 26... Insulating material, 29...・Through power supply lotus.
Claims (1)
能を受持つ第２のＬＳＩシップとを上下に重ね合せ、パ
ッケージに搭載し、前記第１のＬＳＩチップの電極と前
記パッケージの電極とを電気的に接続し、前記第２のＬ
ＳＩチップの裏面上の電極と前記パッケージの接続部と
を電気的に接続していることを特徴とする半導体装置。A first LSI chip in charge of a first function and a second LSI chip in charge of a second function are stacked vertically and mounted in a package, and the electrodes of the first LSI chip and the second LSI chip in charge of the package are stacked one on top of the other. The second L is electrically connected to the electrode.
A semiconductor device characterized in that an electrode on a back surface of an SI chip and a connecting portion of the package are electrically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2194524A JPH0479360A (en) | 1990-07-23 | 1990-07-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2194524A JPH0479360A (en) | 1990-07-23 | 1990-07-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0479360A true JPH0479360A (en) | 1992-03-12 |
Family
ID=16325967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2194524A Pending JPH0479360A (en) | 1990-07-23 | 1990-07-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0479360A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6324067B1 (en) | 1995-11-16 | 2001-11-27 | Matsushita Electric Industrial Co., Ltd. | Printed wiring board and assembly of the same |
-
1990
- 1990-07-23 JP JP2194524A patent/JPH0479360A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6324067B1 (en) | 1995-11-16 | 2001-11-27 | Matsushita Electric Industrial Co., Ltd. | Printed wiring board and assembly of the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2731134A1 (en) | Multi-chip module connection by way of bridging blocks | |
| US9875955B2 (en) | Low cost hybrid high density package | |
| JP2002222889A (en) | Semiconductor device and manufacturing method thereof | |
| US7863093B2 (en) | Integrated circuit die with logically equivalent bonding pads | |
| JP2001223326A (en) | Semiconductor device | |
| US9972606B2 (en) | Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding | |
| US6091138A (en) | Multi-chip packaging using bump technology | |
| US6100593A (en) | Multiple chip hybrid package using bump technology | |
| JPS6347259B2 (en) | ||
| JPH11260851A (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| US20050269680A1 (en) | System-in-package (SIP) structure and fabrication thereof | |
| TW200531246A (en) | Semiconductor package | |
| KR100621547B1 (en) | Multichip Package | |
| JP2015523740A (en) | Reconfigured wafer level microelectronic package | |
| TWI299966B (en) | Circuit device | |
| US20040245651A1 (en) | Semiconductor device and method for fabricating the same | |
| JPS5988864A (en) | Manufacture of semiconductor device | |
| JP3815933B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0322544A (en) | Semiconductor device | |
| CN100524736C (en) | Stacked chip package structure | |
| JPH0479360A (en) | Semiconductor device | |
| CN100466246C (en) | Flexible Substrates for Packaging | |
| CN115831779A (en) | Wafer bonding method and wafer bonding structure | |
| JPH11297738A (en) | Semiconductor chip mounting structure | |
| CN111276457A (en) | Dual chip memory package |