JPH0479501B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock phase error detection circuit used for clock reproduction in a four-phase phase modulation/demodulation system.

[Conventional technology]

Conventionally, this type of clock phase error detection circuit has used a zero-crossing detection method using pieces of two series of demodulated signals (hereinafter referred to as an I channel and a Q channel). Hereinafter, a demodulation circuit using conventional digital signal processing will be described as an example, with reference to a block diagram of a clock phase error detection circuit in FIG. In the figure, an analog signal A applied to an A/D (analog-digital) converter 21 is converted to k by a clock signal (2f _S ) B twice the modulation rate f _S .
The signal is quantized into a digital signal of bits (k is a positive integer). The most significant bit (MSB) of this k-bit quantized signal C is sampled and delayed in a 1-bit D.FF (delayed flip-flop) 22a at a rate of _fs . In this case, the clock signal B (synchronized with the reference clock f _S ) having a speed of 2f _S is divided by two by the frequency divider 23, and the clock signal (f _S ) D is output as the clock input ( ck).

The output signal E of the D.FF 22a is delayed in sampling at a speed of f _S in the D.FF 22c, and is input to an Ex.OR (exclusive OR) circuit 24a. The output signal F of D・FF22c is Ex・
Input to OR24, output signal E of D・FF22a
The zero crossing of the k-bit quantized signal C is detected by taking the exclusive OR with
When not detected, outputs "0". The k bits of the k bit quantized signal C are delayed in sampling at a rate _S in the D.FF 22b.
Here, the clock signal D with a speed of f _S is transferred to the inverter 2.
The clock ( _S ) H inverted at 5 is D・FF22b
is applied to the clock input (ck) of the D・FF
The output signal J of 22b is f _S at D・FF22d.
The sampling is delayed by a different clock. D.
The output signal K of FF22d is a k-bit quantized signal C.
This is the sample value at the zero crossing point of , that is, the clock phase error value. However, in order to set the polarity of this error value J to an error value L that correctly corresponds to the delay or advance of the clock timing, a polarity inverting circuit 26
When the output signal of the D.FF22c is "1", the polarity of the input signal K is inverted, and the D.FF22c
By not inverting the polarity of the input signal K when the output signal is "0", a clock phase error signal L whose polarity correctly corresponds to the delay or advance of the clock timing is output.

Here, with reference to FIG. 3, the polarity of the zero-crossing detection value K and the delay and advance of the clock timing will be explained depending on the polarity inversion direction of the k-bit quantized signal C. FIG. 3a shows that the zero-crossing detection timing T ₁ is delayed from the timing T ₀ when there is no clock phase error. The detected values A and B are detected when the polarity is reversed from negative to positive and when the polarity is reversed from positive to negative, respectively. It can be seen that there are two polarities of the detected value depending on the direction of polarity reversal. If the polarity of the detected value when the clock timing is delayed is to be negative (-), it is necessary to invert the polarity of the detected value A. Similarly, Fig. 3b shows
This indicates that the zero-crossing detection timing T ₂ is ahead of T ₀ , and the detection values C and D are detected when the polarity inversion direction is from negative to positive and from positive to negative, respectively. Assuming that the polarity of the detected value when the clock timing is advanced is positive (+), it is necessary to reverse the polarity of the detected value D. Referring again to FIG. 2, the selection circuit 27 outputs the input signal L when the output signal of Ex・OR 24 is “1”, and
When the output signal of is "0", the input signal N(0) is output. The output signal R of the selection circuit 27 is a clock phase error signal, and when the clock timing is correct, the average value of the output signal R converges to "0".

[Problem that the invention seeks to solve]

The above-mentioned conventional clock error detection circuit detects a clock phase error by detecting a zero-crossing of a demodulated signal of one series (one channel), so it has the disadvantage that correct zero-crossing detection cannot be performed if there is a carrier phase error. There is. Regarding this reason,
This will be explained with reference to FIG. Figure a is a four-phase signal space diagram, and Figure b is an example of a demodulated signal corresponding to Figure a. Since the conventional clock phase error detection circuit detects the phase error only by detecting the zero crossing of the I channel, for example, the time T ₁ in FIG.
The phase error will be detected at T ₂ , T ₄ , and T ₅ .
It is clear from this figure that the phase errors detected at times T ₁ and T ₅ are not correct values. That is, the clock phase error cannot be detected without being affected by the carrier phase error. In FIG. 4a, white circles indicate signal points when there is no carrier phase error, black circles indicate signal points when there is a carrier phase error, and α indicates the phase error of the carrier wave. Further, in FIG. 4b, the broken line shows the data transition when there is no carrier wave phase error, and the solid line shows the data transition when there is a carrier wave phase error.

[Means for solving problems]

The clock phase error detection circuit according to the present invention has n
Two demodulated signal sequences obtained by orthogonally demodulating a phase-phase modulated signal (n is a positive integer and n>2) are input, and the reciprocal of a multiple of the modulation speed f _S of the modulated signal T _S (=
first and second A/D converters that sample the demodulated string at a rate of 1/2f _S ) and convert the analog signal into a digital signal; and outputs of the first and second A/D converters. First and second zero-crossing detection circuits that receive a signal as input, detect zero-crossings of digital data from odd-numbered sample data, and output logic "1"; and these first and second zero-crossing detection circuits. an AND circuit that calculates the logical product of the data and detects that a zero crossing occurs simultaneously between two series of data; A polarity inverting circuit that inverts the polarity of the sample value of and the output signal of the logic circuit is input, and when the logical product is "1", the output signal of the polarity inverting circuit is selected, and when the logical product is "0", the output signal of the polarity inverting circuit is selected. A selection circuit that selects an output signal indicating zero error.

[Embodiments of the invention]

Next, an embodiment of a clock phase error detection circuit according to the present invention will be described with reference to the block diagram of FIG. In this figure, in A/D converters 11a and 11b, analog signals A and B of I and Q channels, respectively, have a modulation rate.
It is quantized into a k-bit (k is a positive integer) digital signal by a clock signal (2f _S )C that is twice f _S . MSB of n-bit quantized signal D of I channel
and the signal E which is the MSB of the k-bit quantized signal of the Q channel are B.FF12a, 12, respectively.
The sampling is delayed at a rate f _S at b. In this case, the clock signal C of 2f _S (synchronized with the reference clock of f _S ) is passed through the frequency divider 13 to 2
The frequency-divided clock signal (f _S ) F is D・FF12a,
12b's clock input (ck).
The output signals G and H of the D-FFs 12a and 12b are delayed by sampling at a speed of f _S in the D-FFs 22c and d, respectively, and the signals G and H are input to the Ex-ORs 14a and 14b, respectively, and
By performing exclusive OR with each of the FFs 12a and 12b, zero crossings of the I channel and Q channel are detected.

The Ex•ORs 14a and 14b output "1" as signals L and M when a zero crossing is detected, and "0" when no zero crossing is detected, respectively. AND circuit 15
takes the AND of the signals L and M, detects that the polarities of the demodulated signals of the I channel and Q channel are inverted at the same time, and detects "1" when the polarity inversion (zero crossing) of both channels is detected. If not, the circuit outputs "0" as the output signal N. The k bits of the k bit quantized signal D of the I channel are D.FF1.
2e, the sampling is delayed at a rate of _S. Here, the clock ( _S )R obtained by inverting the clock signal F with a speed of _fS by the inverter 16 is D.
It is applied to the clock input (ck) of FF12e. The output signal S of D・FF12e is D・FF12f
The sampling is delayed by a clock f _S at . The output signal U of the D.FF 22f is a sample value at the zero crossing point of the k-bit quantized signal D of the I channel, but the polarity of the signal U does not correspond correctly to the delay or advance of the clock timing.

Similar to the conventional clock phase error detection circuit, in order to correspond to the clock timing advance as a positive phase error detection value and the delay as a negative value,
The polarity of the output signal U of the DFF 12f is inverted in the polarity inverting circuit 17 when the output signal J of the D.FF 12c is "1", and the polarity is not inverted when the signal J is "0". The output signal W of the polarity inversion circuit 17 becomes a clock phase error signal W whose polarity correctly corresponds to the delay or advance of the clock timing. Selection circuit 18
selects signal W when the output of the AND circuit 15 is "1" (when zero crossing is detected in I and Q channels), and when the output of AND circuit 15 is "0" (when no zero crossing is detected in I and Q channels) This circuit selects and outputs the signal X(0) when The output signal Y of the selection circuit 18 is a clock phase error signal. When the clock timing is correct, the average value of the output signal Y converges to zero.

According to the above clock phase error detection circuit, 2
A zero-crossing detection circuit is provided for each of the demodulated signals of the series, and by taking the logic seat of these zero-crossing detection circuits, clock phase errors are detected only when two series of demodulated signals simultaneously zero-cross. I can do it. That is, in FIG. 4b, times T ₂ and T ₄
It is clear that the clock phase error value at is the correct value. Therefore, the clock phase error detection circuit of this embodiment is not affected by carrier phase error.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, by detecting the clock phase error only when zero crossings are simultaneously detected by two series of demodulated signals, accurate clock phase error can be achieved even when there is a carrier phase error. It is effective in detecting

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a clock phase error detection circuit according to the present invention, FIG. 2 is a block diagram showing an example of the configuration of a conventional clock phase error circuit, and FIG. Figures 4a and 4b are diagrams for explaining the polarity of the detected values of clock phase errors at delays and zero crossings, and are time charts showing a space diagram of the demodulated signal and waveform examples of the demodulated signals of the I channel and Q channel, respectively. It is. In the figure, 11a, 11b, 21 are A/D converters, 12a, 12b, 12c, 12d, 12
e, 12f, 22a, 22b, 22c, 22d are D-FF (D flip-flop), 13, 23 are frequency dividers, 14a, 14b, 24 are Ex-OR, 15
is an AND circuit, 16, 25 is an inverter, 17, 26
is a polarity inversion circuit, and 18 and 27 are selection circuits.

Claims (1)

[Claims] 1 n-phase phase modulation signal (n is a positive integer and n>2)
Input two demodulated signal sequences obtained by orthogonal _{demodulation of}
(=1/2f _S ), respectively, to sample the demodulation string and convert the analog signal into a digital signal; first and second zero-crossing detection circuits which detect zero-crossings of digital data from odd-numbered sample data by inputting the output signal of An AND circuit that calculates the AND of the detection circuit and detects the simultaneous occurrence of zero crossing between two series of data; A polarity inversion circuit that inverts the polarity with the polarity of the immediately previous sample value and the output signal of the logic circuit are input, and when the AND is "1", the output signal of the polarity inversion circuit is selected, and the AND is "0". 1. A clock phase error detection circuit comprising: a selection circuit for selecting an output signal indicating zero error when .