JPH0480154U - - Google Patents

Info

Publication number
JPH0480154U
JPH0480154U JP1990124780U JP12478090U JPH0480154U JP H0480154 U JPH0480154 U JP H0480154U JP 1990124780 U JP1990124780 U JP 1990124780U JP 12478090 U JP12478090 U JP 12478090U JP H0480154 U JPH0480154 U JP H0480154U
Authority
JP
Japan
Prior art keywords
signal
error
measurement signal
error measurement
under test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990124780U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990124780U priority Critical patent/JPH0480154U/ja
Publication of JPH0480154U publication Critical patent/JPH0480154U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Monitoring And Testing Of Exchanges (AREA)
  • Dc Digital Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例に係わる誤り測定装
置の概略構成を示すブロツク図、第２図は同実施
例装置の信号遮断検出回路を示すブロツク図、第
３図は同信号遮断検出回路の動作を示すタイムチ
ヤートである。 １……送信クロツク信号発生回路、２……信号
送信回路、３……被試験装置、４……擬似ランダ
ム信号発生回路、５……同期遅延回路、６……信
号受信回路、７……信号遮断検出回路、８……比
較パターン発生回路、９……誤り測定回路、１０
……同期外れ検出回路、１１……マイクロコンピ
ユータ、１５……ＣＰＵ、２０……スピーカ、２
１……スピーカ制御回路。 Fig. 1 is a block diagram showing a schematic configuration of an error measuring device according to an embodiment of the present invention, Fig. 2 is a block diagram showing a signal cutoff detection circuit of the same embodiment, and Fig. 3 is a block diagram showing the signal cutoff detection circuit of the same embodiment. This is a time chart showing the operation. DESCRIPTION OF SYMBOLS 1... Transmission clock signal generation circuit, 2... Signal transmission circuit, 3... Device under test, 4... Pseudo random signal generation circuit, 5... Synchronous delay circuit, 6... Signal receiving circuit, 7... Signal Interruption detection circuit, 8... Comparison pattern generation circuit, 9... Error measurement circuit, 10
... Out-of-synchronization detection circuit, 11 ... Microcomputer, 15 ... CPU, 20 ... Speaker, 2
1...Speaker control circuit.

Claims (1)

【実用新案登録請求の範囲】 誤り測定信号を被試験装置へ送信して、この被
試験装置内を経由して出力された前記誤り測定信
号を受信して、この受信した誤り測定信号の各ビ
ツトデータが前記送信した誤り測定信号の各ビツ
トデータに一致するか否かを調べて不一致の場合
に誤り検出信号を出力すると共に、前記被試験装
置から出力される誤り測定信号が正常に検出され
ない場合に警報信号を出力する誤り測定装置にお
いて、 前記誤り検出信号と前記警報信号とを互いに異
なる音色で音出力することを特徴とする誤り測定
装置。[Claims for Utility Model Registration] Transmitting an error measurement signal to a device under test, receiving the error measurement signal outputted through the device under test, and analyzing each bit of the received error measurement signal. It checks whether the data matches each bit data of the transmitted error measurement signal and outputs an error detection signal if they do not match, and if the error measurement signal output from the device under test is not normally detected. What is claimed is: 1. An error measuring device that outputs an alarm signal to a user, wherein the error detection signal and the alarm signal are output with different tones.
JP1990124780U 1990-11-27 1990-11-27 Pending JPH0480154U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990124780U JPH0480154U (en) 1990-11-27 1990-11-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990124780U JPH0480154U (en) 1990-11-27 1990-11-27

Publications (1)

Publication Number Publication Date
JPH0480154U true JPH0480154U (en) 1992-07-13

Family

ID=31872411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990124780U Pending JPH0480154U (en) 1990-11-27 1990-11-27

Country Status (1)

Country Link
JP (1) JPH0480154U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238097U (en) * 1975-02-28 1977-03-17
JPH01231546A (en) * 1988-03-11 1989-09-14 Nec Corp Alarm display system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238097U (en) * 1975-02-28 1977-03-17
JPH01231546A (en) * 1988-03-11 1989-09-14 Nec Corp Alarm display system

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