JPH0481038A - Synchronized pull-in system for communication system - Google Patents

Abstract

PURPOSE:To enable synchronized pull-in instantaneously after a power source is applied on by detecting how much the synchronizing signal of a self station is advanced to that of a high-order station by the application the power source, and immediately adjusting timing for transmitting the synchronizing signal of the self station. CONSTITUTION:When the power source of the system is applied, a power source application detection circuit 7 detects it and outputs a power source application signal E and when this signal E is outputted, an absolute value difference detection circuit 8 outputs a half value signal F to a reset pulse preparation circuit 10 based on time difference signals C and D. On the other hand, when the power source application detection circuit 7 outputs the power source application signal E, a control direction detection circuit 9 detects it based on the time difference signals C and D whether time difference (c) or (d) expressed by these signals is larger, and outputs a control signal G expressing the result to the reset pulse preparation circuit 10. Based on the signal F from the absolute value difference detection circuit 8, the reset pulse preparation circuit 10 outputs a reset pulse to a frequency divider circuit 3 so as to fasten the transmission of transmission timing A only for ¦c-d¦/2. Thus, after the power source is turned on, synchronized pull-in can be executed instantaneously.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a synchronization pull-in method for a communication system that performs sampling time synchronization to synchronize the synchronization signal of a local station to the synchronization signal of a higher-level station, and particularly relates to a synchronization pull-in method for a communication system that performs sampling time synchronization to synchronize a synchronization signal of a local station with a synchronization signal of a higher-level station. This relates to a synchronous pull-in method immediately after the power is turned on.

[Conventional technology]

FIG. 3 shows an example of a communication system based on the conventional synchronous pull-in method. The oscillator 1 generates a signal of a predetermined frequency higher than the transmission timing A, that is, the synchronization signal of its own station. The automatic phase control circuit 2 receives and receives a signal from the oscillator 1, controls its phase based on a signal from a comparison circuit 6, which will be described later, and outputs the signal. Then, the frequency dividing circuit 30 divides the frequency of the signal from the control circuit 2 and outputs it at transmission timing A, that is, as a synchronization signal of its own station. The upper station receiving section 4
It receives a signal from the upper station, and outputs the synchronization signal B of the upper station and a time difference signal representing the time difference between the synchronization signal of the upper station and the synchronization signal of the own station at the upper station. The time measurement circuit 5 measures the time difference between the transmission timing (synchronization signal of its own station) A and the synchronization signal B of the upper station, and outputs a time difference signal C representing the time difference between these two signals. The comparator circuit 6 receives the signal from the upper station receiving section 4 and the signal C from the time measuring circuit 5, and outputs a signal representing the time difference represented by these signals to the automatic phase control circuit 2.

Immediately after turning on the power for startup in such a communication system, the phase of the synchronization signal of the local station and the phase of the synchronization signal of the higher-level station that the local station should follow do not match, and the two synchronization The signals are asynchronous. At this time, each part operates as follows. The frequency dividing circuit 3 divides the frequency of the signal from the automatic phase control circuit 2 and outputs the divided signal, and the time measuring circuit 5 calculates the transmission timing A from the frequency dividing circuit 3 and the upper station receiving section 4.
It measures the time difference with the synchronization signal B of the higher-level station output by the station, and outputs a signal C representing the result. The comparator circuit 6 receives this signal C and a signal representing the time difference between the synchronization signal of the upper station and the synchronization signal of the own station in the upper station outputted by the receiving section 4, and calculates the time difference c represented by these signals, A signal representing the difference in d is output. The automatic phase control circuit 2 receives and receives the signal from the comparator circuit 6, controls the phase of the signal from the oscillator 1 in a direction to match the time differences c and d, and outputs it to the frequency divider circuit 30. By repeating such operations, the time differences c and d gradually approach each other, and eventually the synchronization signal B of the upper station and the transmission timing A match in phase, resulting in a synchronized state.

By the way, the time required for the phase difference between the two synchronization signals to disappear after the power is turned on, that is, the synchronization pull-in time, is determined by the phase difference between the synchronization signal of the local station and the synchronization signal of the upper station, and the control width in the control circuit 2. , and the control frequency in the control circuit 2. It is desirable that this synchronization pull-in time be as short as possible, and conventionally, the synchronization pull-in time has been shortened by changing the control frequency in stages and increasing the control frequency as necessary.

[Problem to be solved by the invention]

However, simply changing the control frequency in this way is not enough, and in the conventional communication system using the synchronous pull-in method, it still takes a long time to perform the synchronous pull-in.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous pull-in method for a communication system that can solve these problems and complete synchronous pull-in immediately after power is turned on.

[Means to solve the problem]

The present invention provides a synchronization pull-in method for a communication system that synchronizes a synchronization signal of its own station outputted by a frequency dividing circuit with a synchronization signal of a higher-level station. a first time difference, which is a time difference between the synchronization signal of the upper station outputted by the reception unit and the synchronization signal of the own station outputted by the frequency dividing circuit, and a first time difference representing the measurement result. a time measurement circuit that outputs a time difference signal of 1; and a time measurement circuit that receives a signal from the upper station and represents a second time difference that is a time difference between the synchronization signal of the upper station and the synchronization signal of the own station in the upper station. a second receiving section that outputs a second time difference signal; a power-on detection circuit that detects when the power of the own station device is turned on and outputs a predetermined detection signal; and this power-on detection circuit. outputs the detection signal,
an absolute value difference detection circuit that calculates the absolute value of the difference between the two time differences using the first time difference signal and the second time difference signal, and outputs an absolute value difference signal representing a value proportional to the absolute value; When the power-on detection circuit outputs the detection signal,
a control direction detection circuit that compares the magnitude of the two time differences using the first time difference signal and the second time difference signal and outputs a control signal representing a magnitude relationship between the two time differences; and the absolute value detection circuit. Based on the absolute value difference signal outputted by the circuit and the control signal outputted by the control direction detection circuit, when the first time difference is smaller than the second time difference, only the time represented by the absolute value difference signal is determined. A reset pulse is outputted to the frequency dividing circuit to speed up the sending timing of the synchronization signal of the own station, and when the first time difference is larger than the second time difference, the time difference represented by the absolute value difference signal is increased. The present invention is characterized in that it further includes a reset pulse generation circuit that outputs a reset pulse to the frequency divider circuit for delaying the sending timing of the synchronization signal of the own station.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a communication system using a synchronous pull-in method according to the present invention.

The oscillator 1 generates a signal of a predetermined frequency higher than the transmission timing A, that is, the synchronization signal of its own station.

The automatic phase control circuit 2 receives and receives a signal from the oscillator 1, controls its phase based on a signal from a comparator circuit 6, which will be described later, and outputs the signal. And the frequency divider circuit 3 is the control circuit 2
The frequency of the signal from the station is divided and output at transmission timing A, that is, as the synchronization signal of the own station.

The upper station receiving section 4 receives a signal from the upper station, and outputs the synchronization signal B of the upper station and a time difference signal representing the time difference between the synchronization signal of the upper station and the synchronization signal of the own station in the upper station.

The time measurement circuit 5 is the transmission timing (synchronization signal of own station) A
and the synchronization signal B of the upper station is measured, and a time difference signal C representing the time difference between these two signals is output. The comparator circuit 6 receives the signal from the upper station receiving section 4 and the signal C from the time measuring circuit 5, and outputs a signal representing the time difference represented by these signals to the automatic phase control circuit 2.

The power-on detection circuit 7 detects when the communication system is powered on, and outputs a power-on signal E indicating that the power has been turned on.

When the absolute value difference detection circuit 8 receives the power-on signal E from the power-on detection circuit 7, it calculates the absolute value 1 cmdl of the difference between the time differences c and d expressed by these signals based on the time difference signals C and D. A half-value signal F representing the obtained result 1c-dl/2 is output.

When the control direction detection circuit 9 receives the power-on signal E from the power-on detection circuit 7, it detects which of the time differences represented by these signals is larger based on the time difference signals C and D, and outputs a control signal G representing the result. Output. Based on the signals F and G, the reset pulse generation circuit 10 generates a reset pulse (pulse width is 1c-dl/ 2) is output to the frequency divider circuit 3, and on the other hand, when the time difference C is larger than the time difference d, (c>d)
Reset pulse to delay sending of transmission timing A by 1c-dl/2 (pulse width is 1cmdl/2)
(proportional to) is output to the frequency divider circuit 3.

Next, the operation will be explained. First, under normal conditions after a sufficient period of time has passed since the communication system was powered on, the following will occur:
This works. The frequency dividing circuit 3 divides the frequency of the signal from the automatic phase control circuit 2 and outputs it, and the time measuring circuit 5 uses the transmission timing A from the frequency dividing circuit 3 and the upper The time difference with the synchronization signal B of the station is measured and a signal C representing the result is output. The comparison circuit 6 receives this signal C and a signal representing the time difference between the synchronization signal of the upper station and the synchronization signal of the own station in the upper station outputted by the receiving section 4, and calculates the time difference c represented by these signals, A signal representing the difference in d is output. The automatic phase control circuit 2 receives and receives the signal from the comparator circuit 6, and controls the oscillator 1 in a direction to match the time difference Cd.
It controls the phase of the signal from and outputs it to the frequency divider circuit 3. By repeating this operation, the time difference c
, d gradually approach each other, and eventually the phase difference between the synchronization signal B of the upper station and the transmission timing A caused by the transmission delay is eliminated, and synchronization is achieved.

Next, the synchronization pull-in operation immediately after the communication system is powered on will be described. When the power of the system is turned on, the power-on detection circuit 7 detects it and sends the power-on signal E.
Output. When this signal E is output, the absolute value difference detection circuit 8 calculates the absolute value of the difference between the time differences c and d expressed by the time difference signals C and D based on the time difference signals C and D.
It is further divided by 2, and a half-value signal F representing the obtained result l c - d l/2 is output to the reset pulse generation circuit 10 . On the other hand, when the power-on detection circuit 7 outputs the power-on signal E, the control direction detection circuit 9 detects which of the time differences c and d expressed by these signals is larger based on the time difference signals C and D, and outputs the result. A control signal G representing the reset pulse generation circuit 10 is outputted to the reset pulse generation circuit 10.

FIG. 2(a) shows the time relationship between the synchronization signal B of the upper station and the transmission timing A (synchronization signal of the own station) when the time difference C is smaller than the time difference d, and the arrow a indicates the transmission timing A.
The arrow represents the phase of the synchronization signal B of the upper station, respectively. The difference between the start point of arrow a and the end point of arrow corresponds to the time difference C between the two synchronization signals at the own station, and the difference between the end point of arrow a and the start point of arrow corresponds to the time difference d between the two synchronization signals at the upper station. It corresponds to As can be seen from this figure, the deviation between the starting points of the two arrows, that is, the deviation between the two synchronization signals, is: cdl/2.

In the reset pulse generation circuit 10, the control signal G has a time difference C.
is smaller than the time difference d, based on the signal F from the absolute value difference detection circuit 8, outputs a reset pulse to the frequency dividing circuit 3 to advance the sending of the transmission timing A by 1c-dl2. . As a result, the transmission timing A is represented by an arrow a', and the phases of the two synchronization signals match.

On the other hand, Fig. 2(b) shows the time relationship between the synchronization signal B of the upper station and the transmission timing A (synchronization signal of the own station) when the time difference C is larger than the time difference d, and Fig. 2(a) Similarly, the arrow a represents the phase of the transmission timing A, and the arrow represents the phase of the synchronization signal B of the upper station. The difference between the start point of arrow a and the end point of arrow corresponds to the time difference C between the two synchronization signals at the own station, and the difference between the end point of arrow a and the start point of arrow corresponds to the time difference d between the two synchronization signals at the upper station. It corresponds to The deviation between the starting points of the two arrows, that is, the deviation between the two synchronization signals, is 1c-dl/2.

In the reset pulse generation circuit 10, the control signal G has a time difference C.
is larger than the time difference d, based on the signal F from the absolute value difference detection circuit 8, outputs a reset pulse to the frequency dividing circuit 3 to delay the sending to the transmission timing by 1 cmd/2. do. As a result, the transmission timing A is represented by an arrow a', and the phases of the two synchronization signals match.

In this way, in the communication system using the synchronization pull-in method of the present invention, when the power is turned on, it is detected how far the synchronization signal of the own station is ahead or behind the synchronization signal of the upper station, and the detection result is Based on this, the timing of sending out the synchronization signal of the own station is immediately adjusted. Therefore, synchronization pull-in after power-on is completed instantly.

In this embodiment, the absolute value difference detection circuit 8 detects the time difference c,
The absolute value IC-dl of the difference in d was calculated and further divided by 2, but this dividing number does not necessarily need to be limited to 2.
A predetermined effect can also be obtained with other numbers close to 2. In other words, in that case, even though the operation of the reset pulse generation circuit 10 does not completely eliminate the phase difference between the synchronization signal of the upper station and the synchronization signal of the local station, it is possible to reduce the phase difference to some extent, and therefore the subsequent Synchronization pull-in by the automatic phase control circuit 2 can be completed in a short time.

〔Effect of the invention〕

As explained above, the present invention provides a synchronization pull-in method for a communication system that synchronizes the synchronization signal of its own station outputted by a frequency dividing circuit with the synchronization signal of a higher-level station. A first receiving section that outputs the first receiving section, and a first time difference that is the time difference between the synchronizing signal of the upper station outputted by this receiving section and the synchronizing signal of the own station outputted by the frequency dividing circuit, and the measurement result is expressed. A time measurement circuit that outputs a first time difference signal, and a second time measurement circuit that receives a signal from an upper station and measures the time difference between the synchronization signal of the upper station and the synchronization signal of the own station at the upper station.
a second receiving section that outputs a second time difference signal representing a time difference between the two; a power-on detection circuit that detects when the local device is powered on and outputs a predetermined detection signal;
When this power-on detection circuit outputs a detection signal, the first
an absolute value difference detection circuit that calculates the absolute value of the difference between the two time differences using the time difference signal and the second time difference signal, and outputs an absolute value signal representing a value proportional to the absolute value; and a power-on detection circuit. a control direction detection circuit that, when outputting a detection signal, compares the magnitude of the two time differences using a first time difference signal and a second time difference signal, and outputs a control signal representing a magnitude relationship between these two time differences; , based on the absolute value difference signal outputted by the absolute value detection circuit and the control signal outputted by the control direction detection circuit, when the first time difference is smaller than the second time difference, the own station is operated for only the time represented by the absolute value difference signal. A reset pulse is output to the frequency divider circuit to speed up the sending timing of the synchronization signal of the station, and when the first time difference is larger than the second time difference, the synchronization signal of the own station is sent out for the time represented by the absolute value difference signal. The present invention is characterized in that it includes a reset pulse generation circuit that outputs a reset pulse for delaying the timing to a frequency dividing circuit.

Therefore, in the communication system using the synchronization pull-in method of the present invention, when the power is turned on, it is detected how far the synchronization signal of the local station is ahead or behind the synchronization signal of the higher-level station, and based on the detection result, The timing of sending out the synchronization signal of the own station is immediately adjusted. Therefore, synchronization pull-in after power-on is completed instantly. Specifically, while synchronization pull-in conventionally required several seconds of time, this system requires only 1/1000 of a second.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of a communication system using the synchronous pull-in method according to the present invention, Fig. 2 is a timing diagram for explaining the operation of the communication system of Fig. 1, and Fig. 3 is a conventional synchronous pull-in method. 1 is a block diagram illustrating an example of a communication system based on this method. 1... Oscillator 2... Automatic phase control circuit Frequency dividing circuit Upper station receiving section Time measurement circuit Comparison circuit Power-on detection circuit Absolute value difference detection circuit Control direction detection circuit Reset pulse generation circuit

Claims (2)

[Claims] (1) In a synchronization pull-in method for a communication system that synchronizes the synchronization signal of its own station outputted by a frequency dividing circuit with the synchronization signal of a higher-level station, a first circuit that receives a signal from the higher-level station and outputs a synchronization signal of the higher-level station; and a first time difference that is a time difference between the synchronization signal of the upper station outputted by the reception unit and the synchronization signal of the own station outputted by the frequency dividing circuit, and a first time difference representing the measurement result. a time measurement circuit that outputs a time difference signal; and a time measurement circuit that receives a signal from the upper station and represents a second time difference that is a time difference between the synchronization signal of the upper station and the synchronization signal of the own station in the upper station. a second receiving section that outputs a time difference signal of 2; a power-on detection circuit that detects when the power of the own station device is turned on and outputs a predetermined detection signal; and this power-on detection circuit When the detection signal is output,
an absolute value difference detection circuit that calculates the absolute value of the difference between the two time differences using the first time difference signal and the second time difference signal, and outputs an absolute value difference signal representing a value proportional to the absolute value; When the power-on detection circuit outputs the detection signal,
a control direction detection circuit that compares the magnitude of the two time differences using the first time difference signal and the second time difference signal and outputs a control signal representing a magnitude relationship between the two time differences; and the absolute value detection circuit. Based on the absolute value difference signal outputted by the circuit and the control signal outputted by the control direction detection circuit, when the first time difference is smaller than the second time difference, only the time represented by the absolute value difference signal is determined. A reset pulse is outputted to the frequency dividing circuit to speed up the sending timing of the synchronization signal of the own station, and when the first time difference is larger than the second time difference, the time difference represented by the absolute value difference signal is increased. A synchronization pull-in method for a communication system, comprising: a reset pulse generation circuit that outputs a reset pulse to the frequency divider circuit to delay the transmission timing of the synchronization signal of the own station. (2) The absolute value difference detection circuit calculates the absolute value of the difference between the two time differences using the first time difference signal and the second time difference signal, and generates an absolute value representing a value obtained by dividing the absolute value by 2. 2. The synchronization pull-in method for a communication system according to claim 1, wherein a value difference signal is output.