JPH0481879B2 - - Google Patents
Info
- Publication number
- JPH0481879B2 JPH0481879B2 JP21634684A JP21634684A JPH0481879B2 JP H0481879 B2 JPH0481879 B2 JP H0481879B2 JP 21634684 A JP21634684 A JP 21634684A JP 21634684 A JP21634684 A JP 21634684A JP H0481879 B2 JPH0481879 B2 JP H0481879B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- holes
- hole
- multilayer wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は混成集積回路用多層配線板とくに高速
信号伝送用多層配線板におけるスルホールの構成
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a structure of through-holes in a multilayer wiring board for hybrid integrated circuits, particularly in a multilayer wiring board for high-speed signal transmission.
電子計算機に使用される混成集積回路の高速信
号伝送用多層配線板においては、高密度化・絶縁
層の低誘電率化をはかるため、薄膜化の方向で検
討が進められている。この場合、半導体工業での
絶縁層の厚さに比較して５〜20倍の厚さが必要で
あるが、このような絶縁層では、スルホールを経
由しての配線接続はスルホール内に絶縁層厚さに
見合う厚さの配線材を埋める必要があるため、製
造工程が複雑となつて現実性に乏しい。
In multilayer wiring boards for high-speed signal transmission of hybrid integrated circuits used in electronic computers, studies are progressing toward thinning the film in order to increase the density and lower the dielectric constant of the insulating layer. In this case, the thickness of the insulating layer is required to be 5 to 20 times the thickness of the insulating layer used in the semiconductor industry. Since it is necessary to fill the wiring material with a thickness corresponding to the thickness, the manufacturing process becomes complicated and impractical.
これに対して、昭和58年度通信学会半導体、材
料部会全国大会用講演集における高木氏らによる
「厚い樹脂絶縁膜を用いた多層配線の形成」で論
じられている。然るに、この論文では各絶縁層ご
とにスルホールの位置をズラして形成する方法で
あるため、スルホール位置が絶縁層ごとに異なる
ので、配線の布設に大きな制約があつて現実性に
乏しい。 On the other hand, this is discussed in ``Formation of multilayer wiring using thick resin insulating films'' by Mr. Takagi et al. in the collection of lectures for the 1985 National Conference of the Semiconductor and Materials Subcommittee of the Communications Society of Japan. However, in this paper, the method of forming through-holes is shifted for each insulating layer, and as the through-hole positions differ from insulating layer to insulating layer, there are significant restrictions on wiring installation, making this method impractical.
本発明は上記従来の問題点を解決し、各絶縁層
の積層時のスルホールの位置をズラすことなく、
厚い絶縁層のスルホールを経ての良好な配線接続
を可能とする多層配線板を提供することにある。
The present invention solves the above-mentioned conventional problems, and without shifting the position of through holes when laminating each insulating layer,
An object of the present invention is to provide a multilayer wiring board that enables good wiring connections through through holes in a thick insulating layer.
本発明は上記の目的を達成するため、各絶縁層
毎に設置されたスルホールを長方形状あるいは長
円形状に形成し、かつ上記スルホールの長手方向
を上下方向に相隣れるスルホールの長手方向と所
定角度、好ましくは90゜で交叉する如く形成し、
該各スルホールに充填されるとともに各スルホー
ルの周辺部に所定の厚さに形成された絶縁層と、
該絶縁層上に前記相隣れる上下スルホール間を電
気的に接続可能に形成されたスルホール接続用の
金属膜とを設けたことを特徴とするものである。
In order to achieve the above object, the present invention forms the through holes installed in each insulating layer in a rectangular or elliptical shape, and the longitudinal direction of the through holes is aligned with the longitudinal direction of the vertically adjacent through holes. formed so as to intersect at an angle, preferably 90°,
an insulating layer filled in each through hole and formed at a predetermined thickness around each through hole;
The present invention is characterized in that a metal film for through-hole connection is provided on the insulating layer so that the adjacent upper and lower through-holes can be electrically connected to each other.
以下本発明の実施例を示す第１図および第２図
について説明する。
1 and 2 showing embodiments of the present invention will be explained below.
第１図は本発明の実施例を示す多層配線基板の
平面図、第２図は多層配線板とくにスルホールの
製造工程図にして、そのａ〜ｉは第１図のＢ−Ｂ
矢視断面図、a′〜i′は第１図のＡ−A′矢視断面図
である。同図において、１は基板、２ａ〜２ｅは
スルホール接続用金属膜、３ａ〜３ｅは絶縁層、
４ａ〜４ｅはスルホールにして、長方形状をし、
その両端部を円弧状に形成している。また上記ス
ルホール４ａ〜４ｅはその長手方向を上下方向に
相隣れるスルホールの長手方向と角度90゜で交叉
する如くしている。５ａ，５ｂは配線金属膜であ
る。 FIG. 1 is a plan view of a multilayer wiring board showing an embodiment of the present invention, and FIG. 2 is a manufacturing process diagram of the multilayer wiring board, particularly through-holes, and a to i are B-B in FIG.
A' to i' are cross-sectional views taken along the line A-A' in FIG. 1. In the figure, 1 is a substrate, 2a to 2e are metal films for through-hole connection, 3a to 3e are insulating layers,
4a to 4e are through holes and have a rectangular shape,
Both ends thereof are formed into an arc shape. Further, the longitudinal direction of the through holes 4a to 4e intersects the longitudinal direction of the vertically adjacent through holes at an angle of 90 degrees. 5a and 5b are wiring metal films.
つぎに多層配線基板とくにスルホールの製造工
程を第２図により述べる。同図ａ，a′は基板１上
にスルホール接続用金属膜２ａと、スルホール４
ａを有する絶縁層３ａとを形成した状態である。
この上に第２図ｂ，b′に示すように、Alなどをス
パツタなどで成膜したのち、ホトエツチング工程
により接続用金属膜２ｂを形成する。ついで、第
２図ｃ，c′に示すようにポリイミドワニスを上記
接続用金属膜２ｂ上に塗布し、所定の厚さに成形
したのち熱処理で硬化して絶縁層３ｂを形成す
る。然る後、上記スルホール４ａの長手方向と、
角度90゜で交叉するごとくスルホール４ｂを上記
絶縁層３ｂ上に形成する。上記スルホール４ｂは
ホトリソグラフ工程即ち上記絶縁層３ｂ上にホト
マスクの転写パターンをホトレジストで形成し、
このホトレジストをマスクとしてヒトラジン等の
ポリイミドを溶解するエツチング液に浸漬し、こ
れを上記絶縁層３ｂ上に金属膜２ｂが露出すると
ころ停止する。そのため、第２図ｃに示すように
スルホール４ａ〔同図ａ〕は、絶縁層３ｂによつ
て埋められいてる。ついで第２図ｄに示すよう
に、上記絶縁層３ｂ上に前述と同一方法で接続用
金属膜２ｃを形成する。このとき上記２個のスル
ホール４ａ，４ｂとの接続が２個の接続用金属膜
２ｂ，２ｃとで達成される。以下第２図ｅ，e′〜
ｉ，i′に示す如く、上記の作用を繰り返すことに
より第２図ｉ，i′に示すようにスルホール４ｅの
底面が平坦な面をした絶縁層３ｅを有する多層配
線板が形成される。 Next, the manufacturing process of a multilayer wiring board, particularly a through hole, will be described with reference to FIG. Figures a and a' show a metal film 2a for connecting through holes and a through hole 4 on a substrate 1.
This is a state in which an insulating layer 3a having a layer a is formed.
As shown in FIGS. 2b and 2b', a film of Al or the like is formed thereon by sputtering or the like, and then a connecting metal film 2b is formed by a photo-etching process. Then, as shown in FIGS. 2c and 2c', polyimide varnish is applied onto the connecting metal film 2b, molded to a predetermined thickness, and then hardened by heat treatment to form an insulating layer 3b. After that, the longitudinal direction of the through hole 4a,
Through holes 4b are formed on the insulating layer 3b so as to intersect at an angle of 90°. The through holes 4b are formed by a photolithography process, that is, a transfer pattern of a photomask is formed using photoresist on the insulating layer 3b,
Using this photoresist as a mask, the photoresist is immersed in an etching solution that dissolves polyimide such as hytrazine, and the process is stopped when the metal film 2b is exposed on the insulating layer 3b. Therefore, as shown in FIG. 2c, the through hole 4a (FIG. 2a) is filled with the insulating layer 3b. Then, as shown in FIG. 2d, a connecting metal film 2c is formed on the insulating layer 3b by the same method as described above. At this time, connection to the two through holes 4a, 4b is achieved by the two connection metal films 2b, 2c. Below, Figure 2 e, e'~
By repeating the above-described operations as shown in FIG. 2 i and i', a multilayer wiring board having an insulating layer 3e with a flat bottom surface of the through hole 4e is formed as shown in FIG. 2i and i'.
本発明は以上述べたる如く、絶縁層形成時にス
ルホールの穴埋めを行いながら、絶縁層を積重す
るので、絶縁層がたとえ厚い場合でも、スルホー
ルの位置をズラすことなく良好なスルホールの接
続を行うことができる。
As described above, the present invention stacks insulating layers while filling through holes when forming an insulating layer, so even if the insulating layer is thick, good through-hole connections can be made without shifting the positions of the through holes. be able to.
第１図は本発明の実施例を示す多層配線板の平
面図、第２図は多層配線板のスルホール部分の製
造工程を示す説明図である。
１……基板、２ａ〜２ｅ……スルホール接続用
金属膜、３ａ〜３ｅ……絶縁層、４ａ〜４ｅ……
スルホール、５ａ，５ｂ……配線金属膜。
FIG. 1 is a plan view of a multilayer wiring board showing an embodiment of the present invention, and FIG. 2 is an explanatory view showing the manufacturing process of a through-hole portion of the multilayer wiring board. DESCRIPTION OF SYMBOLS 1... Substrate, 2a-2e... Metal film for through-hole connection, 3a-3e... Insulating layer, 4a-4e...
Through holes, 5a, 5b...wiring metal film.
Claims (1)
とを複数個積重し、上記各絶縁層にスルホールを
形成した多層配線板において、形状が長方形また
は長円形に形成され、かつ相隣れる上下を直交状
態に配置されてなるスルホールと、該各スルホー
ルに充填されるとともに各スルホールの周辺部に
所定の厚さに形成された絶縁層と、該絶縁層上に
前記相隣れる上下スルホール間を電気的に接続可
能に形成されたスルホール接続用の金属膜とを設
けたことを特徴とする多層配線板。1. In a multilayer wiring board in which a plurality of through-hole connection metal films and insulating layers are stacked on a substrate and through-holes are formed in each of the insulating layers, the shape is rectangular or oval, and adjacent upper and lower an insulating layer filled in each through hole and formed to a predetermined thickness around the through hole, and a layer formed on the insulating layer between the adjacent upper and lower through holes. A multilayer wiring board characterized by being provided with a metal film for through-hole connection formed to be electrically connectable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21634684A JPS6196796A (en) | 1984-10-17 | 1984-10-17 | multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21634684A JPS6196796A (en) | 1984-10-17 | 1984-10-17 | multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6196796A JPS6196796A (en) | 1986-05-15 |
| JPH0481879B2 true JPH0481879B2 (en) | 1992-12-25 |
Family
ID=16687108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21634684A Granted JPS6196796A (en) | 1984-10-17 | 1984-10-17 | multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6196796A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63155691A (en) * | 1986-12-18 | 1988-06-28 | 株式会社東芝 | Maltilayer interconnection circuit board |
-
1984
- 1984-10-17 JP JP21634684A patent/JPS6196796A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6196796A (en) | 1986-05-15 |
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