JPH0481925A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To shorten the processing time of data, and also, to reduce the capacity of program data by completing multiplication by one step. CONSTITUTION:The circuit is provided with a multiplier data memory 11 and a multiplicand data memory 12 for storing multiplier data and multiplicand data, respectively, and an address of the multiplier data memory 11 is designated, based on an output of an address register 10 subjected to increment or decrement in accordance with an arithmetic operation of a multiplier 5. Accordingly, it becomes unnecessary to designate simultaneously address of two memories 11, 12 irrespective of a fact that multiplication is completed by one step. In such a way, an arithmetic speed can be improved without being accompanied with a remarkable increase of a circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a digital signal processing circuit that multiplies digital data.

(b) Conventional technology DSP (Digi
-tal Signal Processor), a sum-of-products operation is frequently performed in which specific digital data is added to the data to be processed as a filter coefficient. This data to be processed is stored in a memory such as a static RAM that can be written and read freely, is once taken into a register each time a product-sum operation is performed, and is input from the register to a multiplier.

FIG. 2 is a block diagram showing the configuration of a digital signal processing circuit that performs multiplication as described above.

The data memory (1) stores various digital data serving as a multiplier and a multiplicand, and the multiplier data and the multiplicand data are sequentially read out in accordance with a read control signal from a control circuit (2). The multiplier data and multiplicand data read from this data memory (1) are respectively input to the input register (3) (
4) and is supplied to the multiplier (5) from the input registers (3) and (4). Input register (3) (4)
In this case, multiplier data and multiplicand data read out in time series from a data memory (1) are stored one data at a time, and are input to the multiplier (5) at a timing that follows the arithmetic operation of the multiplier (5). Then, the calculation result of the multiplier (5) is stored in the output register (6), and the next stage circuit (
(Drawing omitted).

On the other hand, the control circuit (2) that controls the arithmetic operation is connected to a program memory (7) in which an operation program for the arithmetic operation is stored.
It consists of a command register (8) that takes in the read program data, and a decoder (9) that decodes the program data and sends instructions to each part, and is configured so that calculations are executed according to the program data. That is, the program memory (7) stores data such as address designations for the data memory (1) and operation execution instructions in a predetermined order, and these data are sequentially read out and stored in the program memory (1) and the multiplier. (5), the calculation operation of the circuit is controlled.6 For example, in filter calculation, etc., in the first step, the multiplication data that becomes the filter coefficient is read from the data memory (1) and input register (3), and in the second step, the multiplicand data is read from the data memory (1) and input register (4).
), each data is supplied from each input register (3), (4) to a multiplier (5), and multiplication is executed. Then, by repeating the first and second steps, the predetermined calculation can be completed.

(8) Problems to be Solved by the Invention However, in the data processing described above, there is a problem in that the calculation speed is slow because two steps are required to execute one multiplication. . In particular, data processing such as filter operation that repeats multiplication many times takes a long time to process the data. Furthermore, since it is necessary to supply a command from the control circuit (2) for each step of operation, the program data becomes long, increasing the capacity of the program memory (7) and causing an increase in the circuit scale. .

Furthermore, if the data memory (1) is divided into two parts and the multiplier data and multiplicand data are simultaneously supplied to the input registers (3) and (4), it becomes possible to perform calculations in one step. Since it is difficult to specify two addresses simultaneously with an instruction, it is necessary to make the operation instruction itself long. Therefore, the circuit size will increase significantly as the capacity of the program memory (7) increases and the number of bits of the command register (8) and decoder (9) increases.

Therefore, an object of the present invention is to improve the calculation speed without significantly increasing the circuit scale.

(d) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and is characterized by a first memory that stores first digital data serving as a multiplicand; , a second memory that stores second digital data that is a multiplier for the first digital data, and a first memory that receives the first and second digital data from each of these memories and accumulates the data for a certain period of time. and a second input register, and receives the first and second digital data from the first and second input registers, and multiplies the first digital data by the second digital data to obtain third digital data. an address register that obtains address data that increases or decreases according to the arithmetic operation of the multiplier, the address of the first memory is specified based on predetermined program data, and the second memory A digital signal processing circuit characterized in that an address of is specified based on address data of the address register.

(*) Effect According to the present invention, the address register is incremented or decremented according to the arithmetic operation of the multiplier to obtain address data and specify the address of the second memory, so that one arithmetic instruction can be executed. The addresses of the first and second memories can be specified simultaneously without increasing the length of time, and the operation can be completed in one step. Therefore, calculation speed can be improved without increasing program data or circuit configuration.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital signal processing circuit according to the present invention. In this figure, the control circuit (2) and multiplier (5) are the same as in FIG. 2, and the same parts are given the same reference numerals.

A feature of the present invention is that a multiplier data memory <11> and a multiplicand data memory (12) are provided for storing multiplier data and multiplicand data, respectively.
1) The address is designated based on the output of the address register (10) which is incremented or decremented according to the operation of the multiplier (5). That is,
The address register (10) has a counter structure that is incremented or decremented by 11 every time the multiplier (5) completes the operation, and when the operation is completed, the address of the multiplier data memory (11) is set to the next address. shifted to the address. The multiplier data memory (11) stores multiplier data that becomes filter coefficients in a predetermined order, and by shifting the address designation one by one, the multiplier data is stored in the input register (3) in the desired order. This means that the supply will be exhausted.

Generally, in product-sum operations such as filter operations, regular operations are repeatedly executed, so the multiplier data memory (
A desired operation can be performed by shifting the address of 11) according to the operation of the multiplier (5) and reading the multiplier data.

Here, the address of the multiplicand data memory (12) is designated by the control circuit (2) in the same manner as in FIG. 2, and the address designation data is stored in the program memory (7>).

Therefore, the control circuit (2) is connected to the multiplicand data memory (12).
When an instruction to execute an operation is supplied to the multiplier (5) at the same time as specifying the address of (11
) address can be moved to the next address. °For this reason,
The address of the multiplier data memory (11) is the address of the multiplier (5)
Each time the multiplication is completed, the address is moved to the next address, and the address can be designated in sequence without having to use the control circuit (2) to designate the address.

According to the above configuration, even though the multiplication is completed in one step, it is not necessary to specify the addresses of two memories at the same time, so the operation can be completed in a short time without increasing the length of the operation instruction.

(G) Effects of the Invention According to the present invention, since multiplication can be completed in one step, data processing time can be shortened, and the number of calculation instructions can be reduced by reducing the number of steps to execute calculations. Data capacity can be reduced.

Also, since there is no need to make one operation instruction long,
It is possible to prevent an increase in the circuit configuration of a control system circuit that controls the operation of each part.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital signal processing circuit of the present invention, and FIG. 2 is a block diagram of a conventional digital signal processing circuit. (1)...Data memory, (2)...Control circuit,
(3) (4)... Input register, (5)... Multiplier, (6)... Output register, <7)... Program memory, (8)... Command register, (9 )・
...Decoder, (10) ...Address register, (1
1)... Multiplicand data memory, (12)... Multiplicand data memory.

Claims (2)

[Claims] (1) A first memory that stores first digital data that is a multiplicand; a second memory that stores second digital data that is a multiplier for the first digital data; and a second memory that stores second digital data that is a multiplier for the first digital data. first and second input registers that receive and accumulate the first and second digital data for a certain period of time; and
digital data is received, and the second digital data is added to the first digital data.
a multiplier that obtains third digital data by multiplying the digital data of the multiplier, and an address register that obtains address data that increases or decreases according to the operation of the multiplier, and the address of the first memory is set to predetermined program data. and the address of the second memory is specified based on address data of the address register. (2) The digital signal processing circuit according to claim 1, wherein the addressing of the first memory and the arithmetic operation of the multiplier are set at timings according to a basic clock having a constant period.