JPH0483341A - Processing of semiconductor minute device - Google Patents

Processing of semiconductor minute device

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Publication number
JPH0483341A
JPH0483341A JP19834590A JP19834590A JPH0483341A JP H0483341 A JPH0483341 A JP H0483341A JP 19834590 A JP19834590 A JP 19834590A JP 19834590 A JP19834590 A JP 19834590A JP H0483341 A JPH0483341 A JP H0483341A
Authority
JP
Japan
Prior art keywords
etching
layer
substrate
semiconductor layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19834590A
Other languages
Japanese (ja)
Inventor
Hiroyuki Wakayama
若山 博之
Hiroshi Daiku
博 大工
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19834590A priority Critical patent/JPH0483341A/en
Publication of JPH0483341A publication Critical patent/JPH0483341A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily process a complicated and minute pattern by selectively etching a semiconductor substrate through using an etchant, of which etching speed changes depending upon the variation of high impurity concentration or difference in conductivity type. CONSTITUTION:Impurity atoms composed of boron atoms are introduced into a semiconductor layer 12 to form a P-type high concentration impurity layer 14. Then, SiO2 film 15 is formed on both sides of Si substrate. After that, etching is conducted by the use of an etchant mainly composed of ethylenediamine, of which etching speed changes abruptly between 10<-1>OMEGA-cm and 10<-2>OMEGA-cm in the P-type layer Si. Then, the Si substrate 11 forming a rack using the SiO2 film 15 as a mask is etched surely. In this case, the low concentration P-type part of an Si epitaxial layer 12 almost remains without being etched. Subsequently, when etching is conducted by the use of the etchant, of which etching speed changes abruptly between resistivities of 10<-1>OMEGA-cm and 10<-2>OMEGA-cm, only he high concentration impurity layer 14 is selectively etched along the direction of thickness of the semiconductor layer 12 so that a square opening 17 with high accuracy can be formed in the semiconductor layer 12.

Description

【発明の詳細な説明】 〔概 要〕 多素子型光検知素子のアパーチャ等の半導体の微細装置
の加工方法に関し、 半導体基板を用いて複雑で微細なパターンが容易に加工
できる加工方法を目的とし、 半導体基板に該基板と逆導電型の半導体層を形成し、該
半導体層に所定パターンの高濃度不純物層を形成し、該
基板を不純物濃度の変動、或いは導電型の相違に依存し
てエツチング速度が変化するエツチング液を用いて選択
的にエツチング加工することで構成する。
[Detailed Description of the Invention] [Summary] This invention relates to a method for processing fine semiconductor devices such as apertures of multi-element photodetecting elements, and aims to provide a processing method that can easily process complex and fine patterns using a semiconductor substrate. , forming a semiconductor layer of a conductivity type opposite to that of the substrate on a semiconductor substrate, forming a high concentration impurity layer in a predetermined pattern on the semiconductor layer, and etching the substrate depending on variations in impurity concentration or differences in conductivity type. It is constructed by selectively etching using an etching solution with varying speed.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体微細装置の加工方法、特に多素子型光検
知素子のアパーチャ等の加工方法に関する。
The present invention relates to a method for processing semiconductor microdevices, and particularly to a method for processing apertures, etc. of multi-element type photodetecting elements.

多素子型の光検知装置に於いては、該光検知素子に入射
する光量を規制したり、或いは入射光の視野角を規制す
るために、該検知素子に対向して微細な開口部を有する
アパーチャが用いられている。
In a multi-element type photodetecting device, in order to regulate the amount of light incident on the photodetecting element or to regulate the viewing angle of the incident light, a fine aperture is provided opposite to the detecting element. Aperture is used.

〔従来の技術〕[Conventional technology]

従来、このようなアパーチャをシリコン(Si)のよう
な半導体基板を用いて形成する方法を本出願人は特開平
1−3337号に於いて提案している。
Conventionally, the present applicant has proposed a method of forming such an aperture using a semiconductor substrate such as silicon (Si) in Japanese Patent Laid-Open No. 1-3337.

この方法は例えば第3図(a)に示すようにP型、或い
はN型のSi基板1の表面にイオン注入法等を用いてP
゛層の上面層2を形成後、該基板の両面に二酸化シリコ
ン(SiOz)膜3を形成する。次いで該SiO□膜3
上に^l膜4を形成後、該A2膜4をレジスト膜をマス
クとしてエツチングにより所定のパターンに形成する。
For example, as shown in FIG. 3(a), this method uses ion implantation or the like to inject P into the surface of a P-type or N-type Si substrate 1.
After forming the top layer 2, a silicon dioxide (SiOz) film 3 is formed on both sides of the substrate. Next, the SiO□ film 3
After forming the ^l film 4 thereon, the A2 film 4 is etched into a predetermined pattern using a resist film as a mask.

次いでこのA42114をマスクとしてエツチングによ
りSiO□膜3を所定のパターンにエツチングする。
Next, using this A42114 as a mask, the SiO□ film 3 is etched into a predetermined pattern.

更に第3図(b)に示すように上記A!膜4と5in2
膜3をマスクと′して上面層2を弗化水素酸(HF)、
硝酸(HNO:l)、酢酸(CF13COOH)の混合
液よりなる等方性のエツチングによりエツチングする。
Furthermore, as shown in FIG. 3(b), the above A! Membrane 4 and 5in2
Hydrofluoric acid (HF) is applied to the upper layer 2 using the film 3 as a mask.
Etching is performed by isotropic etching using a mixture of nitric acid (HNO:l) and acetic acid (CF13COOH).

次いでSi基板1の裏面の^!膜4を除去した後、第3
図(C)に示すように基板の裏面側に5i02膜5を形
成する。
Next, the back side of the Si substrate 1! After removing the film 4, the third
As shown in Figure (C), a 5i02 film 5 is formed on the back side of the substrate.

次いで第3図(d)に示すようにP゛層の上面層2はエ
ツチングしないが、P型層のみを選択的にエツチングす
るエツチング液を用いてSi基板lのみを選択的に前記
したSi0g膜をマスクとして異方性エツチングしてア
パーチャの架台6を形成してアパーチャを形成している
Next, as shown in FIG. 3(d), only the Si substrate 1 is selectively etched using an etching solution that does not etch the upper surface layer 2 of the P layer but selectively etch only the P type layer. An aperture is formed by anisotropic etching using the mask as a mask to form an aperture frame 6.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、上記した従来の方法では前記した上面層2を
厚さ方向に沿って前記等方性のエツチング液によりエツ
チングしている。
By the way, in the above-described conventional method, the above-mentioned upper surface layer 2 is etched along the thickness direction using the above-mentioned isotropic etching solution.

然し、このような等方性エツチング液を用いて上面層の
厚さ方向にエツチングすると、エツチングが横方向に拡
がって行われるようになる。そのため、二次元の多素子
型光検知素子のアパーチャのように、ピ・ンチが50μ
蒙〜100 μ■で、−辺が20〜30μmの方形の開
口部を設けようとしても、上記方形のパターンが菱形状
になり、開口部が相互に連なるようになり、高精度の寸
法の開口部を有するアパーチャが形成されない問題があ
る。
However, if such an isotropic etching solution is used to etch the top layer in the thickness direction, the etching will spread laterally. Therefore, like the aperture of a two-dimensional multi-element photodetector, the pinch is 50 μm.
Even if an attempt is made to form a rectangular opening with a negative side of 20 to 30 μm, the rectangular pattern will become diamond-shaped and the openings will be connected to each other, resulting in an opening with highly accurate dimensions. There is a problem that an aperture having a portion is not formed.

本発明は上記した問題点を除去し、アパーチャ形成のた
めの開口部が所定の方形のパターンに高精度に得られる
ようにした半導体微細装置の加工方法の提供を目的とす
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for processing a semiconductor microdevice, which eliminates the above-mentioned problems and allows openings for forming apertures to be formed in a predetermined rectangular pattern with high precision.

〔課題を解決するための手段〕[Means to solve the problem]

上記した目的を達成する本発明の方法は、半導体基板に
該基板と逆導電型の半導体層を形成し、該半導体層に所
定パターンの高濃度不純物層を形成し、該基板を不純物
濃度の変動、或いは導電型の相違に依存してエツチング
速度が変化するエツチング液を用いて選択的にエツチン
グ加工することを特徴とする。
The method of the present invention for achieving the above object includes forming a semiconductor layer of a conductivity type opposite to that of the substrate on a semiconductor substrate, forming a high concentration impurity layer in a predetermined pattern on the semiconductor layer, and changing the impurity concentration of the substrate. Alternatively, it is characterized by selective etching using an etching solution whose etching rate changes depending on the difference in conductivity type.

〔作 用〕[For production]

本発明の方法は半導体基板の表面に該基板と逆導電型の
半導体層を形成し、この半導体層にイオン注入法等によ
り所定のパターンの高濃度不純物層を形成する。そして
この不純物濃度の変動に依存してエツチング速度が変動
するエツチング液を用いて半導体層をエツチングすると
、所定のパターンに高精度な開口部が形成できる。
In the method of the present invention, a semiconductor layer of a conductivity type opposite to that of the substrate is formed on the surface of a semiconductor substrate, and a high concentration impurity layer in a predetermined pattern is formed in this semiconductor layer by ion implantation or the like. When the semiconductor layer is etched using an etching solution whose etching rate varies depending on variations in impurity concentration, highly accurate openings can be formed in a predetermined pattern.

また導電型の相違に依ってエツチング速度が変化するエ
ツチング液を用いて基板を選択エツチングすると、上記
の基板に対して導電型の異なる半導体層はエツチングさ
れないので、架台が容易に形成でき、高精度な寸法の開
口部を有するアパーチャが容易に形成できる。
In addition, if the substrate is selectively etched using an etching solution whose etching speed changes depending on the conductivity type, the semiconductor layer with a different conductivity type will not be etched with respect to the substrate, so the pedestal can be formed easily and with high precision. An aperture having an opening with a certain size can be easily formed.

〔実 施 例] 以下、図面を用いて本発明の一実施例につき詳細に説明
する。
[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図(a)に示すように厚さが数100μmのP型の
Si基板11上に0.1Ω−Gの抵抗率を有するP型の
Stエピタキシャル層よりなる半導体層12を数10μ
mの厚さに形成する。
As shown in FIG. 1(a), a semiconductor layer 12 made of a P-type St epitaxial layer having a resistivity of 0.1 Ω-G is formed on a P-type Si substrate 11 with a thickness of several tens of μm.
Form to a thickness of m.

次いで該基板上に熱酸化法によりSin、膜13を形成
し、この5iO1膜13をレジストパターンをマスクと
した弗化水素酸のエツチングにより所定のパターンにエ
ツチングする。
Next, a Si film 13 is formed on the substrate by thermal oxidation, and the 5iO1 film 13 is etched into a predetermined pattern by hydrofluoric acid etching using the resist pattern as a mask.

次いで第1図(C)、および第1図(C)の1−1 ’
線断面図の第1図℃)に示すように、前記したSiO□
膜をマスクとしてイオン注入法、或いは熱拡散法を用い
て硼素(B)原子よりなる不純物原子を前記半導体層1
2に導入し、抵抗率がio−’Ω−Ω程度のP型の高濃
度不純物層14を形成する。
Next, Fig. 1(C) and 1-1' of Fig. 1(C)
As shown in Figure 1 (°C) of the line cross-sectional view, the SiO
Using the film as a mask, impurity atoms made of boron (B) atoms are added to the semiconductor layer 1 using an ion implantation method or a thermal diffusion method.
2 to form a P-type high concentration impurity layer 14 having a resistivity of about io-'Ω-Ω.

次いで第1図(d)に示すように、該Si基板の両面に
SiO□膜15膜形5し、Si基板11の裏面側の5i
02膜を架台形成用のパターンにエツチングする。
Next, as shown in FIG. 1(d), a SiO□ film 15 is formed on both sides of the Si substrate, and a 5i film is formed on the back side of the Si substrate 11.
The 02 film is etched into a pattern for forming a pedestal.

次いで第2図(b)の曲線22に示すようにP型層のS
tで10−1Ω−1と、10−2Ω−1の間で急激にエ
ツチング速度が変化するエチレンジアミンを主体とする
エツチング液を用いてエツチングする。
Next, as shown by curve 22 in FIG. 2(b), S of the P-type layer is
Etching is carried out using an etching solution containing ethylenediamine as a main ingredient whose etching rate changes rapidly between 10@-1 Ω@-1 and 10@-2 Ω@-1 at t.

すると第1図(e)に示すように、5iOz膜15をマ
スクとして架台となるSi基板11は確実にエツチング
される。この時、Siエピタキシャル層12の低濃度の
P型の部分は、このエツチング液が異方性を有するため
に殆どエツチングされずに残る。
Then, as shown in FIG. 1(e), using the 5iOz film 15 as a mask, the Si substrate 11 serving as the pedestal is reliably etched. At this time, the low concentration P-type portion of the Si epitaxial layer 12 remains almost unetched because the etching solution has anisotropy.

次いで第2図(a)の曲線21に示すように、抵抗率が
10−1Ω−1と10−”Ω−Ωの間で急激にエツチン
グ速度が変化する例えば硝酸、弗化水素酸、酢酸の混合
液より成るエツチング液を用いてエツチングすると、高
濃度不純物層14のみが選択的に半導体層12の厚さ方
向に沿ってエツチングされ、第1図げ)のように半導体
層12に高精度な方形の開口部17が形成できる。
Next, as shown in curve 21 of FIG. 2(a), etching rates such as nitric acid, hydrofluoric acid, and acetic acid, whose resistivity changes rapidly between 10-1 Ω-1 and 10-'' Ω-Ω, are used. When etching is performed using an etching solution consisting of a mixed solution, only the high concentration impurity layer 14 is selectively etched along the thickness direction of the semiconductor layer 12, and as shown in Figure 1), the semiconductor layer 12 is etched with high precision. A rectangular opening 17 can be formed.

以上は多素子型光検知素子のアパーチャの製造に例を用
いて述べたが、半導体の不純物濃度、或いは導電型に対
応してエツチング速度が異なるエツチング液を用いて加
工すれば、半導体基板を用いて複雑な形状を加工するこ
とができ、例えばインクジェットヘッドのノズル、圧カ
ドラスジューサ、或いはガスクロマトグラフィ装置の渦
巻状のカラム等が容易に加工形成できる。
The above has been described using an example of manufacturing an aperture for a multi-element type photodetecting element, but if etching is performed using an etching solution that has different etching speeds depending on the impurity concentration or conductivity type of the semiconductor, it is possible to use a semiconductor substrate. For example, the nozzle of an inkjet head, a pressure fluid juicer, or the spiral column of a gas chromatography device can be easily formed.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば複雑な形
状を有するアパーチャが開口部の寸法を高精度にした状
態で容易に形成でき、本発明の方法で微細加工したアパ
ーチャを用いることで分解能の良い一次元、或いは二次
元の多素子型の光検知素子を形成することができる。
As is clear from the above description, according to the present invention, an aperture having a complicated shape can be easily formed with highly accurate opening dimensions, and by using an aperture microfabricated by the method of the present invention, resolution can be improved. It is possible to form a one-dimensional or two-dimensional multi-element type photodetecting element with good properties.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)より第1図げ)迄は、本発明の方法の工程
を示す断面図および平面図、 第2図(a)および第2図ら)は本発明の方法に用いる
エツチング液の特性図、 第3図(a)より第3図(d)迄は、従来の方法の工程
を示す断面図である。 図において、 11はSi基板、12は半導体層、13.15はSin
、膜、14は高濃度不純物層、16架台、17は開口部
、21 、22はエツチング液の特性曲線を示す。 第1図RfI)2ツ バT7re″′や 第2図
FIGS. 1(a) to 1(g) are cross-sectional views and plan views showing the steps of the method of the present invention, and FIGS. Characteristic diagrams FIG. 3(a) to FIG. 3(d) are cross-sectional views showing the steps of the conventional method. In the figure, 11 is a Si substrate, 12 is a semiconductor layer, and 13.15 is a Si substrate.
, a film, 14 a high concentration impurity layer, 16 a pedestal, 17 an opening, and 21 and 22 a characteristic curve of an etching solution. Figure 1 RfI) 2 brim T7re''' and Figure 2

Claims (1)

【特許請求の範囲】[Claims]  半導体基板(11)に該基板と逆導電型の半導体層(
12)を形成し、該半導体層(12)に所定パターンの
高濃度不純物層(14)を形成し、該半導体基板(11
)を不純物濃度の変動、或いは導電型の相違に依存して
エッチング速度が変化するエッチング液を用いて選択的
にエッチング加工することを特徴とする半導体微細装置
の加工方法。
A semiconductor substrate (11) is provided with a semiconductor layer (
12), a high concentration impurity layer (14) of a predetermined pattern is formed on the semiconductor layer (12), and a highly concentrated impurity layer (14) is formed on the semiconductor layer (12).
) is selectively etched using an etching solution whose etching rate changes depending on changes in impurity concentration or differences in conductivity type.
JP19834590A 1990-07-25 1990-07-25 Processing of semiconductor minute device Pending JPH0483341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19834590A JPH0483341A (en) 1990-07-25 1990-07-25 Processing of semiconductor minute device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19834590A JPH0483341A (en) 1990-07-25 1990-07-25 Processing of semiconductor minute device

Publications (1)

Publication Number Publication Date
JPH0483341A true JPH0483341A (en) 1992-03-17

Family

ID=16389580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19834590A Pending JPH0483341A (en) 1990-07-25 1990-07-25 Processing of semiconductor minute device

Country Status (1)

Country Link
JP (1) JPH0483341A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677407A (en) * 1992-04-06 1994-03-18 Nippon Precision Circuits Kk Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677407A (en) * 1992-04-06 1994-03-18 Nippon Precision Circuits Kk Semiconductor device

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