JPH0484228A - debug equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging device that enables debugging of a program to be debugged, and furthermore, to a technology for enhancing a trap function for detecting abnormal operations, such as in-circuit - Concerning techniques that are effective when applied to emulators.

[Conventional technology]

In the development of microcomputer application equipment, in-circuit emulators are used to debug the application system and perform detailed evaluation of the system. Such an in-circuit emulator is connected between a system development device such as a parent computer (host computer) for software development and an application device under development, and is used to control the microprocessor (target microprocessor) included in the application device. While acting as a debugger, it supports detailed system debugging. Such in-circuit emulators are equipped with various trap functions (abnormal processing detection function of the target microprocessor) in addition to a break function that enables evaluation of the hardware and software on the application equipment side. There is. A typical example of this function is an address trap detection function that detects an address error in the target microprocessor and breaks the program.

An example of a document describing in-circuit emulators is "Hitachi Microcomputer Technical Report (Volume 2, No. 2)" published by Hitachi Microcomputer Engineering Co., Ltd. on October 1, 1986. .

[Problem to be solved by the invention]

However, even if the system operates normally during system debugging using the trap function, it may not operate normally when an application system is operated using an actual chip. According to the inventor's study on this, the operating margin is different between the emulation chip installed in the emulator and the actual chip actually installed in the application system, and even if there is a timing failure in the actual chip, It was discovered that the problem mentioned above is caused by the fact that the emulation chip operates normally. The inventor has revealed that such timing failures cannot be detected by conventional trap functions such as the address trap function, which inevitably lowers the reliability of system debugging.

An object of the present invention is to provide a technique that can improve the reliability of system debugging by strengthening the trap function in system debugging.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description herein and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the debug device includes a timing defect detection means for detecting a timing defect in a signal exchanged between a processor executing a debug target program and a debug target device. The timing failure detection means includes a first comparator that determines whether there is a setup time failure in the signal input to the processor, and a second comparator that determines whether there is a hold time failure in the signal. be able to.

1st. In order to facilitate the determination by the second comparator, a latch circuit that holds a signal exchanged between the processor and the device to be debugged at a predetermined timing synchronized with the system clock, and a latch circuit that holds the signal exchanged between the processor and the debug target device at a predetermined timing synchronized with the system clock, and It is preferable to provide a delay circuit that delays the time. At this time, by comparing the held value of the latch circuit with the delayed output of the delay circuit using the first comparator, it is possible to determine whether or not there is a set-up time failure. The presence or absence of a hold time failure can be determined by comparing the signal exchanged with the held value of the latch circuit using a second comparator.

Further, the signal delay time in the delay circuit can be configured to be changed, and the delay circuit can be configured to break based on the timing failure detection result.

[For production]

According to the above-described means, a timing failure in a signal exchanged between a processor and a device to be debugged can be detected by the timing failure detection means.
This function allows the presence or absence of timing specification errors to be detected at the debugging stage, thereby improving the reliability of system debugging.

〔Example〕

FIG. 2 shows a microcomputer development system including an in-circuit emulator, which is an embodiment of the present invention.

The in-circuit emulator 2 shown in the figure is connected between a system development device 1 such as a parent computer and a microprocessor application device 3 as a device to be debugged, and is connected to a target microprocessor included in the application device 3. While acting as a debugger, it supports detailed system debugging. The system development device 1 and the in-circuit emulator 2 are connected by a serial path line, and this path line allows data to be exchanged between the two. In addition, a cable 4 is pulled out from the in-circuit emulator 2, and a plug 4a provided at the tip of the cable 4 is connected to the target microprocessor socket S of the application device 3, so that the in-circuit emulator
Predetermined emulation operations are enabled in the emulator 2.

FIG. 3 shows a detailed configuration of the in-circuit emulator 2. As shown in FIG.

In-circuit emulator 2 as shown in the figure
1 includes a slave microprocessor (hereinafter referred to as SMCU) 1 for controlling the operation of the target microprocessor included in the microprocessor application device 3 and performing emulation.
1 and a microprocessor (hereinafter referred to as MMCU) 16 that controls control for achieving various debugging functions.

When the SMCUI 1 performs proxy control (emulation) of the functions of the target microprocessor in the application device 3, the SMCUII is separated from the control of the MMCUI 6, and is broken when the control operation state of the SMCUII reaches a predetermined state. Time, MMCU16
will be subject to control. Such switching of control states is performed by the emulation control section 12.

In addition to the emulation control section 12, the in-circuit emulator 2 also monitors the control state of the SMCUI 1 and the state of the slave bus 21, and stops the emulation operation when the state reaches a preset state. a real-time trace unit 14 that sequentially traces and stores data and addresses given to the slave bus 21 as well as control information, and a substitute memory unit that acts on behalf of data memory and programs to be included in the application device 3. 15. It has an abnormal processing detection section 50 that detects abnormal operation of the SMCU II, such as an address error or a timing specification error, and is connected to the SMCU II via a slave bus 21 and to the MMCU 16 via a master bus 22. The execution of the functions of each of the blocks described above is controlled by the console 10 of the parent computer connected to the in-circuit emulator 2.

Furthermore, the in-circuit emulator 2 includes an MMCU
16 is provided with a serial interface circuit 17 for data communication with the console 10, and
A cable 4 is led out from the SMCUII via an interface circuit 18.

FIG. 1 shows means for realizing the function of timing failure detection in the abnormality processing detection section 50. Note that, as in the past, various trap detection functions typified by the address trap detection function are also included in this abnormality processing detection section 50, but their implementation means are omitted in FIG. Further, in FIG. 1, signals with umbrellas indicate low active signals.

The slave bus 21 includes, but is not particularly limited to, a slave control bus 31, a slave data bus 32, and a slave address 33, and the master bus 42 includes a mask address bus 41, a master data bus 42, and a mask control bus 43.

The abnormal processing detection section 50 includes, but is not particularly limited to, an abnormal processing control section 23, multiplexers (MPX) 51, 52, delay circuits (DL) 5, 3, 54, and latch circuits (LAT).
) 55, comparators (CMP) 56, 57, and logic gates such as Nant gates 60, 61 and inverters 62 that enable the comparators 56, 57 to operate.

During the emulation operation period, the abnormality processing control unit 23
In response to instructions from the emulation control section 12, the hold error detection mode signal HON and the set-up error detection mode signal SON are selectively asserted to high level. The abnormality processing control section 23 also has a function of outputting a select signal Si,52 for selectively setting a delay corresponding to a hold value and a set-up value of a signal subject to error detection.

The decoder 58 has a function of decoding a signal input from the MMCU 16 via the master data bus 42 when the select signal S1* from the abnormality processing control section 23 is asserted. This decoded output is transmitted to the subsequent multiplexer 51, and the multiplexer 51 adjusts the delay value (
delay time).

Similarly, the decoder 59 receives the select signal S? from the abnormality processing control section 23. It has a function of decoding a signal inputted from the MMCU 16 via the master data bus 42 when the MMCU 16 is asserted. This decoded output is transmitted to the subsequent stage multiplexer 52, and the multiplexer 52 selects the delay value (delay time) of the delay circuit 54 based on this decoded output.

That is, in this embodiment, the delay values of the delay circuits 53 and 54 can be changed and set by the MMCU 16.

The delay circuit 53 delays the input target reference clock (also referred to as system clock) signal SE.
It has a function of delaying and outputting by a delay time (hold time) selected by the multiplexer 51.

The delay circuit 54 receives the input target reference clock signal SE and a signal subject to abnormality detection (in this embodiment, a signal carried on the slave data bus 31, which is a signal carried on the slave data bus 31, which is a signal carried by the SMCUII and the application device 3 which is the device to be debugged). (refer to FIG. 2)) is delayed by a delay time (setup time) selected by the decoder 59 and output.

The latch circuit 53 holds the signal state on the slave data bus 31 during the setup and hold period according to the timing of the target reference clock signal SE. This held value is sent to the subsequent comparators 56 and 57 as reference data (DOR
G signal).

The comparator 56 outputs the output signal CM of the Nant gate 60.
When the IE rate is asserted to a low level, the signal on the slave data bus 32 and the latch circuit 5
5 (reference data DORG signal).

In other words, the selection signal H output from the abnormality processing control section 23
When ON is at a high level, a signal state comparison is performed with respect to the reference clock signal SE by the delay time in the delay circuit 53, and if there is a mismatch in this comparison, a hold error signal HOLDERR* is asserted to a low level.

The comparator 57 outputs the output signal CM of the Nant gate 61.
When 2E* is asserted to low level, the value held by the latch circuit 55 (reference data DORG signal)
It has a function of comparing the delay output of the delay circuit 54 and the delay output of the delay circuit 54. That is, when the selection signal SON output from the abnormality processing control section 23 is at a high level, the reference clock signal S
Signal comparison is performed for E by the delay time set in the delay circuit 54. If there is a mismatch in this comparison, the set-up error signal SETEERR is output.
Monkey is asserted to low level.

Next, the operation of the above configuration will be explained.

When starting the emulation operation, delay circuits 53 and 54 are initialized. This initial setting is performed via the abnormality processing control section 23 under the control of the MMCU 16. That is, by asserting the select signal S1*, a delay value corresponding to the hold value is set in the delay circuit 53, and the select signal S?
By asserting , a delay value corresponding to the set-up value is set in the delay circuit 54 .

Also, at this time, a selection signal (HON, 5ON) indicating the timing failure detection mode is asserted. When the emulation control unit 12 asserts the emulation control unit signal EMLON indicating the emulation mode to a high level, the selection signal HON
, SON, the corresponding comparators 56 and 57 are placed in detection mode.

Hold error detection is performed as follows.

That is, if the timing from the reference clock signal SE to the change in input data is short with respect to the delay value of the delay circuit 53, the input change will occur during the active period of the comparator 56, and the hold error signal HOL DE
RR* is asserted to low level. This makes it possible to detect hold time failures.

On the other hand, in the case of a setup error, the delay circuit 54
Data DLDATA delayed by the delay value of
and data D latched by the reference clock signal SE.
ORG is compared by the comparator 57 for the set-up time from the reference clock signal SE. For example, if the input data has not been determined before the set-up time from the reference clock signal SE, the comparator 57 compares the input data immediately after the start of the comparison. It is determined that they do not match, and the set-up error signal 5ETEERR* is asserted to low level. This makes it possible to detect setup time failures.

The trap signals such as the error signal HOLDERR and 5ETEERR* are sent to the emulation control unit 12 and
The information is transmitted to the break control unit 13 and used for break processing of the target program, and for displaying traps on the console 10 of the parent computer.

According to the above embodiment, the following effects can be obtained.

(1) Assuming that the hold timing spec is Ans (nanosec) and the hold time of the actual input data is A-αns from the reference clock signal SE (αns
To explain the case of insufficient hold), the delay value of the delay circuit 53 is set to A n s by default, and the data input during target program operation is transferred to the latch LAT on the DORGOR at the falling timing of the reference clock signal SE. The output signal CMIE of the Nant gate 60 is delayed by Ans by the inverted signal SE umbrella and the delay circuit 53 and the output signal CMIE of the Nant gate 60 is held every cycle and input to the Nant gate 60. It becomes low level during Ans from the falling edge of , during which time comparator 5
6, the input data and the latch data DORG signal are compared, so that the reference clock signal SE to A
After −αns, there is a mismatch, and the output signal HOLDERR* of the comparator 56 becomes low level. By checking the hold error signal HOLDERR or performing break processing or the like based on the hold error signal HOLDERR, it is possible to grasp a hold time failure caused by a design error or the like.

In addition, the setup timing spec is set to BnS,
Taking as an example a case where the actual input data set-up time is -(B-β)ns from the reference clock signal SE (βns shortage), Bns is set in the delay circuit 54 by default, and the target program Input data during operation is applied to the latch 55 by DORGOR at the falling edge of the reference clock signal SE and is held every cycle. The output DLDATA of the input data delayed by the delay 54 always continues to output the state before Bns with respect to the reference clock signal SE. In contrast, the reference clock signal S input to the Nantes gate 61
The output signal C3E2 of the Nant gate 61 is the reference clock signal SE by the signal obtained by inverting E by the inverter 62 and C5E2 delayed by Bns by the delay 54.
It becomes low level from the falling edge of Bns to Bns,
During that time, the comparator 57 outputs the latch data DOR.
Since the comparison between G and the delay data DLDATA is performed, βns
As a result, the set-up error signal 5ETERRI, which is the output of the comparator 57, is asserted to a low level. By checking the set-up error signal 5ETERRI or by performing break processing based on the set-up error signal HOLDERR, it is possible to grasp a set-up time failure caused by a design error or the like.

(2) The reliability of system debugging can be improved by the effect of (1) above.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various changes can be made without departing from the gist of the present invention.

In the above embodiment, the detection of a pair of set-up time and hold time shortages for the slave data bus 31 was explained as an example, but the target input signal may be a signal other than the data bus. For example, external interrupt input signal (N
A timing failure detection circuit for MI, IRQ, RESET signals, etc.) may be provided. In addition, in the above embodiment, there was one set value for one specification, but by providing multiple detection circuits with different detection standards or connecting multiple delay circuits with different delay values in parallel, More detailed timing verification becomes possible.

Further, the delay setting value does not necessarily have to be equal to the specifications, and can be made to correspond to the timing version (the version with the highest operating frequency) of the target microprocessor by changing it appropriately.

Furthermore, in the above embodiment, the system clock (reference clock signal SE) is taken into the latch circuit 55, delay circuit 53, 54, etc., but the period generated by appropriately delaying or frequency dividing the block concerned is The signal may be transmitted to the latch circuit 55, delay circuits 53, 54, etc.

In the above explanation, the present invention was mainly applied to an in-circuit emulator, which is the background field of application, but the present invention is not limited to this, and the present invention is not limited to this. It can be applied to tools and other data processing systems having emulation functions. The present invention can be applied to conditions that are coupled to or include at least a processor that executes a program to be debugged.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, since the timing defect detection means detects a timing defect in a signal exchanged between the processor executing the debug target program and the debug target device, the presence or absence of a timing specification error can be detected at the debugging stage. It is possible to improve the reliability of system debugging.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of an emulator that is an embodiment of the present invention, and FIG. 2 is a block diagram of a microcomputer development system including the emulator. FIG. 3 is a block diagram showing the overall configuration of the emulator. 1...System development equipment, 2...In-circuit・
Emulator, 3... Application equipment, 4... Cable,
4a...Plug, 5...Socket, 10...Console, 11...SMCU, 12...Emulation control unit. 13... Break control section, 14... Trace memory section, 15-03 proxy memory section, 16. MMCU, 17-
9 real interface, 18... interface,
19...Probe, 21...Slave bus, 22.
... Master bus, 23 ... Abnormality processing control section, 31 ...
Slave data bus, 32... Slave address bus, 33... Slave control bus, 41... Master address bus, 42... Master data bus, 43
...Master control bus, 50...Abnormal processing detection section, 51.52...Multiplexer, 53.54...
Delay circuit, 55...Latch circuit, 56.57...
Comparator, 58, 59...decoder, 60, 61
...Nant Gate, 62...Inverter.

Claims (1)

[Scope of Claims] 1. In a debugging device that enables system debugging of a device to be debugged based on the operating state of a processor of a program to be debugged, a timing error in a signal exchanged between the processor and the device to be debugged is detected. A debugging device characterized in that it includes timing failure detection means. 2. The timing failure detection means includes a first comparator that determines whether there is a setup time failure in the signal input to the processor, and a second comparator that determines whether there is a hold time failure in the signal. The debugging device according to claim 1. 3. The timing failure detection means includes a latch circuit that holds the signal input to the processor at a predetermined timing synchronized with the system clock, and a delay circuit that delays the signal for a predetermined time, and The comparator determines whether there is a setup time failure by comparing the held value of the latch circuit with the delayed output of the delay circuit, and the second comparator compares the held value of the latch circuit with the delayed output of the delay circuit. and a value held by the latch circuit to determine whether or not there is a hold time failure.
Debug equipment as described. 4. The debugging device according to claim 3, wherein the signal delay time in the delay circuit can be changed. 5. The debugging device according to claim 1, 2, 3 or 4, further comprising a break control circuit that breaks based on the detection result of the timing detection means.