JPH048524U - - Google Patents

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Publication number
JPH048524U
JPH048524U JP4764290U JP4764290U JPH048524U JP H048524 U JPH048524 U JP H048524U JP 4764290 U JP4764290 U JP 4764290U JP 4764290 U JP4764290 U JP 4764290U JP H048524 U JPH048524 U JP H048524U
Authority
JP
Japan
Prior art keywords
impedance
fet
buffer
source
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4764290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4764290U priority Critical patent/JPH048524U/ja
Publication of JPH048524U publication Critical patent/JPH048524U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る高入力インピーダンス・
バツフアの原理構成図、第2図は本考案の具体例
を示す構成図、第3図は第2図に示す回路の等価
回路、第4図は従来の高入力インピーダンス・バ
ツフアの一例を示す図、第5図は第4図をモデル
化した回路、第6図は第5図の等価回路である。 Q……FET、YC……補償アドミツタンス、
CB……電流バツフア、CS……直流電流源、Z
L……負荷。
Figure 1 shows the high input impedance system according to the present invention.
Figure 2 is a configuration diagram showing a specific example of the present invention, Figure 3 is an equivalent circuit of the circuit shown in Figure 2, and Figure 4 is a diagram showing an example of a conventional high input impedance buffer. , FIG. 5 is a circuit modeled after FIG. 4, and FIG. 6 is an equivalent circuit of FIG. Q...FET, YC...compensation admittance,
CB...Current buffer, CS...DC current source, Z
L...Load.

Claims (1)

【実用新案登録請求の範囲】 FETソース・フオロア型のバツフアであつて
、負荷インピーダンスの逆数に等しい補償アドミ
ツタンスと、 入力インピーダンスが極めて小さく出力インピ
ーダンスが無限大であり、かつ電流ゲインが1の
電流バツフア を備え、この補償アドミツタンスと電流バツフア
を直列接続して前記FETのゲート・ソース間に
接続し、負性入力インピーダンスを自動的に相殺
することができるように構成したことを特徴とす
る高入力インピーダンス・バツフア。
[Scope of Claim for Utility Model Registration] A current buffer that is a FET source-follower type buffer and has a compensation admittance equal to the reciprocal of the load impedance, an input impedance that is extremely small, an output impedance that is infinite, and a current gain of 1. The compensation admittance and the current buffer are connected in series between the gate and source of the FET, and the negative input impedance is automatically canceled out.・Batsuhua.
JP4764290U 1990-05-09 1990-05-09 Pending JPH048524U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4764290U JPH048524U (en) 1990-05-09 1990-05-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4764290U JPH048524U (en) 1990-05-09 1990-05-09

Publications (1)

Publication Number Publication Date
JPH048524U true JPH048524U (en) 1992-01-27

Family

ID=31563752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4764290U Pending JPH048524U (en) 1990-05-09 1990-05-09

Country Status (1)

Country Link
JP (1) JPH048524U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004503160A (en) * 2000-07-07 2004-01-29 テレフオンアクチーボラゲツト エル エム エリクソン Transmitter with composite amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004503160A (en) * 2000-07-07 2004-01-29 テレフオンアクチーボラゲツト エル エム エリクソン Transmitter with composite amplifier

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