JPH0485380U - - Google Patents
Info
- Publication number
- JPH0485380U JPH0485380U JP12672690U JP12672690U JPH0485380U JP H0485380 U JPH0485380 U JP H0485380U JP 12672690 U JP12672690 U JP 12672690U JP 12672690 U JP12672690 U JP 12672690U JP H0485380 U JPH0485380 U JP H0485380U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- output
- signal
- data
- driven
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009466 transformation Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Image Processing (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
第１図は、本考案によるデータ直交変換回路の
一実施例を示すデータ直交変換回路の構成図、第
２図は第１図に示す実施例回路の動作タイミング
チヤート、第３図は第１図に示す実施例による直
交変換前後のデータ例を示す図、第４図は第１図
に示す実施例により画面上の画像を９０°回転さ
せたときの画像例を示す図である。
１，０〜１，７，４，０，４，７……ＯＲゲー
ト、２，０〜２，７……シフトレジスタ、３０，
０〜３０，７，３１，０〜３１，７，……３７，
０〜３７，７……ゲート回路。
FIG. 1 is a block diagram of a data orthogonal transformation circuit showing an embodiment of the data orthogonal transformation circuit according to the present invention, FIG. 2 is an operation timing chart of the embodiment circuit shown in FIG. FIG. 4 is a diagram showing an example of data before and after orthogonal transformation according to the embodiment shown in FIG. 1,0~1,7,4,0,4,7...OR gate, 2,0~2,7...shift register, 30 ,
0 ~ 30,7,31,0 ~ 31,7 ,... 37 ,
0 to 3 7 , 7... gate circuit.
Claims (1)
され、セレクタ信号とライト信号のＯＲゲート出
力で駆動動作され、Ｎ個の出力端子を有するＮ個
のシフトレジスタと、 前記Ｎ個のシフトレジスタの各シフトレジスタ
の各出力端子に接続され、対応するリード信号と
前記セレクタ信号のＯＲゲート出力でゲート制御
され、直交変換データを出力するゲート回路と、
を備えて成ることを特徴とするデータ直交変換回
路。[Claims for Utility Model Registration] N time-series data are input to N input terminals, driven by an OR gate output of a selector signal and a write signal, and N shift units having N output terminals are driven. a gate circuit connected to each output terminal of each of the N shift registers, gate-controlled by an OR gate output of a corresponding read signal and the selector signal, and outputting orthogonal transformed data;
A data orthogonal transformation circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12672690U JPH0485380U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12672690U JPH0485380U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0485380U true JPH0485380U (en) | 1992-07-24 |
Family
ID=31874267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12672690U Pending JPH0485380U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0485380U (en) |
-
1990
- 1990-11-30 JP JP12672690U patent/JPH0485380U/ja active Pending
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