JPH0485933A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit device technology, and particularly to wiring technology for semiconductor integrated circuit devices.

[Conventional technology]

Regarding wiring technology for semiconductor integrated circuit devices, for example, Te
chnical Diges! of IEDM
le+nal 1onaElectron Device
es Meeting) 1983. PP, 542-5
It is described in 45.

A conventional wiring structure is shown in FIG. In FIG. 1, a chain line extending in the vertical direction is a center line CL indicating the channel direction of the wiring 1. In FIG. Center lines CL extending parallel to each other
, , CL, indicates the channel spacing. In addition, the dashed line extending in the direction perpendicular to the center line CL is
A center line CL2 indicates the channel direction of the upper layer wiring (not shown) of the wiring 1. At the intersection of the center line CL and the center line CL2, a through-hole portion 2 for connecting the wiring 1 and the upper layer wiring is arranged. Wiring], the through-hole portion 2 is formed with a dogbone portion 1a. In order to prevent misalignment of the through-hole portion 2 due to mask misalignment, the dockbone portion 1a is wider than the other wiring portion 1b of the wiring 1, and is formed in a roughly square shape.

To design such a wiring structure, first, the minimum interval between the adjacent wirings 1.1 and the minimum line width of the wiring 1 are determined. Since the dock bone portion 1a is wider than the other wiring portions 1b, the minimum interval is determined by the distance d between the dog bone portion 1a and the adjacent wiring portion 1b.

Further, the minimum line width is determined by the width d2 of the wiring portion 1b sandwiched between the dogbone portions 1a and la.

Conventionally, when setting the line width of the wiring, the width d of only the wiring portion lb sandwiched between the dock bone portions 1a and la was determined.
2 is not set to the minimum line width, but for ease of layout and efficiency of layout, the wiring portion 1b of the wiring 1 that is not sandwiched by the dock bone portions 1a and la is also set to the minimum line width.

As a semiconductor integrated circuit device having such a wiring structure, a semiconductor integrated circuit device employing a gate array method is known. A semiconductor integrated circuit device employing this gate array method uses multiple layers of wiring to connect basic cells (basic cells) regularly arranged in a matrix and between basic cells. Semiconductor integrated circuit devices that use this type of mask slicing method can configure various logic circuits simply by changing the wiring pattern, so they have the characteristic of being able to develop a wide variety of products in a short period of time. be.

Connections to semiconductor integrated circuit devices that use the gate array method are made using a computer-based automatic placement system (DA).
:Design Automation).

Regarding semiconductor integrated circuit devices that adopt this type of gate array method, for example, 15SCCDIGEST
TECHNICAL PAPER5, P, 72-
73:Fe6. ．． 1988.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, in which the wiring portions not sandwiched by the dogbone portion are set to the minimum line width for ease of layout, the width of the wiring portion not sandwiched by the dogbone portion is narrower than necessary, and the wiring The inventors have discovered that there is a problem in which the reliability of the system is significantly reduced.

That is, the reliability of the wiring is determined by the formula: [occurrence rate of repeated fine interconnects with disconnections x appearance rate of base level differences].

In conventional wiring structures, as the channel spacing becomes narrower and the minimum line width becomes finer based on the narrower channel spacing, the appearance rate of fine wiring in the entire semiconductor integrated circuit device and the probability that fine wiring is located above the underlying stepped portion increase. Therefore, problems such as electromigration (hereinafter referred to as EM) defects, stress migration (hereinafter referred to as SM) defects, or increased wiring resistance are likely to occur.

In addition, especially in semiconductor integrated circuit devices that adopt the gate array method, due to the increase in the number of gates due to high integration,
There is a tendency for wiring spacing and wiring width to become finer. Along with this, when forming a connection pattern using an automatic placement and routing system using the above-mentioned conventional technology, the degree of freedom in connection is reduced due to requirements for wiring resistance and wiring delay, and the implementation efficiency of logic circuits is reduced. Problems are likely to occur.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technique capable of improving the reliability of wiring formed in a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can improve the reliability of wiring formed in a semiconductor integrated circuit device without impairing the ease of wiring layout.

Another object of the present invention is to provide a technique that can improve circuit mounting efficiency without impairing the ease of wiring layout.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a semiconductor integrated circuit device having laminated wiring,
A wiring having a dock bone portion in a connection hole portion that connects different wiring layers is configured with a wiring structure in which corners of the dog bone portion are chamfered.

In addition, in the wiring adjacent to each other formed on the same wiring layer, the wiring part adjacent to the dog bone part is recessed in the direction away from the tonk horn part, so that only the width of that wiring part becomes the width of the other part of the wiring. Construct thinner than that.

(2) When manufacturing the semiconductor integrated circuit device described in (1) above using an automatic wiring placement system, the automatic wiring layout design stage is such that only the wiring portion adjacent to the dockbone portion is moved in the direction away from the dogbone portion. The method includes the step of arranging a connecting hole element cell having information for recessing in the connecting hole.

[Effect]

According to the above-mentioned means (L), the appearance rate of fine wiring and fine wiring are higher than that of the conventional wiring structure in which the width of all wiring parts except the dockbone part is set to the minimum line width. Since it is possible to significantly lower the probability that the wiring will be located at , for example, it is possible to improve the wiring OEM resistance and SMt properties, and also to reduce the wiring resistance, thereby improving the reliability of the wiring.

In addition, it is possible to prevent poor resolution during the exposure and development process that occurs due to the shortening of the distance between the corner of the dock horn section and the corner of the wiring section or dock bone section that diagonally opposes it. Therefore, the reliability of wiring can be improved, and the interval between the dogbone parts can be reduced, so that the wiring interval can be shortened and the circuit mounting efficiency can be improved.

According to the above-mentioned means (2), when manufacturing the semiconductor integrated circuit device according to the means (1), at the stage of automatic wiring layout design, for example, only the wiring portions sandwiched between the dog bone parts have the minimum line width. Since the wiring pattern can be designed to have the same width, it is possible to improve the reliability of the wiring and the mounting efficiency of the circuit without impairing the ease of wiring layout.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device that employs a gate array method.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Embodiment 1) FIG. 2 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, and the semiconductor integrated circuit device 10 is a composite gate array having a multilayer wiring structure.

A plurality of logic circuit blocks 13 are arranged in a logic circuit formation region 12a at the center of a semiconductor chip (semiconductor substrate) 12 made of, for example, single crystal silicon. The logic circuit block 13 is made of Bi-CMO3 (Bipolar-Complement) from the viewpoint of increasing signal speed and reducing power consumption.
(tary MOS) circuit.

On both sides of the logic circuit forming area 12a, memory circuit blocks 14 are arranged, for example, in two columns and four stages. For example, a static RAM is formed in each memory circuit block 14. Around each memory circuit block 14, an X decoder circuit 15a and a Y decoder circuit 15 are provided.
Peripheral circuit blocks such as b are arranged.

Further, in the semiconductor chip 12, a plurality of input/output circuit blocks 16 are arranged on both left and right ends in the figure. The input/output circuit block 16, like the logic circuit block 13,
For example, it is composed of five Bi-CMO circuits. In the logic circuit forming area 12a, hex cells (not shown) are formed in a matrix. The inverter circuit, NA
Logic elements such as an ND circuit, a NOR circuit, and a flip-flop circuit are configured, and a logic circuit is configured by connecting the logic elements.

Further, this logic element is registered as a macro cell, and information such as an l\-thick cell interconnection pattern, a delay parameter, a symbol diagram, etc. is registered for each macro cell in an automatic placement and wiring system to be described later.

In this way, the logic circuit block 13 is made up of Hesinox cells made of BICMO3. Bi-C
For a Hage Soxel configured with MO3, for example, l5SCCDTGEST OF TECHNIC
AL PAPER3゜P, 116-117. Fe6.
．． 1989.

In the semiconductor integrated circuit device 10 of this embodiment, the wiring constituting the circuit block arranged on the semiconductor chip 12 has a structure shown in FIGS. 3A and 3B, for example.

The one-dot chain line extending in the vertical direction (for example, the X direction) in FIGS. 3A and 3B is the center line CL indicating the channel direction of the wiring 17 formed in the first wiring layer.

Furthermore, a dashed dotted line extending in a direction (for example, the Y direction) perpendicular to the direction in which the center line CL extends indicates the center line CL, which indicates the channel direction of the wiring 19 formed in the second wiring layer.
It is 2.

Note that FIG. 3B shows only the first wiring layer in FIG. 3A. Further, the second wiring layer is formed on the first wiring layer via an interlayer insulating film (not shown), and the wirings in each layer are connected through through holes 18.

As shown in FIG. 3B, in the wiring 17, a dock bone portion 1 for preventing misalignment is provided in a portion where a through hole (connection hole portion) 18 connecting different layer wiring is arranged.
7a is formed, and the interconnects 1 adjacent to each other
7. In 17, the dockbone part 17 of the wiring 17 on the other side
A part of the other wiring 17 adjacent to a is connected to the dockbone part 1
It is recessed in the direction away from 7a, and only the radius d of 17b (the part sandwiched between the dock bone parts 17a of the adjacent wirings on both sides) from that wiring part is the width of the other wiring part 17c of the wiring 17. It is thinner than d2.

In other words, conventionally, the width d of the wiring portion 17b having the minimum line width
The width d2 of the wiring portion 17c, which had been made thinner than necessary in accordance with the wiring pattern 1, is now wider than the wiring portion 17b having the minimum line width. However, in this case, the width d2 of the wiring portion 1.7c is defined such that the distance d4 between the adjacent wiring portions 17c, 17c falls within the following range. That is, [distance d3 between dock bone portion 17a and wiring portion 17b]≦
[Distance d4 between wiring portions 17c and 17c] < (distance d5 between wiring portions 17c and 17b).

In this way, in the wiring 17 of this embodiment, the wiring portion 17b with the minimum line width is only a small part of the entire wiring 17, so all portions of the wiring 17 except the dog bone portion 17a are set to have the minimum line width. The appearance rate of the wiring portion 17b with the minimum line width and the probability that the wiring portion 17b with the minimum line width is located above the base level difference portion are significantly lower than in the case of the wiring structure set to . Therefore, the wiring 17 is, for example, an EM
The structure suppresses defects, SM defects, and increases in wiring resistance.

As shown in FIG. 3A, in this embodiment, the wiring 19 also has the same wiring structure as the wiring 17, and the channel opening distance of one wiring in the second wiring layer is different from that in the first wiring layer. It is configured to be equal to the channel spacing of the wiring 17.

The width d of the wiring portion 17b is, for example, about 16 to 18 μm. The width d2 of the wiring portions 17c and 19c is, for example, 2.
．． It is about 5 to 2.7 μm. In addition, the dock bone part 1
7a, 19a and adjacent wiring portions 17b, 19d
The distance d3 between the adjacent wirings 17, 17;
, 19, and is, for example, about 1.0 to 1.1 μm. Note that the wirings 17 and 19 are made of, for example, an aluminum (AQ)-5i-copper (Cu) alloy.

The above-mentioned through hole 18 is formed between the first wiring layer and the second wiring layer, for example.
This is a part that connects the wiring layer, and is arranged at the intersection of the center line CL and the center line CL2.

In the through hole 18, the width d6 in the direction perpendicular to the center line CLI is, for example, about 1.2 μm.

In addition, the dog bone portion 17a (in this case, the margin width d7 for preventing misalignment is, for example, about 0.6 to 09 μm).

Note that the through hole 18 may be made larger by reducing the margin width d7 for preventing misalignment.

The distance between the center lines CL, CL2 that extend parallel to each other is
It shows the channel spacing of the wiring 17 in the first wiring layer,
For example, it is about 30 μm. The channel spacing is determined, for example, by the following equation.

D=d6/2+d7+d3+d,/2 As shown in FIG. 3B, the corner 2 of the dock bone portion 17a
0 is chamfered. In other words, the dock bone part 17
A has a roughly square shape with chamfered corners.

A corner 22 of the wiring portion 17c diagonally opposite to the chamfered corner 20 is also chamfered.

This means that if the corner 2o of the dockbone section 17a and the corner 22 of the wiring section 17c that is in the same layer and opposite thereto,
If left as is without chamfering, the distance between the corners 20 and 22 will be narrower than the minimum distance d3, which will likely cause poor resolution during the exposure and development process, so this is prevented. It's for a reason. This will be explained in more detail using FIG. 3C. FIG. 3C mainly shows wirings 19A, B, and C of the second wiring layer. Wiring 19A, B, C
, D, the dotted line 20a indicates the position of the corner of the dogbone portion 19a when the corner of the dogbone portion 19a is left as is without chamfering. Further, a point 22a indicates the position of a corner when the corner of the wiring portion 19c diagonally opposite to the corner 20 of the dockbone portion 19a is left as it is without being chamfered. The two-dot chain line indicates the wiring 17A of the first wiring layer.

If the corner 20 of the dockbone section 19a and the corner 22 of the wiring section 19c on the same layer and facing each other are left as they are without chamfering, the distance between the corners 20a (112, Since each of the distances d14 between the corners 20a and the corners 20a are narrower than the minimum distance d3, poor resolution is likely to occur during exposure and development processes, reducing the reliability of wiring. When the distance d12 from the corner 20a is set to the same length as the distance d3 or longer, it is necessary to increase the channel distance between the wires 19 in the second wiring layer or the channel distance between the wires 17 in the first wiring layer. Therefore, the number of wiring lines decreases, and the mounting efficiency of the logic circuit decreases.

Also, the length Q of the portion of the wiring 19c adjacent to the dogbone portion 19a of the wiring 19B that is recessed in the direction away from the dogbone portion 19C.

By increasing the distance between the corner 20a and the corner 22a (h4), the wiring portion 19d with a narrow wiring width will be placed above the wiring 17A of the first wiring layer, and the wiring portion 19d will be placed above the wiring 17A of the first wiring layer. 1
The portion of the wiring layer that spans the step portion increases. If the area of the narrow wiring portion 19d on the step portion of the base increases, EM failures and SM failures are likely to occur, and the reliability of the wiring decreases.

In this way, the corner portions 20 of the dockbone portions 17a and 19a
is chamfered, and the corner 2 of the wiring opposite to the corner 20
0, the distance d+6 is configured to be larger than the minimum distance d3. In this way, poor resolution can be prevented and reliability of wiring can be improved. Further, since the channel spacing between the first wiring layer and the second wiring layer can be reduced, the number of wirings can be increased and the mounting efficiency of the logic circuit can be improved.

Further, a wiring portion 17c diagonally faces the corner portion 20 of the dock bone portions 17a and 19a.

The corner 22 of 19c is also chamfered, and the distance d9 between the corner 20 and the corner 22 is configured to be larger than the minimum distance d3. This makes it possible to prevent poor resolution, reduce the probability that a wiring portion with a narrow wiring width will be located above the underlying stepped portion, and improve the reliability of the wiring.

Note that regarding a wiring structure having a square-shaped dogbone portion, for example, there is Japanese Patent Application Laid-Open No. 57-50448 published on March 24, 1982. The margin width d3 of the dowel for preventing misalignment in the diagonal direction is, for example, about 087 μm, and the interval d3 is, for example, about 1.13 μm.

Note that the margin width d8 for preventing misalignment in the diagonal direction may be above the margin r379 for preventing misalignment, that is, d8≧d7.

Next, regarding the method for forming the above-mentioned semiconductor integrated circuit device,
This will be briefly explained using FIGS. 4A and 4B, FIGS. 5A to 5C, and FIGS. 6A to 6D.

As shown in FIG. 4A (process flow), first, a logic configuration (function) to be mounted on the semiconductor integrated circuit device 10 is designed and a logic circuit is created <40>.

Next, based on the logic circuit, the placement and wiring of the logic circuit is automatically performed using an automatic placement and routing system (DA) using a computer. Input this connection information into the automatic placement and routing system as connection information (NET FILE) that can be handled by the automatic placement and routing system <411
>.

Next, the base data of the automatic placement and routing system <415>
A semiconductor integrated circuit device (virtually represented) stored in
The designed logic circuit is automatically placed on the base chip) based on the connection information input to the automatic placement and wiring system <412>. Automatic placement of logic circuits is performed when macro cells (logic elements) <4 stored in the automatic placement and routing system are used.
16) is automatically arranged along the basic cell pattern. <415> is information on the arrangement of basic cell patterns on the semiconductor integrated circuit device (base chip).

Next, based on the connection information, the automatically placed logic circuits are automatically connected to complete the logic circuit information. <
413>.

This automatic wiring layout design step <413> is provided with a function <50> shown in FIG. 4B, which will be described later, in order to form the above-mentioned wiring IIA structure.

Next, the logic circuit information completed by the automatic placement and routing system is converted into mask creation data based on design rules in the automatic placement and routing system <414>.

The steps from the step <411> of inputting connection information to the step <414> of converting it into mask creation data are automatically processed by the automatic placement and wiring system.

Next, a connection mask is formed using an electron beam (EB) lithography device based on the mask creation data.
.

Next, a device process is performed using a wiring mask (43), whereby a semiconductor integrated circuit device having a predetermined logical configuration (circuit) is substantially completed (44).

Next, a case will be described in which, for example, wiring pattern data of an actual wiring mask is automatically created from wiring data created in the automatic wiring layout design stage.

In order to form the above-mentioned wiring structure, the automatic placement and wiring system is equipped with the function <50> shown in FIG. 4B.

As shown in FIG. 4B, first, a wiring route is automatically created based on the wiring information (51).

FIG. 5A shows a part of the layout plane during automatic wiring layout design after macro cells have been placed.

A-SD indicates terminals of the macro cell.

In the wiring route creation step <51>, a route search between terminals A and B and between terminals C and D is performed using a route search method such as a maze method, a line segment search route method, or a channel wiring method.
As shown in FIG. 5B, a wiring route 60 connecting terminals A and B and a wiring route 62 connecting terminal C1D are automatically created.

Next, in the part connecting the first wiring layer and the second wiring layer,
Take out the through-hole cell (element cell for connection hole portion) TE01 having the following information from the through-hole cell library (54) and place it (52). That is, the through-hole cell TH,2 is connected to the dockbone section 1.
Information forming 7a, 19a and its dockbone part 1
7a and 19a, and information for recessing a portion of the wiring at different potentials adjacent to the dockbone portions 17a and 19a in a direction away from the dogbone portions 17a and 19a. Note that the subscript of through-hole cell TH indicates a wiring layer.

Next, wiring pattern data 53> is created.

In the automatic placement and routing system, the following functions +5111. +512) is provided.

First, as shown in FIG. 5C, the created wiring route 60
．． 62 is distributed to wiring data for each wiring layer.

Note that, in order to simplify the explanation, FIG. 5C shows only the wiring routes 60 and 62 of the first wiring layer. Then, the wiring data is automatically converted into graphic data having the width and size as shown in FIGS. 6A and 6B <511>.

FIG. 6A shows a rectangular wiring pattern 6 created based on the wiring data of the wiring route 60.62 (FIG. 5C).
Only 0c and 62c are shown. Wiring pattern 60c,
The pattern spacing of 62c is, for example, the above-mentioned wiring 17,
It is assumed that the minimum interval d3 of 17 is equivalent.

Further, the pattern width is, for example, equal to the width d2 of the wiring portion 17c.

FIG. 6B shows the graphical data of the through-hole cell TH, □. In the center of the graphic data of the through-hole cell TH,2, a region 18a including information for forming the through-hole portion 18 is set in coordinates. That area 18
On the outer periphery of a, an area 17a1 having, for example, a diagonal shape and having information for forming the dogbon part 17a is set in coordinates. Further, on the outer periphery of the area 17a, an area 64 is set with coordinates that includes information for recessing a part of the wiring with a different potential adjacent to the dog bone part 17a in a direction away from the dog bone part 17a. There is. Area 6
4 is defined in such a way that when a wiring with a different potential that is not adjacent to the dog bone portion 17a overlaps with the region 64, the overlapping wiring portion is removed. The width d18 of this region 64 is, for example, equal to the minimum interval d3.

Next, as shown in FIG. 6C, the graphic data of FIGS. 6A and 6B are synthesized <512>. Then, wiring pattern 6
The portion adjacent to area 17a1 at 0c is area 17
a and the wiring pattern 62c is removed so that the distance is the minimum distance d3. However, the definition of the region 64 is not applied to the wiring pattern 60 of the same potential connected to the region 17a and the region 17a1 connected to the adjacent wiring pattern. Note that the diagonal line in FIG. 6C indicates area 6.
4 and the wiring pattern 62c are shown, and a part where the wiring pattern 62c is removed is shown.

As a result, as shown in the sixth diagram, in the wirings 17 and 17 adjacent to each other, a depression is formed in a part of the wiring 17 adjacent to the dogbone part 17a in a direction away from the dogbone part 17a. Wiring pattern data is created such that only the wiring portion 17b sandwiched between the portions 17a has the minimum line width.

After this, the automatic placement and routing system converts it into mask creation data based on design rules <414>
.

Note that the wiring pattern data created in this manner can also be used as wiring pattern data for, for example, a wafer direct writing apparatus.

In this way, in the method for forming a semiconductor integrated circuit device that adopts the mask slicing method formed by an automatic placement and wiring system, the wiring patterns 60c, 6 are formed based on connection information.
2c <511+, and a step +512+ of arranging a through-hole cell TH, □ having information for recessing a part of the wiring pattern 62c adjacent to the dockbone portion 17a1 at the connection portion.

As described above, according to this embodiment, it is possible to obtain the following effects.

(a) In a semiconductor integrated circuit device having a multilayer wiring layer in which wiring layers and interlayer insulating films are alternately stacked, a dockbone portion 17a is located in a connection hole portion 18 that connects different wiring layers.
, 19a, the dockbone portion 17a
, 19a are configured with a chamfered shape (cornered shape), so that poor resolution can be prevented and the reliability of wiring can be improved, and the X direction (CL, one direction) can be improved. Furthermore, the channel spacing in the Y direction (one direction of CL2) can be reduced, and the effective efficiency of the logic circuit can be improved.

(b) In the above (a), the interconnects 17. which are adjacent to each other.
1'9, the dock bone portion 17a.

A part of the wiring 17.19 adjacent to 19a is recessed in the direction away from the dog bone parts 17a, 19a, and the wiring part 17 is sandwiched between the dog bone parts of the adjacent wiring.
Only the width d1 of b is set to the minimum line width, and the other wiring portions 17
By making each of the widths d2゜dlo of c and 19d wider than the minimum line width, the wiring portion 17b with the minimum line width is only a small part of the entire wiring 17. Wiring structure with minimum line width for all parts except for wiring part 1
7b and the probability that the wiring portion 17b with the minimum line width is located above the base step can be significantly lowered.

In addition, since the corner 22 of the wiring portion 19c which is on the same layer as the corner 20 of the dock bone portion 19a and is opposite to the corner 20 of the dog bone portion 19a is chamfered, poor resolution can be prevented and the wiring portion 19c with a narrow wiring width d1o can be , it is possible to reduce the probability that the lower layer wiring 17A is located above the base step portion.

(c) According to (6) above, the current density of the wiring 17 can be lowered, so that the EMifference property of the wiring 17 can be improved.

Also, wiring 17. ．． Increased wide area of 19, wiring 17
．． Since bamboo grain boundaries are difficult to form in wiring 19,
It becomes possible to improve the 3M resistance of 7.19. Moreover, it becomes possible to lower wiring resistance.

(d) With the above (a) to (c), it becomes possible to significantly improve the reliability of the wirings 17 and 19, and it becomes possible to obtain a highly reliable semiconductor integrated circuit device 1.

(e) At the stage of automatic wiring layout design (412>), a through-hole cell TH, □, which includes information for recessing a part of the wiring adjacent to the dockbone part 17a, is added to the through-hole part 18 that connects different layer wiring. Place <512>
As a result, it is possible to create wiring pattern data in which only the width d1 of the wiring portion 17b adjacent to the dockbone portion 17a has the minimum line width, so that the creation time can be shortened.

In addition, the wiring portion adjacent to the dock bone portion 17a],
Since it is possible to create wiring pattern data such that only the width d of 7 b is the minimum line width, the reliability of the wiring 17 and 19 and the implementation efficiency of the logic circuit can be improved without compromising the ease of wiring layout. It becomes possible to improve the performance.

[Embodiment 2] Embodiment 2 is a second embodiment of the present invention in which the method for forming a semiconductor integrated circuit device is different from that of Embodiment 1.

The method for forming the semiconductor integrated circuit device of this example is as follows: Example 1
In place of the function <50> provided in the automatic wiring layout design stage <413>, a function 70> shown in FIG. 7 is provided.

As shown in FIG. 7, first, a wiring route is automatically created based on the connection information in the same manner as in the first embodiment <71>. In the wiring route creation step <71>, as shown in FIG. 8A,
After creating the wiring route 80.82, the created wiring route 80.82 is separated into each wiring layer as shown in FIG. 8B.
Retained as layout information.

In order to simplify the explanation, FIG. 8B shows only the wiring routes 80c and 82c of the first wiring layer.

Here, the wiring paths 80c and 82c of each wiring layer include wiring width information and placement position information for arranging a through-hole cell in a portion 84 connecting the first wiring layer and the second wiring layer. .

Next, based on the layout information, the wiring paths 80c and 82c of each wiring layer are automatically converted into graphic data (wiring pattern) having a width and size as shown in FIG. 8C (72). FIG. 8C shows a rectangular wiring pattern 17b created based on the layout information of the wiring routes 80c and 82c, and an octagonal area 17a1 having coordinate information for forming the dockbone portion 17a. ing. The wiring width of the wiring pattern 17b is, for example, equal to the width d1 of the wiring portion 17b having the above-mentioned minimum line width.

This graphic data is held as wiring pattern data A.

Next, based on the layout information, the wiring paths 80c and 82c of each wiring layer are automatically converted into graphic data (wiring pattern 17c,) having the width and size as shown in Figure 8 (73).

The eighth diagram shows a rectangular wiring pattern 17c created based on the layout information of wiring routes 80c and 82c.
, is shown.

The wiring pattern 17c1 is a rectangular wiring pattern 17.
This is a rectangular bulge 90 shown by a hatched area located on the outer periphery of b1. It is equipped with coordinate information.

The pattern spacing D1 of this wiring pattern 17c1 is, for example, equivalent to the minimum spacing d3 of the wirings 17.17 described above. Further, the pattern width D2 is, for example, the wiring portion 17c.
width d2.

This graphic data is held as wiring pattern data B.

Next, as shown in FIG. 8E, a through-hole cell THH2" (connection hole element cell) T
Take out HI□' and place it <74>.

In the center of the graphic data of the through-hole cell TH, 2', a region 18a including information for forming the through-hole portion 18 is set in coordinates.

On the outer periphery of the area 18a, an area 92 is set with coordinates that includes information for recessing a part of the wiring adjacent to the dogbone part 17a in a direction away from the dogbone part 17a. The region 92 is defined so that when it overlaps with the bulge 90, the overlapping wiring portion is removed. In FIG. This shows the portion where the bulge 90 is removed. As a result, the wiring pattern 17c1'' having the shape of the bulge 90' shown in FIG. 8F is held as the wiring pattern data C.

Next, as shown in Fig. 8G, the figure data of Fig. 8C and F are synthesized to create wiring pattern data 17°.
5〉. As a result, in the wirings 17, 17 adjacent to each other, a depression is formed in a part of the wiring adjacent to the dogbone part 17a in the direction away from the dogbone part 17a, and the wiring part 17b sandwiched between the dogbone part 17a Create wiring pattern data that has the minimum line width.

Thereafter, as in the first embodiment, in the automatic placement and routing system, the data is converted into mask creation data based on the design rules <414>.

In this way, in the method for forming a semiconductor integrated circuit device that adopts the mask slicing method formed by an automatic placement and wiring system, the first wiring pattern 17b is
1. Step of creating 17a1 <72n, wiring pattern 1
7b, a step of creating a wiring pattern 17c1 with information to add a bulge 9° to the dock bone portion 17a1 (73>, creating a through-hole cell THI2' with information to remove a part of the wiring pattern 17c1 adjacent to the dock bone portion 17a1); , placed on wiring pattern +7 c 4, wiring pattern 1
7c.

(74>, wiring pattern 17b,

A step 75> of synthesizing the wiring pattern 17cl' with the wiring pattern 17a1 to create wiring pattern data 17'' is provided.

The semiconductor integrated circuit device formed in this manner can have the following effects in addition to the effects of the first embodiment.

In the step <74> of arranging the through-hole cell TH,2'' in the automatic wiring layout design step <412>,
Since it is not necessary to perform a process in which the definition of the region 11 is not applied to the wiring pattern 60 having the same potential as the tongue bone portion 17a as in the first embodiment, the time required to create the distribution pattern data can be shortened.

(Embodiment 3) Embodiment 3 is a third embodiment of the present invention that differs from Embodiment 1 in the graphic data of the through-hole cells.

FIG. 9 shows graphic data of the through-hole cell THI2 of this example. In Example 1, the area 64 indicated by the hatched area is provided in a part of the through-hole cell TH process.
different from. The spacing d1m is, for example, equivalent to the minimum spacing d3, and the spacing (il) is, for example, d3--←(,-dΩ
− is equivalent to As a result, as in Example 1, the sixth
The wiring pattern data shown in the figure is created.

The semiconductor integrated circuit device formed in this manner can achieve the same effects as those of the second embodiment.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

For example, in the embodiment described above, a case has been described in which the logic circuit block and the input/output circuit block B i -CM OS circuit are configured, but the present invention is not limited to this and various modifications are possible.
An MO5 circuit may also be used.

Further, in the above embodiment, a case has been described in which all the circuit blocks of a semiconductor integrated circuit device are configured by wiring having the structure described in the above embodiment, but the present invention is not limited to this. The wiring formed on the region may have the structure described in the above embodiment.

In the above description, the invention made by the present inventor was mainly applied to a composite gate array equipped with a memory, which is the background field of application, but the invention is not limited to this and can be applied in various ways. It is also possible to apply the present invention to other semiconductor integrated circuit devices such as arrays, standard cells, and general-purpose LSIs.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

Since the appearance rate of fine wiring and the probability that fine wiring is located above the base step can be significantly lowered than before, for example, the EM resistance and 5M1fl property of the wiring can be improved, and furthermore, the wiring resistance can be reduced. This makes it possible to improve the reliability of wiring. Further, the wiring spacing (channel spacing) can be reduced in the X-Y direction, and the number of wiring can be increased to improve the mounting efficiency of the logic circuit.

Further, since the wiring pattern can be designed so that only the wiring portion adjacent to the dockbone portion has the minimum line width, it is possible to improve the reliability of the wiring without impairing the ease of wiring layout.

Furthermore, it is possible to improve the mounting efficiency of logic circuits without impairing the ease of wiring layout.

[Brief explanation of drawings]

FIG. 1 is a partial plan view showing a conventional wiring structure, FIG. 2 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIGS. FIG. 3B is an enlarged plan view of the main part of the wiring shown in FIG. 3A, and FIG. 4A is a diagram showing the first wiring layer in FIG.
, B is a process flow showing a method for forming this semiconductor integrated circuit device. FIGS. -D is a partial plan view of a layout plane showing the process of converting wiring data created by this automatic wiring layout into actual wiring pattern data, and FIG. 7 is a semiconductor integrated circuit according to a second embodiment of the present invention. Process flow diagrams illustrating the device formation method. FIGS. 8A to 8G are layout planes illustrating the process of converting wiring data created by automatic wiring layout, which is the manufacturing method of this semiconductor integrated circuit device, into actual wiring pattern data. FIG. 9 is a plan view showing graphic data of a through-hole cell used in automatic wiring layout, which is a method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention. In the figure, 17 and 19 are wiring, 17a and 19a are tosock bone parts, 18 is a through hole (connection hole part), TH, TH,
TH" is a through-hole cell (element cell for connection hole), D is channel spacing, and CL + and CL 2 are center lines. Figure 3B Figure A Figure 4B Figure <41> L1 LI L1 Figure 6A [Ll [S1 Ll L1 [I] Ll [S1 L1 Figure 6C Figure D Figure 7C1 Figure 8F Figure CL+

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a multilayer wiring structure in which a dock bone portion is formed in a connection hole of a wire connecting different wiring layers, wherein the front dog bone portion has a corner thereof. A semiconductor integrated circuit device characterized by having a chamfered shape. 2. In mutually adjacent wirings formed on the same wiring layer, the wiring portion adjacent to the dogbone portion is recessed in the direction away from the dogbone portion, and the width of the wiring portion is reduced compared to the portion that is not recessed. 2. The semiconductor integrated circuit device according to claim 1, wherein the recessed wiring portion is narrower than the width and has chamfered corners. 3. The semiconductor integrated circuit device according to claims 1 and 2, wherein the dogbone portion has an octagonal shape. 4. When manufacturing the semiconductor integrated circuit device according to claim 2,
At the stage of automatic wiring layout design, a connection hole element cell having information for recessing a wiring part adjacent to a dock bone part in a direction away from the dog bone part is arranged in the connection hole part. A method for manufacturing a semiconductor integrated circuit device. 5. The stage of automatic wiring layout design includes a stage of forming a wiring pattern, a stage of forming a bulge in the wiring pattern, and a stage of connecting the connection hole element cell having information for deleting only the bulge. 1. A method for manufacturing a semiconductor integrated circuit device, comprising the step of arranging it in a hole. 6. A semiconductor integrated circuit characterized in that the information for recessing the wiring portion adjacent to the dogbone portion in the direction away from the dogbone portion is provided only in an area close to the adjacent wiring of the connection hole element cell. A method of manufacturing a circuit device.