JPH0486098A - Signal transmission equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention connects a central processing unit and a plurality of terminal devices with a pair of transmission lines, and connects the central processing unit to the terminal devices cyclically. The present invention relates to a signal transmission device that transmits a transmission signal to a computer.

(Prior Art) As a conventional signal transmission device for remote control of this type, a central processing unit and a plurality of terminal devices are connected by a pair of transmission lines, and transmission signals from the central processing unit to the terminal devices are It is considered that the transmission signal from the terminal device to the central processing unit is transmitted in the voltage mode and in the current mode.

(Problem to be Solved by the Invention) However, when the transmission line is long, when a current mode transmission signal is output from a certain terminal to the central processing unit, the signal voltage of the transmission line drops and becomes below the threshold voltage. Even though there is no voltage mode transmission signal, other terminals may misread it as a voltage mode transmission signal.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a signal transmission device that can lengthen the transmission distance without causing misreading of the transmitted signal.

[Structure of the invention]

(Means for Solving the Problem) The present invention connects a central processing unit and a plurality of terminal devices through a pair of transmission lines, transmits a synchronization pulse from the central processing unit to the plurality of terminal devices, and transmits a synchronization pulse from the central processing unit to the plurality of terminal devices. In a signal transmission device that transmits a transmission signal from a processing device to the terminal device in a voltage mode, and a return signal from the terminal device to the central processing device in a current mode, in a time-division manner, the terminal device transmits the After a synchronization pulse is received from the central processing unit, a reception prohibition period is provided during which a return signal is permitted to be output to the central processing unit, and a reception prohibition period is prohibited from inputting a transmission signal from the central processing unit.

(Operation) In the present invention, the central processing unit outputs a synchronization pulse and transmits a voltage mode transmission signal to the terminal device. In addition, the terminal device transmits a current mode transmission signal to the central processing unit, and the terminal device prohibits the input of the transmission signal from the central processing unit for a predetermined period of time after receiving the synchronization pulse to prevent misreading. let

(Embodiment) An embodiment of the signal transmission device of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a central processing unit, and this central processing unit ff1il is connected to a plurality of terminal devices 3 via a pair of transmission lines 2.
and a monitoring display panel 4 etc. are connected. Each terminal 3 has a load such as a lighting fixture (not shown),
Alternatively, a wall switch, illuminance sensor, etc. are connected.

This central processing unit 1, as shown in FIG.
A current detection circuit 11 that detects the current mode signal from the terminal device 3, and a current detection circuit 11 that is connected to this current detection circuit 11, takes in data according to a predetermined sequence, collects data of each terminal device 3, and based on these data It consists of a signal processing circuit 12 that creates a transmission voltage signal consisting of a control signal, etc., and a drive circuit 13. The signal processing circuit 12 is connected to the current detection circuit II, and when the output voltage of the current detection circuit 11 is detected, the signal processing circuit 12 is connected to the current detection circuit II. Later, a signal for inverting the voltage is output to the drive circuit 13. Note that the central processing unit 1 further includes:
A keyboard and switches or sensors for data input, and a display device such as a CRT for various displays are connected as necessary.

In the central processing unit of FIG. 2, the current detection circuit 11
converts the current of a current mode transmission signal such as monitoring data flowing between the central processing unit 1 and the terminal device 3 via the transmission line 2 into a voltage.

The drive circuit 13 drives the transmission line 2 with a bipolar signal according to the signal from the signal processing circuit 12. For example, if the input signal is at the "1" level, the drive circuit 13 pulls up the transmission line 2 to +24V and pulls up the transmission line 2 to "0". ” level, it is pulled down to -24.

Further, as shown in FIG. 3, the terminal device 3 has a reception prohibition period for a predetermined time after the synchronization pulse 5YNC is output from the central processing unit 1, and then has an inversion voltage reading permission period in which the inversion voltage is read. There is.

Further, as shown in FIG. 4, in the terminal device 3, a receiving circuit 2J, a transmitting circuit 22, etc. are connected to the transmission line 2, and a signal processing circuit 23 is connected to the receiving circuit 21 and the transmitting circuit 22. One or more loads 24 are connected to the signal processing circuit 23 .

Then, the receiving circuit 21 connects the central processing unit 1 to the transmission line 2.
When the signal processing circuit 23 receives the voltage mode transmission signal transmitted to the receiver circuit 21, the signal processing circuit 23 operates according to a predetermined sequence, receives and receives the control signal, etc. included in the voltage mode transmission signal received by the receiving circuit 21. A load drive signal based on the control signal, etc. of , this, etc. is supplied to the load 24, or if this load 24 is a monitoring load, the monitoring signal is detected to create monitoring data, and this monitoring data is generated according to the control signal, etc. The data is output to the transmitting circuit 22. Then, the transmission circuit 22 transmits a current mode transmission signal to the transmission line 2 according to the monitoring data output from the signal processing circuit 23. Note that when the output impedance of the drive circuit 13 of the central processing unit 1 is low, there is almost no change in the line voltage of the transmission line 2 due to this current mode signal.

Further, the receiving circuit 21 is specifically constructed as shown in FIG. First, the received signal is inverter circuit 1nV2
Through +, the waveform shaping circuit 21! It is now entered into This waveform shaping circuit 211 consists of four flip 70 tubes F F 21. FF 21 FF,
, and FF24, and two AND circuits AN,
and AN22. The received signal is then shaped into a waveform. A state change pulse generation circuit 21b is connected to the waveform shaping circuit 211, and the state change pulse generation circuit 21b is composed of a flip-flop FF16, an OR circuit 0R21, and an AND circuit AN2-. The state change pulse circuit 21b outputs a pulse when the state changes. Also, the AND circuit A N2 of the state change pulse generation circuit 21b.
are connected to two counters CO2 and C022, and these counters C02I and CO2□ are connected to decoders DE2. and DE2□ are connected, and these decoders DE2. and DE2□ are connected to the AND circuit AN of the state change pulse generation circuit 21b via the AND circuit 24 and the AND circuit AN24 of the state change pulse generation circuit 21b.
2. It is connected to the.

Furthermore, as shown in FIG. 6, the monitoring display panel 4 connects a receiving circuit 25 to the transmission line 2, and sequentially continuously connects a signal processing circuit 26, a display section 27, etc.

Then, the receiving circuit 25 connects the central processing unit ll to the transmission line 2.
When the signal processing circuit 26 receives the voltage mode transmission signal transmitted to the terminal 3. The monitoring data etc. are determined based on the voltage mode transmission signal obtained by converting the current mode transmission signal sent from the central processing module ff1ll, and a display signal corresponding to this monitoring data is transmitted to the display section 27. The display unit 27 is composed of display elements such as LEDs, triacs, LED arrays, LCDs, or CRTs, and a drive circuit for driving these display elements, and according to display signals input from the signal processing circuit 26. The status of the load etc. is indicated by blinking these display elements or by displaying lines, figures, characters, etc. on these display elements.

A specific circuit of the central processing bag a1 is shown in FIG. 7, for example.

The central processing bag M1 includes a microprocessor (CPU) 31
The functions corresponding to the signal processing circuit 12 are based on the operation program of the microprocessor 31.

Further, an analog-to-digital converter (A/D converter) 32 for converting the analog output of the current detection circuit 11 into digital data that can be processed by the microprocessor 31 and supplying the digital data, for example, a drive circuit 1 from an AC power source.
A DC power supply 33 that generates a DC voltage of +24v1-24v for the output stage of No. 3 and +5v for circuits other than this output stage.
, a zero-crossing detection circuit 34 for detecting zero-crossing of the AC power supply, a zero-crossing signal transmitting circuit 35 for transmitting a zero-crossing signal to the transmission line 2, a transmitting circuit 36 for generating a drive clock for the microprocessor 31, and putting the microprocessor 31 into an initial state. A reset circuit 37 for setting is provided.

When transmitting a transmission signal from the central processing unit 1 to the terminal device 3, the microprocessor 31 determines that the "0" level is OV,
A voltage signal with a “1” level of 5V is supplied to the drive circuit 13. In addition, the drive circuit 13 has a "0" level of 124 V according to a voltage signal from the microprocessor 31.
Then, the "1" register transmits a +24V voltage mode transmission signal to the transmission line 2.

The zero cross detection circuit 34 connects, for example, a commercial AC power supply of Act 00v to a diode bridge DB via an isolation transformer T.
A resistor R1 and a capacitor CI are connected between the output terminals of , and the negative terminal is grounded, and a resistor R6 and a capacitor C
The connection point of I is connected to the phototransistor Tr via the resistor R2.
The collector of this transistor Tr is connected to +5V of a DC power supply 33 via a resistor R3, and also connected to the microprocessor 31, and its emitter is grounded. Then, the control transformer T1 steps down the voltage, the diode bridge D B + performs full-wave rectification, and the base current is applied to the base of the transistor Tr for ultra-class C amplification. When this full-wave rectified output is Ov. That is, the transistor Tr is turned off at the zero-crossing timing of the commercial AC power supply, and a 5V zero-crossing signal "1" is generated at the collector of the transistor Tr+.

Furthermore, the microprocessor 31 supplies the zero-crossing signal as it is to the zero-crossing signal transmitting circuit 35 when necessary, such as during central activation. This zero cross signal transmission circuit 3
5 connects an analog switch AS between the OUT terminal for the drive circuit 13 of the microprocessor 31 and the drive circuit 13, and connects the OUT terminal for the zero-cross signal transmission circuit 35 to the inverter circuit Inv. Connect to analog switch AS. In addition, the base of the transistor Tr2 is connected to the OUT terminal for the zero-cross signal transmission circuit 35 via a resistor R4, the emitter of this transistor Tr2 is grounded, and the collector is connected to +5V via a light emitting diode LED and a resistor R6. do. Additionally, light emitting diodes LED.

are a phototransistor PTr, a photocoupler PC,
The collector and emitter of the phototransistor P T r + are connected to a diode bridge DB, one end of the diode bridge DB2 is connected to the transmission line 2, and the other end is grounded.

When the zero-cross signal is input, the microprocessor 3 is turned off by turning off the analog switch AS.
1 to the drive circuit 13,
This blocks the signal transmission from the central processing unit 1 to the terminal device 3, and also drives the photocoupler PC1 by the zero-cross signal, shorting the AC terminals of the diode bridge DB2 and shorting the transmission line 2. do. Due to this short circuit, a zero cross signal of voltage O is transmitted to each terminal device 3.

Further, in the drive circuit 13, the base of an NPN type transistor Tr or a PNP type transistor Tr4 is connected to the analog switch AS via a resistor R6 or a resistor R7. The emitter of the NPN phototransistor Tr is grounded, and the collector is connected to two resistors R.
It is connected to the +24V output terminal of the DC power supply 33 via 8 and R. Furthermore, a transistor T r <
The emitter of the transistor Tr is connected, the base of the transistor Tr is connected to the connection point of the resistor Ra5R9, and the collector is connected to the base of the transistor Tr6.
The collector of r6 is connected to the DC power supply 33 through a resistor R7°.
The emitter is connected to one end of the transmission line 2.

On the other hand, the emitter of the PNP type transistor Tr is connected to the +5V output terminal of the DC power supply 33, and the collector is connected to the resistor R11, R
42 to one 24V output terminal of the DC power supply 33. Further, the emitter of a transistor Tr7 is connected to one 24V output terminal of the DC power supply 33 via diodes D3 and D4, and the base of the transistor Tr is connected to a resistor R1.
1, connected to the connection point of R1□, the collector is connected to the base of the transistor Trg, and this transistor Trs
The collector is connected to one 24V terminal of the DC power supply 33 via a resistor R11, and the emitter is connected to one end of the transmission line 2. Furthermore, the other end of the transmission line 2 is grounded via resistors R and 4.

Then, by outputting a positive or negative output from the OUT terminal for the drive circuit 13, the transistor Tr3
Alternatively, one of the transistors Tra is turned on, and an output of +24V or -24V is made to the transmission line 2.

Further, the current detection circuit 11 is connected to a resistor R from the other side of the transmission line 2.
It is connected to the inverting input terminal of operational amplifier OP or the non-inverting input terminal of operational amplifier OP2 via I5 or resistor R76. The non-inverting input terminal of the operational amplifier OP is grounded, a resistor R1□ is connected between the inverting input terminal and the output terminal, and the output terminal is connected to a diode D5 and a resistor RIR.
It is connected to an analog-to-digital converter 32 via.

On the other hand, the inverting input terminal of the operational amplifier OP is grounded, a resistor R,, is connected between the non-inverting input terminal and the output terminal, and the output terminal is connected to a diode D5 and a resistor R11+ via a diode D6. connected to a connection point.

Further, the transmitting circuit 36 is an OS of the microprocessor 31.
Connect a crystal oscillator Cr+ between the C, terminal and the OSC, terminal, and connect a capacitor C2 or a capacitor C3, each with one end installed at the OSC, terminal and the 0802 terminal, and connect the 08C2 terminal to the inverter circuit 1nv2.
It is connected to the CK terminal of the analog-to-digital converter 32 via.

Further, a specific circuit of the terminal device 3 is shown in FIG. 8, for example.

In FIG. 8, 41 is an LSI, and this LSI 41 is
It has the function of a signal processing circuit 23, and is connected to a receiving circuit 2I and a transmitting circuit 22.

In this receiving circuit 21, the collector of a transistor Tr is connected to the positive output side of a matching diode bridge DB3 connected to the transmission line 2 via a resistor R21, and the emitter of the transistor Tr is grounded. , the base is connected to the OUT terminal of the LSI 41 via the resistor R2□. Further, the transmitting circuit 22 is connected to the other end of the transmission line 2, and the transistors T r ,
The collector of this transistor Tr, , is connected to the DC power supply DC via a resistor R24, and is also connected to the IN terminal of the LSI 41, the emitter is grounded, and a resistor R2S is connected between the base and emitter. and a diode D7 are connected in parallel.

The receiving circuit 21 receives 0 or 5.0 depending on whether the voltage mode of the transmission line 2 is rOJ or IJ. A signal of V is generated and supplied to the LSI 41.

On the other hand, the transmission circuit 22 is supplied with a transmission signal from the terminal device 3 created by the microprocessor 41 to the central processing unit 1i1, and only when this transmission signal is "1", the transmission line 2
Connect a resistor Rz+ between the lines. At this time, the resistor R2+ becomes a current sink, and the current RPI flowing through the transmission line 2 changes depending on the current flowing through the resistor R21, and this is detected by the current detection circuit 11 of the central processing unit 1, so that the current RPI flows from the terminal device 3 to the central processing unit. Current mode signal transmission to 1 takes place.

Connected to the LSI 41 are a zero-cross signal receiving circuit 42, a self-address setting circuit 43, a clock generating circuit 44, a load driving circuit 45, a monitoring load 46, and an initializing capacitor C4.

In addition, the zero-cross signal receiving circuit 42 is connected to a voltage dividing resistor R26 and resistors R, 7 that divide the voltage between the output terminals of the diode bridge DB3 to about 175, and these resistors R2
6 and the resistor R27 are connected to the IN terminal of the LSI 41.

The line voltage of the transmission line 2 becomes 0 only when the central processing unit 1 transmits a zero cross, and at other times it becomes +24.
V or -24V.

Further, the self-address setting circuit 43 connects pull-up switches SW1. SW2, S N
V, and 3w4 are connected, and the self-address is set by turning on and off the respective self-address switches Sw1, SW7, SW, and 3w4.

Further, a crystal oscillator Cr= is connected between the OSC terminal and the 0802 terminal of the LSI 41, and a capacitor C6 and a capacitor C7 each having one end grounded are connected.

Further, in the load drive circuit 45, the microprocessor 41
The OUT terminal of is connected to the transistor Tr through the resistor R16.
, and the collector of the transistor Tr, , is connected to the base of the transistor Tr, , and the collector of the transistor Tr, , is connected to the light emitting diode LED2, LED, and the resistor R
DC power supply DC through 35.

It is connected to the. And these light emitting diodes LE
D2. The LED constitutes a photocoupling PC2 and a PCB using a photothyristor PTh or a photothyrist PTh2, respectively. Furthermore, the gates of these photothyristors PTh and PTh2 are connected to a resistor R17, an RNA, and a capacitor C, .
C,2 are connected to these photothyristors PTh.

A resistor R39 is connected in parallel to PTh2, and this resistor R
A capacitor C11 is connected in series to 39, and a resistor R,1'l and a capacitor CI3 are connected in series.
A triac TZ is connected to the triac TZ, a resistor Ran is connected to the gate of the triac TZ, one end of the triac TZ is connected to a commercial AC power supply, the other end is connected to one end of a load, and the other end of the triac TZ is connected to a commercial AC power supply. The other end of the load is connected, and a constant voltage element DA is connected between the commercial AC power source.

Then, the LSI 41 detects as a zero-cross signal when the output of the zero-cross transmitter/receiver circuit 42 changes from approximately 5V to Ov, and transmits this zero-cross signal and the control signal transmitted from the central processing unit 1 every half cycle of the commercial AC power supply. A 5V pulse is created with a phase angle based on the signal and is supplied to the load drive circuit 45.

As a result, in the load drive circuit 45, the triac TZ is turned on at the conduction angle specified by the control signal, and a lamp, which is a load (not shown), is dimmed and lit.

Further, the monitoring load 46 includes a resistor R4 connected to a DC power supply DC, and a switch S w q whose one end is grounded.

It is made up of.

When the switch S w 5 is operated in the monitoring load 46, the LSI 4] detects it and creates monitoring data indicating its on/off state. This monitoring data is transmitted to the central processing unit 1 in current mode.

A specific circuit of the monitoring display panel 4 is shown in FIG. 9, for example.

Reference numeral 51 denotes an LSI, and this LSI 51 has the function of the signal processing circuit 26, and is connected to the receiving circuit 25 and the display section 27.

The receiving circuit 25 connects the transistor Tr to one end of the transmission line 2 via the diode DI+ and the resistor R4□.
. It is grounded, and a resistor R44 is connected between the base and emitter.

Furthermore, the display section 27 has a resistor R4 connected to each OUT terminal.
The bases of the transistors T r , .

Then, the receiving circuit 25 determines that the voltage mode of the transmission line 2 is rO.
When a reception signal of O or 1 is generated depending on whether it is J or rIJ and supplied to the LSI 5+, the display unit 27 shows that the corresponding phototransistor Tr is turned on and the light emitting diode LED is turned on. and is displayed.

Further, in the clock circuit 52, a crystal oscillator Cr is connected between the OSC terminal and the OSC terminal of the LSI 5], and capacitors CI5 and C10 each having one end grounded are connected.

Further, an initializing capacitor C1□ whose one end is grounded is connected to the reset terminal.

Next, the operation will be explained with reference to a flowchart.

First, when the central processing unit 1, the terminal device 3, and the monitoring display panel 4 are powered on, they start operating according to the control program built into each microprocessor 31 and LSI 41, 51. do.

First, each microprocessor 31 and LSI 41.
The various memories and registers built into the controller 51 are initialized, and then the processes shown in the respective flowcharts are executed.

As shown in the flowchart of FIG. 10, the central processing unit 1 first sends transmission data consisting of a start signal ST, the address ADH of the destination terminal 3, a control signal CNT, etc. to the transmission line from the drive circuit 13 in voltage mode. 2), the process in step 101 is performed once until it is determined that the transmission is complete. One bit is sequentially processed each time it passes through, and if the number of processing times is less than the predetermined number of times, the processing returns to step 101. Step 101
When the process is repeated a predetermined number of times and a voltage mode transmission signal of a predetermined number of bits is transmitted, the output of the current detection circuit 11 is taken in (step 1o3), and the presence or absence of a current mode transmission signal from the terminal device 3 is determined. (step 104).

Note that if a current mode transmission signal is not detected within a predetermined time (for example, 600 us), it means that one bit of the return signal of the return data corresponding to the section to which the predetermined time belongs is "0", If detected, it means that the bit of the return signal is "1". and,
If it is determined that there is a return signal in step I [14], it is determined whether a certain period of time has elapsed after receiving the synchronization signal, that is, whether it is not a reception prohibited period (step 105); if the certain period has not elapsed, step It circulates and enters the standby state, and then, after transitioning to the reception permission section, the transmission voltage from the drive circuit 13 is reversed (step +06).
, waits until the return signal is no longer detected in step 107, and then inverts the transmission voltage again to return to the original voltage mode (step 108). Through these processes, the current mode return signal “1” becomes the voltage mode return signal “0”.
is converted to

On the other hand, if no return signal is detected in step 104, the process proceeds to step 109. In this case, the current mode transmission signal is "0" and the voltage mode transmission signal remains "1", which means that the current mode transmission has been converted to the voltage mode transmission signal.

Then, it is determined whether the return data from the terminal device 3 has been completed or not (step +09), and the conversion process from the two-sided mode transmission signal to the voltage mode transmission signal has been completed for all bits of the return data. If not, the process returns to step 103 because the return has not been completed. On the other hand, when the process is executed the same number of times as the number of bits of the returned data,
In step 109, it is determined that the return data from the terminal device 3 has been completed, and it is determined whether the returned data is normal (
Step 11O). This determination is made by, for example, returning the same signal as the transmitted control signal CNT as an acknowledgment ACK, and determining whether or not this acknowledgment matches the control signal CNT itself transmitted. If the returned data is normal, the process ends.

On the other hand, if the returned data is determined to be abnormal at step +10, the process returns to step 103.

Next, the operation of the terminal device 3 will be explained with reference to the flowchart shown in FIG.

When the terminal device 3 receives the synchronized pulse 5YNC, it counts whether a predetermined period of time, that is, a reception prohibited period has elapsed (Step 2011), and if the reception prohibited period has not ended, it maintains the reception prohibited state, After the reception prohibition period ends, the reception of the voltage mode transmission signal from the central processing unit is enabled (step 203), it is determined whether there is a transmission signal or not (step 2114), and if there is a transmission signal, the data is (Step 20
5 > If there is no transmission signal, return as is.

In the above embodiment, a random method was described in which the central processing unit 1 is activated from an arbitrary terminal device 3, but a cyclic method may also be used in which the central processing device 1 sequentially instructs different terminal devices 3 to circulate.

〔Effect of the invention〕

According to the present invention, a terminal device that operates with a voltage mode transmission signal from the central processing unit is prohibited from receiving a transmission signal from the central processing unit for a predetermined period of time after receiving a synchronization pulse from the central processing unit. By having the section, even if a voltage drop occurs due to a current mode transmission signal from another terminal device, the transmission signal is less likely to be misread, and malfunctions can be prevented. That is, it is possible to provide a device with high response reliability even when the transmission distance between the central processing unit and the terminals is increased or when a large number of terminals are connected to the transmission line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a signal transmission system according to a first embodiment of the present invention, FIG. 2 is a functional block diagram of a central processing unit, and FIG. 3 is a diagram explaining the format of a transmission signal.
Fig. 4 is a functional block diagram of the terminal, Fig. 5 is a block diagram showing the same receiver, Fig. 6 is a functional block diagram of the monitoring display panel, and Fig. 7 is a specific example of the central processing unit shown in Fig. 2. 8 is a circuit diagram showing a specific example of the terminal device shown in FIG. 4, FIG. 9 is a circuit diagram showing a specific example of the monitoring display panel shown in FIG. 6, and FIG. FIG. 11 is a flowchart showing the operation of the central processing unit shown in FIG. 8, and FIG. 11 is a flowchart showing the operation of the terminal device shown in FIG. 1. Central processing unit, 2. Transmission line, 3. Terminal device, R
PI: Current mode signal, RPV: Voltage mode signal. 4KIL

Claims (1)

[Claims] (1) A central processing unit and a plurality of terminals are connected by a pair of transmission lines, a synchronization pulse is transmitted from the central processing unit to the plurality of terminals, and a transmission signal is transmitted from the central processing unit to the terminals. is a voltage mode, and a return signal from the terminal device to the central processing unit is a current mode, and the terminal device transmits the synchronization pulse after receiving the synchronization pulse from the central processing unit. A signal transmission device characterized by having a reception prohibition period in which input of a transmission signal from the central processing unit is prohibited during a period in which return signal output to the central processing unit is permitted.