JPH0486098U - - Google Patents
Info
- Publication number
- JPH0486098U JPH0486098U JP12710090U JP12710090U JPH0486098U JP H0486098 U JPH0486098 U JP H0486098U JP 12710090 U JP12710090 U JP 12710090U JP 12710090 U JP12710090 U JP 12710090U JP H0486098 U JPH0486098 U JP H0486098U
- Authority
- JP
- Japan
- Prior art keywords
- count
- signal
- gate
- check signal
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000007257 malfunction Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Stepping Motors (AREA)
Description
第１図は本考案の一実施例に係るステツピング
モータ誤動作検出回路の構成を示すブロツク図、
第２図は同実施例の動作を説明するためのタイミ
ング図である。
１……チエツク信号出力回路、２……フラグ回
路、３……ＡＮＤゲート、４……カウンタ、５…
…ラツチ回路、６……原点信号出力手段。
FIG. 1 is a block diagram showing the configuration of a stepping motor malfunction detection circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram for explaining the operation of the same embodiment. 1...Check signal output circuit, 2...Flag circuit, 3...AND gate, 4...Counter, 5...
...Latch circuit, 6...Home signal output means.
Claims (1)
に作動する装置が原点位置にあるときに原点信号
を出力する原点信号出力手段と、前記原点信号が
立ち上がつた後の最初の前記ステツピングモータ
に対する正転及び逆転指令パルスの一方をチエツ
ク信号として出力するチエツク信号出力回路と、
前記チエツク信号が１パルスでも入力されると出
力ゲート信号をリセツトするフラグ回路と、前記
チエツク信号と前記ゲート信号との論理積をとる
ＡＮＤゲートと、アツプカウント端子、ダウンカ
ウント端子及びリセツト端子を有し、前記アツプ
カウント及びダウンカウント端子の一方に前記正
転及び逆転指令パルスの一方を、前記アツプカウ
ント及びダウンカウント端子の他方に前記正転及
び逆転指令パルスの他方を、そしてリセツト端子
に前記ＡＮＤゲートの出力を、夫々入力して前記
アツプカウント及びダウンカウント端子の入力パ
ルスをアツプカウント及びダウンカウントしてカ
ウント値を出力するアウンタと、前記カウント値
を前記チエツク信号によつてラツチするラツチ回
路とを具備することを特徴とするステツピングモ
ータ誤動作検出回路。 origin signal output means for outputting an origin signal when a device operated one-dimensionally by the target stepping motor is at the origin position; a check signal output circuit that outputs one of the rotation and reverse rotation command pulses as a check signal;
It has a flag circuit that resets the output gate signal when even one pulse of the check signal is input, an AND gate that takes the logical product of the check signal and the gate signal, an up count terminal, a down count terminal, and a reset terminal. One of the forward and reverse command pulses is applied to one of the up-count and down-count terminals, the other of the forward and reverse command pulses is applied to the other of the up-count and down-count terminals, and the AND is applied to the reset terminal. a counter that inputs the output of the gate, counts up and down the input pulses of the up-count and down-count terminals, and outputs a count value; and a latch circuit that latches the count value by the check signal. A stepping motor malfunction detection circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12710090U JPH0486098U (en) | 1990-11-28 | 1990-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12710090U JPH0486098U (en) | 1990-11-28 | 1990-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0486098U true JPH0486098U (en) | 1992-07-27 |
Family
ID=31874615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12710090U Pending JPH0486098U (en) | 1990-11-28 | 1990-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0486098U (en) |
-
1990
- 1990-11-28 JP JP12710090U patent/JPH0486098U/ja active Pending
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