JPH0490190A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing the semiconductor memory with a dummy system and generating a non-actived signal based upon the operation completion timing of the dummy system. CONSTITUTION:The semiconductor memory is provided with an address buffer 12 to be an essential data reading system, an address transition detection(ATD) circuit 13, a decoder 14, a memory array 11, and a sense amplifier 16. The device is driven in parallel with the essential system for reading out data and completes its operation simultaneously with the system. On the other hand, a dummy word line DWL, a dummy memory cell DM, a dummy bit line DBL, a dummy sense amplifier 18, and an inverter to be a non-activated signal generating part as the dummy system. The non-activated signal generating part generates a non-activated signal based upon the operation completing timing of the dummy system. Since the non-activated signal can be generated extremely quickly as compared with a convensional case after completing the reading of data, power consumption can be reduced.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to an internally synchronous type semiconductor memory device.

[Conventional technology]

Conventionally, this type of internally synchronous semiconductor memory device is
There is something like the one shown in Figure 2. This semiconductor memory device generates an address signal representing selection of a memory cell in a memory array 101 by an address buffer 102 based on an address input from the outside, and also performs address transition detection (A) to detect a transition of the address input.
TD) circuit 103 to generate a pulsed internal synchronization signal (hereinafter referred to as rATD signal). Then, the decoder +04 is operated in synchronization with the generation timing of this ATD signal to select the word line WL and specify the memory cell M. Furthermore, the sense amplifier 106 is operated in synchronization with the generation timing of the ATD signal to sense and amplify the signal representing the storage content of the memory cell M appearing on the bit line BL. On the other hand, in this semiconductor memory device, the deactivation signal (APD) generation circuit 105 generates a deactivation signal (hereinafter referred to as "APD signal") after a certain period of time has elapsed from the generation timing of the ATD signal. This APD signal is transmitted to the reset circuit 107 by delaying the ATD signal by a certain period of time in the delay circuit 107.
It was initialized and created in 08. After the sense amplification of the sense amplifier 106 is completed and the data reading is completed, the APD signal is used to detect the portions (including the decoder 104 and the sense amplifier 106) where the DC current is flowing inside the semiconductor memory device. Deactivate. This stops unnecessary power consumption inside. In this way, when the address input transitions, A
The APD generates a TD signal and operates each part sequentially in synchronization with this ATD signal to read data at high speed.
It is deactivated by a signal.

[Problem to be solved by the invention]

Incidentally, from the viewpoint of reducing power consumption, it is desirable to perform deactivation immediately after data reading is completed. However, if deactivation is performed before data reading is completely completed, malfunctions will occur. Therefore, it is necessary to synchronize the timing at which reading is completed and the timing at which deactivation is performed. Here, the conventional semiconductor memory device described above has a system (decoder 10) that directly reads data.
4) (including memory array 101- and sense amplifier 106) and APD generation circuit 105 start operating in synchronization with the ATD signal. However, the timing at which reading is actually completed and the timing at which the APD signal is generated are not synchronized and are independent. For this reason, it is necessary to set the timing at which the APD signal is generated to be sufficiently later than the timing at which reading is actually completed to provide some margin, and there is a problem in that unnecessary power is consumed internally for a considerable period of time. SUMMARY OF THE INVENTION An object of the present invention is to provide an internally synchronous semiconductor memory device that can be deactivated much more quickly than before after data reading is completed, thereby reducing power consumption. The goal is to provide equipment.

[Means to solve the problem]

In order to achieve the above object, the present invention generates a pulsed internal synchronization signal by an address transition detection circuit when an address input transitions, and operates a decoder in synchronization with the generation timing of the internal synchronization signal. A word line is selected to identify a memory cell, and a sense amplifier is operated in synchronization with the generation timing of the internal synchronization signal to sense-amplify the signal representing the memory content of the memory cell transmitted to the bit line, and sense it. In a semiconductor memory device that deactivates a portion through which a direct current flows internally by a deactivation signal after completion of amplification, a dummy word line is provided in parallel with the word line and selected at the same time as the word line. and a dummy memory cell 7 that stores either logic 1 or logic 0 and is selected by the dummy word line, and is provided in parallel with the bit line and is capable of transmitting a signal representing the memory content of the dummy memory cell. a dummy bit line, a dummy sense amplifier that sense-amplifies and outputs a signal representing the memory content of the dummy memory cell appearing on the dummy bit line in the same amplification time as the sense amplifier; and an output signal of the dummy sense amplifier. In response to this, the present invention is characterized in that it includes a deactivation signal generating section that generates a deactivation signal based on the timing at which the sense amplification of the dummy sense amplifier is completed.

[Effect]

The dummy word line and dummy bit line are the original word line,
Since they are provided in parallel with the bit lines, they have the same parasitic capacitance as the original word lines and bit lines, respectively. Further, the dummy sense amplifier performs sense amplification in the same amplification time as the original sense amplifier. Therefore, the timing at which the sense amplification of the dummy sense amplifier is completed coincides with the timing at which the sense amplification of the original sense amplifier is completed. Here, the deactivation signal generator generates the deactivation signal based on the timing at which the sense amplifier of the dummy sense amplifier is completed. This is equivalent to generating an inactivation signal based on the timing at which sense amplification of the original sense amplifier is completed. Therefore, it is no longer necessary to take a timing margin, and after the original sense amplifier has completed its sense amplification, that is, after data reading has been completed, it is possible to deactivate it much earlier than in the past. becomes. Therefore, the period during which power is wasted inside the device can be shortened, and power consumption is reduced.

【Example】

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor memory device of the present invention will be explained in detail below with reference to illustrated embodiments. As shown in FIG. 1, this semiconductor memory device includes an address buffer 12, an ATD circuit 13, a decoder 14, a memory array 11, and a sense amplifier 16 as the original data reading system, as in the conventional case. ing. Furthermore, a dummy word line DWL, a dummy memory cell DM, a dummy bit line DBL, and a dummy sense amplifier 18 are provided as a dummy system for the data read system, and an inverter 19 is provided as a deactivation signal generating section. We are prepared. The address buffer 12 receives an address input from the outside and generates an address signal indicating selection of a memory cell M of the memory array 101 based on the address input. The ATD circuit 13 detects a transition of the address signal due to a change in the address signal and generates an H-level pulse-like ATD signal. The above dummy word line DWL is
It is provided in parallel with the original word line WL of the memory array 11, and is designed to be selected simultaneously with the word line WL. The dummy memory cell DM is a logic “bi” or high (H)
) level is stored and is selected by the dummy word line DWL. The dummy bit line DBL is provided in parallel with the original bit line BL of the memory array 11, and can transmit a signal representing the storage content of the dummy memory cell. The dummy sense amplifier 18 transmits a signal representing the memory contents of the dummy memory cell DM appearing on the dummy bit line DBL in synchronization with the ATD signal to the sense amplifier 18.
Sense amplification is performed with the same amplification time as 6 and output. In addition,
The output level of this dummy sense amplifier 18 is set to a low (L) level during standby. When the sense amplification is completed, the output level becomes H level according to the storage contents of the dummy memory cell DM. Inverter 19 receives the output signal of dummy sense amplifier I8, and when the ATD signal is input, inverts the output signal of dummy sense amplifier 18 (which corresponds to the APD signal when at L level) to decoder 14. It is output to the sense amplifier 16 and dummy sense amplifier 18. Note that when the ATD signal is not input, the output of the inverter 19 is at L level. When the address input from the outside changes and the ATD circuit 13 generates an ATD signal, the decoder 14 selects the word line WL and specifies the memory cell M in synchronization with the timing of generation of this ATD signal. The decoder 14 simultaneously selects the dummy word line WL and selects the dummy memory cell DM. As a result, a signal representing the storage contents of the memory cell M appears on the bit line BL, and at the same time, a signal representing the storage content of the memory cell M appears on the dummy bit line DBL.
A signal representing the memory contents of M appears. Next, the above ATD
In synchronization with the signal generation timing, the sense amplifier 16 sense-amplifies the signal representing the memory content of the memory cell M appearing on the bit line BL, and at the same time, the dummy sense amplifier 18
sense-amplifies the signal appearing on the dummy bit line DBL representing the storage contents of the dummy memory cell. The output signal of the sense amplifier 16 is read out as data through an output circuit (not shown). On the other hand, when the sense amplification is completed, the output signal of the dummy sense amplifier 18 changes from L level to H level, and is output through the inverter 19 as an L level APD signal. Here, the dummy word line DWL, the dummy bit line D
Since BL is provided in parallel with word line WL and bit line BL, respectively, it has the same parasitic capacitance as word line WL and bit line BL, respectively. Further, the dummy sense amplifier 18 performs sense amplification in the same amplification time as the sense amplifier 16. Therefore, the dummy sense amplifier 18
The timing at which sense amplification is completed for sense amplifier 1 is
This coincides with the timing at which the sense amplification of No. 6 is completed. Here, the inverter 19 generates the APD signal based on the timing at which the sense amplification of the dummy sense amplifier 18 is completed. This means that after the sense amplification of the sense amplifier 16 is completed, that is, after the data reading is completed, the APD signal can be generated much earlier than in the past. Therefore, after the data read is completed, DC current flows for a short period of time (decoder 14.
(including the sense amplifier 16 and the dummy sense amplifier 18). As a result, the period during which power is wasted inside this semiconductor memory device can be shortened, and power consumption can be reduced.

【Effect of the invention】

As is clear from the above, the present invention provides an internally synchronous semiconductor memory device with a dummy system that operates in parallel with the original data reading system and completes its operation at the same time. Since the deactivation signal generator generates the deactivation signal based on the timing of completing the operation, the deactivation signal can be generated much earlier than before after data reading is completed. I can do it. Therefore, power consumption can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional semiconductor memory device. 11...Memory array, 12. Address buffer,
13. ATD circuit, 14.. Decoder, 16.. Sense amplifier, 18.. Dummy sense amplifier, 19.
Inverter, BL...Bit line, DBL...Dummy bit line, DM...Dummy memory cell, DWL...Dummy word line, M...Memory cell, WL
...word line.

Claims (1)

[Claims] (1) When the address input transitions, the address transition detection circuit generates a pulse-like internal synchronization signal, operates the decoder in synchronization with the generation timing of the internal synchronization signal, selects the word line, and selects the memory cell. At the same time, the sense amplifier is operated in synchronization with the generation timing of the internal synchronization signal to sense and amplify the signal representing the memory contents of the memory cell transmitted to the bit line, and after the sense amplification is completed, it is deactivated. In a semiconductor memory device that inactivates a portion through which an internal DC current flows in response to a signal, a dummy word line is provided in parallel with the word line and selected at the same time as the word line, and either a logic 1 or logic 0. a dummy memory cell that stores a dummy memory cell and is selected by the dummy word line; a dummy bit line that is provided in parallel with the bit line and is capable of transmitting a signal representing the memory content of the dummy memory cell; a dummy sense amplifier that sense-amplifies and outputs a signal representing the memory content of the dummy memory cell appearing in the above-mentioned sense amplifier in the same amplification time as the above-mentioned sense amplifier; A semiconductor memory device comprising a deactivation signal generating section that generates a deactivation signal based on the timing at which sense amplification is completed.