JPH0490627A - Tuning device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of picture image quality by performing the change operation of the frequency division ratio of the frequency divider circuit of a tuner during a sample-and-hold type PLL performs hold operation. CONSTITUTION:A gate pulse from a gate pulse generator 30 is inputted to a control circuit 16. The control circuit 16 performs the change operation of a frequency division ratio N of a frequency divider 13 by the output from an automatic frequency adjusting (AFT) circuit 31 only during a sample operation period based on this gate pulse, and the AFT operation, that is, the change operation of the frequency division ratio is not performed during hold operation. Thus, the AFT operation is not performed during a sample-and-hold type phase synchronizing loop (sample-and-hold type PLL) performs hold operation, the synchronization is not stepped out during a video period and the deterioration the picture image quality can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a channel selection device used in a ghost removal device capable of removing ghost interference in a television receiver.

(Prior Art) Conventionally, in television broadcasting, as shown in FIG. 3, a direct wave s(B
, the reflected wave αS(t−τ
), which occurs when the television receiver 53 receives a broadcast signal that overlaps with other broadcast signals, has become a major problem in terms of deterioration of image quality. However, recently, a ghost removal device that removes this ghost problem has been developed, and it has been effective in improving image quality.

Such a ghost removal device 55, as shown in FIG.
A Wi-like ghost signal DSG (corresponding to S (at t-)) is created from the baseband signal SBB after axing the intermediate frequency (IF) signal SrF by a dexer 56 through a delay line 57 with a delay time τ. The coefficient circuit 58 for the coefficient α generates an amplitude-limited signal αDSG (corresponding to αS (−τ)), applies this signal αDSG to the subtracter 59, and the five subtracters generate a pseudo signal from the received signal. Ghost signal (αDSG
, ), the superimposed ghost signal αS(
−τ) is removed. Therefore, since the pseudo-ghost signal component is removed as described above, linearity in the demodulator 56 is important, and if a non-linear component occurs, the performance of ghost removal will be greatly affected. For this reason, conventionally, the demodulator 56 uses a synchronous detector with a phase-locked loop (hereinafter referred to as PLL) with good linearity, which is further improved and the loop gain band of the PLL is narrowed, or a A hold version is used.

In particular, a synchronous detector using a sample-and-hold type PLL,
It samples during the synchronization signal period when the influence of ghosts is small and holds the signal during the video period when the influence of ghosts is large, so demodulation with good linearity can be performed, so it is currently widely used as a tuning device used in ghost removal devices. has been done.

FIG. 5 is a block diagram showing an example of a channel selection device using the above-described conventional sample-and-hold PLL synchronous detector.

In FIG. 5, the channel selection device converts the frequency of a television broadcast signal received by an antenna into a video intermediate frequency signal using a tuner 110, and converts the frequency of the television broadcast signal received by an antenna into a video intermediate frequency signal SIF using a surface acoustic wave (SAW) filter 140 having a Nyquist slope. The signal is supplied to a demodulator 120, which obtains a demodulated output, and the demodulated output is supplied to a ghost removal device (not shown).

The tuner 110 is constructed using a frequency synthesizer system, and because of its excellent stability, it is used in television receivers that require high performance. tuner 110
, the output of the local oscillator 112 is divided by a frequency divider 113, this frequency is compared with the frequency of a reference oscillator 114 by a frequency comparator 115, and the oscillation frequency of the local oscillator 112 is controlled so that the two match. Therefore, the oscillation frequency of the local oscillator 112 can be controlled by changing the frequency division ratio N of the frequency divider 113. This frequency division ratio N is given a predetermined value corresponding to each broadcast frequency by a control circuit 116 composed of a microcomputer or the like.

A television broadcast signal is frequency-converted into a video intermediate frequency (IF) by a mixer 111 using a local oscillation frequency of a frequency-controlled local oscillator 112.

The output of mixer 111 is input to demodulator 120 via SAW filter 114. The demodulator 120 is called a sample-and-hold PL, L-type synchronous detector. In the demodulator 120, the video intermediate frequency signal that has been amplified to a predetermined value by a video intermediate frequency amplifier (hereinafter referred to as an IF amplifier) >121 is input to the input terminal of each of the video detector 122 and the phase detector 123. The other input terminal of the 0-phase detector 123 is connected to a voltage controlled oscillator (
Hereinafter, the output of >124, referred to as VC○, is input, and the sample and hold circuit (hereinafter referred to as S8 circuit)
126 and a low pass filter (hereinafter referred to as LPF) 1
27 constitutes a sample-and-hold type PL-L. When this PLL is locked, the phase detector 123
Since the phase difference between the two input signals is 90 degrees, the VC
When the phase difference between the signal inputted from O124 to the other input terminal of the video detector 122 and the signal passed through the phase shifter 125 is 90 degrees, the two input signals of the video detector 122 are in phase, and synchronous detection is performed. I can do it. The SH circuit 126 is composed of a switch means and a hold capacitor, and uses the output of the gate pulse generator 130 to turn the switch means on and off to switch between sample operation and hold operation. This gate pulse generator 130 receives the output of the synchronization detector 128 that detects the synchronization state of the PLL and the output of the synchronization separation circuit 129 that outputs synchronization pulses from the video signal. This means that the gate pulse generator 130 is
This means that when the PLL is in an asynchronous state, a gate pulse is always generated to perform a sample operation, and when the PLL is in a synchronous state, a gate pulse is generated from the output of the synchronous separation circuit 129 to perform a sample and hold operation. . This means that the pull-in range of the PLL during the sample and hold operation is narrower in terms of the ratio of the sample period to the hold period, compared to when the sample operation is always performed. In other words, if a sample and hold operation is performed from an asynchronous state, there is a risk that the PLL will not be able to pull in.

In addition, the output of the IP amplifier 121 is output from an automatic frequency adjustment circuit (
Hereinafter, this will be referred to as the AFT circuit. ) 131, and the output of this AFT circuit 131 is input to the control circuit 116 of the tuner 110. In addition to this, the output of the synchronous separation circuit 129 is also input to the control circuit 116 . The input of the output of the synchronous separation circuit 129 is connected to the AFT circuit 13.
This is because if the channel selection is controlled using only the output 1, there is a risk of erroneous locking to the audio carrier or the like during channel selection, and to prevent this, the control circuit 116 always checks to see if there is a synchronization pulse.

As described above, the tuner 110 uses a frequency synthesizer method, and the synchronous demodulator 12 uses a sample hold method.
According to the channel selection device consisting of 0, it is possible to perform restoration with good linearity, so that the performance of the ghost removal device 55 can be fully demonstrated, and the performance of removing ghost disturbances can be improved.

However, under actual conditions of use, there are the following problems.

That is, when the PLL is in a synchronous lock state and the input frequency and the frequency drift of the local oscillator 112 are so small that the synchronous detector 128 can be considered to be in a synchronous lock state,
The PLL will continue sample and hold operations.
On the other hand, the AFT circuit 131 always outputs the carrier frequency fluctuation of the video intermediate frequency signal to the control circuit 28116 of the tuner 110. Therefore, the control circuit 116 changes the frequency division ratio N of the frequency divider 113 of the tuner 110 in response to the output of the AFT circuit 131. The change in the oscillation frequency of the local oscillator 12 due to this change in the frequency division ratio N is approximately several 10 (KIIZ).Here,
If the PLL of the synchronous demodulator 120 is in sampling operation,
Although the PLL can adequately follow this degree of frequency change, if this frequency change occurs during the hold operation, the PLL cannot follow it at all because the PLL is off-loop. The occurrence of this strange state means that the video detector 122 cannot perform normal synchronous detection. For example, P only during the horizontal sync pulse period
Assuming that LL performs a sampling operation and the others perform a hold operation, a frequency change of 10 [KHz) results in a change of 60 [μ
Under the condition of hold period of [S], the maximum is 216 [de! I
I) phase change, and normal detection can no longer be performed.
When viewed on a video screen, this large phase change looks like a horizontally long noise extending from the middle of the screen to the right edge.

In order to solve this problem, it is possible to speed up the operation of the synchronous detector 128 so that the sampling operation starts immediately in response to the frequency deviation. If the operation 9 of the synchronization detector 128 is made to be far away, the stability of the synchronization detector 128 will be impaired. For this reason, the movie Cl
During l7UI 1m, the PLL shifts from the hold operation to the sample operation, and the PLL pull-in operation causes phase fluctuations, which impairs the quality of the screen.

(Problem M to be solved by the invention) As mentioned above, in the conventional tuning device r, normal detection cannot be performed due to the frequency drift 1~ that occurs during the hold period, and therefore a noise image is generated on the screen. This method had the disadvantage that it resulted in a significant loss of image quality. Furthermore, if the operating speed of the synchronous detector is increased in order to prevent this drawback, the stability of the synchronous detector will be impaired, resulting in a drawback of deterioration of image quality.

The present invention has been made in view of the above-mentioned points, and can prevent deterioration of image quality due to frequency drift during hold operation, does not impair the stability of the synchronous detector, and is relatively easy to use. The purpose of the present invention is to provide a channel selection device that can realize the following.

[Structure of the invention]

(Means for Solving the Problems) The present invention changes the frequency division ratio of the frequency divider circuit by a control means,
A frequency synthesizer type tuner that controls the local oscillation frequency to obtain an intermediate frequency output of a predetermined frequency, and a sample-hold type phase-locked loop synchronous detection means that obtains a demodulated output based on the intermediate frequency signal from the tuner; means for detecting a synchronization state of the phase-locked loop and switching between a sample operation and a hold operation in the phase-locked loop according to the synchronization state; detecting a variation of the intermediate frequency signal from a predetermined frequency; and a demodulator comprising an automatic frequency adjustment means that outputs an output to the control means to change the frequency division ratio, wherein only the sampling operation period of the phase-locked loop of the demodulator,
The automatic frequency J! The present invention is characterized in that means for controlling the control means is provided to cause the I11 means to change the frequency dividing ratio of the frequency dividing circuit.

(Function) In the channel selection device configured as described above, the frequency dividing ratio of the frequency dividing circuit of the tuner is not changed during the period when the synchronous demodulator using the sample-and-hold type PLL is performing the hold operation. Therefore, there is no frequency fluctuation due to the operation of the AFT circuit, and no noise-like disturbance occurs on the screen.

Furthermore, since there is no need to increase the operating speed of the synchronous detector, the stability of the synchronous detector is not impaired.

(Example) Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the channel selection device of the present invention.

The channel selection device shown in FIG. 1 frequency-converts a television broadcast signal received by an antenna ANT into a video intermediate frequency signal by a tuner 10, and converts the frequency of the television broadcast signal received by an antenna ANT into a video intermediate frequency signal S[F by using a SAW filter 40 having a Nyquis l slope. Same 1 (l1
The 1υ1 demodulator 20 obtains a demodulated output, and the 1N modulated output is supplied to a ghost l/removal device (not shown).

The tuner 10 is constructed using a frequency synthesizer system and has excellent stability. In this tuner 10, a television broadcast signal received by an antenna ANT is input to a mixer 11. A local oscillation frequency signal from a local oscillator 12 is input to the mixer 11 . The output terminal of the mixer 11 is connected to the SAW filter 4.
Connected to 0. The output of the local oscillator 12 is sent to the frequency divider 1
3. The output of the reference oscillator 14 is supplied to one input of a frequency comparator 15.

The output signal from the frequency divider 13 is supplied to the other input terminal of the frequency comparator 15. The output of the frequency comparator 15 is supplied to the local oscillator 12. The frequency divider 13
The frequency division ratio N is controlled by the control circuit 16.

The synchronous demodulator 20 is configured by a sample-and-hold PLL.
An output terminal of the amplifier 21 is connected to an input terminal of one of the video detector 22 and the phase detector 23, respectively. Also, V.C.
The output terminal from O24 is the video detector 22 and phase shifter 25.
and are connected to each other input terminal. The output terminal of the phase shifter 25 is connected to the other input terminal of the phase detector 23. The SH circuit 26 samples the signal from the phase detector 23 and supplies the sampling result to the ■C○ 24 through the LPF 27. The output terminal of the video detector 22 is connected to a ghost removal device (not shown) and a synchronization detector 2.
8. Connected to each input terminal of the synchronous separation circuit 29.
Each output of the synchronization detector 28 and the synchronization separation circuit 29 is supplied to a gate pulse generation circuit 30, and the gate pulse generation circuit 30 sends the sampling pulse to the SH circuit 26.
is supplied to. In addition, the output of the IP amplifier 21 is AFT
The output of this AFT circuit 31 is supplied to the control circuit 16 of the tuner 10. This control circuit 16 is supplied with the outputs of a gate pulse generation circuit 30 and a synchronous separation circuit 29. Note that the phase detector 23, VCO 24, phase shifter 25, SH circuit 26
, and LPF 27 constitute a sample-and-hold type PLL. The operation of the embodiment configured in this way will be explained below.

In tuner 10 , the output of local oscillator 12 is frequency-divided by frequency divider 13 and supplied to frequency comparator 15 . This frequency comparator 15 compares the frequency from the frequency divider 13 and the reference oscillation frequency from the reference oscillator 14, and controls the oscillation frequency of the local oscillator 12 to match the reference oscillation frequency.

The oscillation frequency of the local oscillator 12 can be controlled by changing the frequency division ratio N of the frequency divider 113. This frequency division ratio N is given a predetermined value corresponding to each broadcast frequency by the control circuit 16. A television broadcast signal is frequency-converted into a video intermediate frequency (IF) by a mixer 11 using a local oscillation frequency of a frequency-controlled local oscillator 12.

The output of mixer 11 is input to demodulator 20 via SAW filter 4o.

In the demodulator 20, the video intermediate frequency signal amplified to a predetermined value by the IF amplifier 21 is input to a video detector 22 and a phase detector 23. And sample hold PL
When L (23 to 27) is locked, the phase difference between the two input signals of the phase detector 23 is 90 degrees, so ■
When the phase difference between the signal input to the other input terminal of the video detector 22 and the signal passed through the phase shifter 25 is 90 degrees, the two input signals of the video detector 22 are in phase. Then, synchronous detection is performed.

Further, this gate pulse generator 30 determines whether the PLL is in an asynchronous state based on a signal from a synchronization detector 28 that detects the synchronization state of the PLL and a signal from a synchronization separation circuit 29 that separates synchronization pulses from the video signal. SH circuit 2
Supply to 6. This SH circuit 26 performs a sample operation and a hold operation using this gate pulse.

Furthermore, the gate pulse from the gate pulse generator 30 is input to the control circuit 16. The control circuit 16 controls the AF only during the sampling operation period based on this gate pulse.
The frequency division ratio N of the frequency divider 13 is changed by the output from the T circuit 31, and during the hold operation, the AF is
The T operation (that is, the operation of changing the frequency division ratio) is not performed.

By operating in this way, the sample-and-hold type PLL
Since the AFT operation is not performed during the hold operation, synchronization will not be lost during the video period, and deterioration of video quality can be prevented.

Furthermore, since the synchronization detector 28 is the same as the conventional one, there is no deterioration in stability at all.

FIG. 2 is a block diagram showing another embodiment of the invention.

In another embodiment shown in FIG. 2, the output of the AFT circuit 31 is input to the control circuit 16 via a switch 32, and the switch 32 is controlled to be turned on and off by the gate pulse from the gate pulse generator 30. It's Nishidarano. This is because, in the embodiment of FIG. 1, the operation of not performing the AFT operation during the period when the sample-and-hold type PLL is performing the hold operation is processed by software using a program by the control circuit 16. On the other hand, this means that the switch 32 is used and processing is performed by hardware.

With this configuration, the switch 32 is turned off by the gate pulse from the gate pulse generator 30 during the period when the sample-and-hold type PLL is performing the hold operation, and the output from the AFT circuit 31 is sent to the control circuit 16. It will no longer be input.

As a result, the control circuit 16 does not perform the AFT operation during the hold operation, and the switch 32
is turned on only when there is an output corresponding to the sampling operation of the gate pulse generator 3o, and transmits the output of the AFT circuit 31 to the control circuit 16.

In the embodiment shown in FIG. 2 above, the configuration other than the above is the first one.
This embodiment is exactly the same as the embodiment, and therefore the operations other than those described above are also exactly the same.

In this way, in the embodiment shown in FIG.
It is exactly the same as the figure, and therefore the same effect as in FIG. 1 can be obtained.

In each of the above-mentioned embodiments, the conventional circuit can be used as is, and there is almost no increase in new circuitry, so it can be realized at a low cost. Furthermore, according to this embodiment, this function can be achieved by only making slight changes to the wiring and the control circuit program, so that it does not adversely affect the performance of other circuits.

Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, the present invention is not limited to the above-mentioned embodiments.
It is possible to use various things such as the gain control (AGC) voltage of the F amplifier to improve the reliability and responsiveness of the operation, but in short, it is a sample-and-hold type PLL.
Any device that performs the AFT operation of the tuner only during the sample operation period is included in the present invention.

〔Effect of the invention〕

As described above, according to the present invention, the AFT operation is not performed during the hold operation and no synchronization loss occurs due to this, so the image quality does not deteriorate.

Further, according to the present invention, there is almost no increase in the number of parts, only slight changes in wiring and control circuit (microcomputer) programs are required, and other circuit functions are not affected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the channel selection device of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG.
4 is a block diagram illustrating a ghost removal device, and FIG. 5 is a block diagram illustrating a conventional channel selection device. 10... Tuner, 11... Mixer, 12... Local oscillator, 13... Frequency divider, 14... Reference oscillator,
15... Frequency comparator, 16... Control circuit, 2o.
...Demodulator, 2.. Image filtration detector, 23.. Phase detector, 4.. VCO125... Phase shifter, 6.. Sample hold circuit, 7.. Low pass filter, 8.. ...Synchronization detection circuit, 0.Gate pulse generator, 1..Automatic frequency adjustment circuit, 32.Switch.

Claims (1)

[Scope of Claims] A frequency synthesizer-type tuner that changes the frequency division ratio of a frequency divider circuit by a control means and thereby controls the local oscillation frequency to obtain an intermediate frequency output of a predetermined frequency; A synchronous detection means using a sample-and-hold phase-locked loop that obtains a demodulated output based on a frequency signal, and a means for detecting a synchronous state of the phase-locked loop and switching between a sample operation and a hold operation in the phase-locked loop according to the synchronous state. and a demodulator comprising automatic frequency adjustment means that detects a variation of the intermediate frequency signal from a predetermined frequency and outputs the variation to the control means in order to change the frequency division ratio. In, only the sampling operation period of the phase-locked loop of the demodulator,
A channel selection device comprising means for controlling the control means to cause the automatic frequency adjustment means to change the division ratio of the frequency division circuit.