JPH0497277A - Halftone display driving method for solid-state display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention slows down the rise of a pulse voltage applied to a pixel forming electrode provided on an electro-optic crystal plate, and also displays halftones by changing the pulse width. The present invention relates to an improvement in a halftone display driving method for a solid-state display device.

[Prior Art] Generally, in this type of solid-state display device, polarizing plates are provided on both sides of a PLZT plate serving as an electro-optic crystal plate so that the polarization directions are perpendicular to each other, and polarizing plates are provided between pixel forming electrodes fixed to the PLZT plate. Depending on whether or not to apply pulse voltage from the drive circuit,
A predetermined display was performed by controlling whether or not incident light was transmitted through the polarizing plate, the PLZT plate, and the polarizing plate. Here, the PLZT plate is PLZ which is an electro-optic ceramic.
T (e.g. (Pbo-, 1La0.os) (Zro,
5sTlo-as)03).

Since the PLZT board has a large capacitance, this PLZT board has a large capacitance.
If a pixel forming electrode is provided on the ZT board and an attempt is made to display halftones by changing the pulse width of the pulse voltage applied to the pixel forming electrode, an excessive current will flow at the moment the pulse voltage is applied, so the power supply It is necessary to increase the current capacity, and it is also necessary to increase the withstand current capacity of the switching element of the drive circuit. In order to avoid this, conventionally, a rise-slowing circuit is used to slow the rise of the pulse voltage (corresponding to A7 in the halftone display) as shown in Figure 4(a), so that the rise of the pulse voltage as shown in Figure 4(b) is slowed down. By creating a pulse voltage and applying it to the pixel forming electrode, excessive rising current is prevented from flowing. In Fig. 4, T represents the display period (lighting period), t□, t
z (=2t) and t4 (=4t1) are weighted 1.2
．． 4 represents the pulse width of the pulse.

[Problems to be Solved by the Invention] However, in the method of slowing down the rise of the pulse voltage as shown in FIG. There was a problem that the intensity (that is, display brightness) could not be obtained. In other words, the relationship between the pulse width W of the pulse voltage and the transmitted light intensity maintains the linearity as designed as shown by the solid line P in Fig. 5 when the rise is not slowed down. Therefore, when the rise was slowed down, it deviated from the design value as shown by the dotted line Q in FIG. 5, and linearity could not be maintained. In particular, when the pulse aW was as small as 1.2.3, . . . 8, the degree of deviation from the design value was large.

The present invention has been made in view of the above-mentioned problems, and is designed to obtain transmitted light intensity as designed when the rise of the pulse voltage for halftone display is slowed down to prevent excessive current. The object of the present invention is to provide a method for driving halftone display of a solid-state display device.

[Means for Solving the Problems] A halftone display driving method for a solid-state display device according to the present invention slows down the rise of a pulse voltage applied to a pixel forming electrode provided on an electro-optic crystal plate, and In the method for driving a halftone display of a solid state display device in which a halftone display is performed by changing the pulse width of a solid-state display device, an amount corresponding to the pulse width reduced due to a slowing of the rising edge of the pulse voltage is added to the pulse voltage. This is a characteristic feature.

[Function] When applying a pulse voltage for halftone display to the pixel forming electrode, the rise of this pulse voltage is slowed to prevent excessive current, but an amount equivalent to the pulse width reduced by this slow rise is added. Therefore, the intensity of transmitted light through the electro-optic crystal plate has a designed value that is proportional to the pulse width of the pulse voltage.

[Embodiment] Figs. 1 to 3 show one embodiment of the present invention, and in these figures, the same parts as in Figs. 4 and 5 are given the same reference numerals. In FIG. 1, 10 is a pulse generating circuit, and from the output side of this pulse generating circuit 10, as shown in FIG.
) to (e), pulse voltages A1, A2, A1 with pulse widths of 1.2.3,...7, -, n (for example, n is 128) within the display period (lighting period) T ,...,A7
,...,A is outputting. 12 is a rising edge slowing circuit, and this rising edge slowing circuit 12 is configured to control the pulse voltage A, .
A2, A3, . . . , A7, .
The pulse voltage B7 shown in FIG. 7B is output by blunting the rising edge of the waveform B7. The same applies to the other pulse voltages A1, A2, A3, . . . An. 14 is a rise time correction circuit, and this rise time correction circuit 14 is configured to adjust the pulse voltages B□, B2, B3, . . . , B7, .
It is configured to add an amount α corresponding to the pulse width reduced by the slowing of the rising edge slowing circuit 12 to n and output the resultant signal. For example, for pulse voltage B7,
) is configured to output the pulse voltage C7 shown in FIG. 2C, which is obtained by adding a certain time α (for example, α=t) to the pulse width of each of the pulses constituting the pulse voltage B7. Other pulse voltages B1, B2, B3,...B,
The same applies to 16 is an A/D (analog/digital) conversion circuit that converts a video signal into a digital signal and outputs the digital signal. 18 is a switching circuit, and this switching circuit 18 is sequentially connected to 8 from the A/D conversion circuit 16.
Pulse voltages C,, C2, C3, . . . , C7 output from the rise time correction circuit 14 based on the input signal.
, ..., Cn, select the corresponding pulse voltage from output signal line O, 02.03, ..., ○, (for example, m is the number of rows or columns of matrix display pixels). A pixel forming electrode (not shown) of a PLZT plate (not shown) as an electro-optic crystal plate is connected via a corresponding output signal line.
is configured to supply. The PLZT board is
PLZT, which is an electro-optic ceramic (e.g. (pbo
.

qlLa. , +19) (ZrO-cs Tlo -35
)03).

When displaying halftones, as described above, the rising portion of the pulse voltage waveform is blunted by the rising edge slowing circuit 12, and the rise time correction circuit 14 adds an amount α corresponding to the pulse width reduced by this rising edge slowing. Since it is supplied to the pixel forming electrodes of the PLZT board, it is possible to prevent excessive current from flowing and to obtain the transmitted light intensity (ie, display brightness) as designed.

In the embodiment described above, in order to simplify the configuration of the rise time correction circuit, the pulse widths t1, t2, and t of the pulses with different weights constituting the pulse voltage for halftone display are changed.
By adding the same pulse width α to 4,... and setting this pulse width α to the time t when the pulse width W is 1,
Although the pulse width equivalent to the substantial reduction due to the slowing of the rise is compensated for, the present invention is not limited to this.
Any method may be used as long as it adds an amount equivalent to the pulse width reduced due to the slowing of the rise of the pulse voltage to compensate for the amount equivalent to the pulse width substantially reduced due to the slowing of the rise. for example,
Pulse widths α□, C2, αi, etc. corresponding to the respective pulse widths t, t2, t, etc. of pulses with different weightings constituting the pulse voltage for halftone display are added. Good too.

[Effects of the Invention] As described above, the halftone display driving method for a solid-state display device according to the present invention slows down the rise of the pulse voltage applied to the pixel forming electrode, and reduces the pulse width by an amount equivalent to the pulse width reduced by this slow rise. is added to compensate for the substantial decrease in pulse width, so it is possible to prevent excessive current from flowing when a pulse voltage is applied to the pixel forming electrode for halftone display, and also to prevent the electric current from flowing. The transmitted light intensity (that is, display brightness) of the optical crystal plate can be set to a designed value that is proportional to the pulse width of the pulse voltage.

[Brief explanation of the drawing]

1 to 3 show an embodiment of the halftone display driving method for a solid-state display device according to the present invention, and FIG. 2
The figure is an output waveform diagram of the pulse generation circuit in Figure 1, Figure 3 is an output waveform diagram of each part in Figure 1, Figure 4 is a waveform diagram of the pulse voltage applied to the pixel forming electrode of the conventional example, FIG. 5 is a characteristic diagram showing the relationship between the pulse width of the pulse voltage and the transmitted light intensity (display brightness). 10... Pulse generation circuit, 12... Rise slowing circuit, 14... Rise time correction circuit, 16... A/D conversion circuit, 18... Switching circuit, ■... Transmitted light intensity, T...display cycle (lighting cycle), t□, t2, t
4...Pulse width of weighted pulses constituting pulse voltage, W...Pulse width of pulse voltage, pulse width equivalent for α. Compensate for slow rise

Claims (2)

[Claims] (1) Slowing down the rise of the pulse voltage applied to the pixel forming electrodes provided on the electro-optic crystal plate,
In the method for driving a halftone display of a solid state display device in which a halftone display is performed by changing the pulse width of the pulse voltage, an amount equivalent to the pulse width reduced due to a slow rise of the pulse voltage is added to the pulse voltage. A method for driving a halftone display of a solid-state display device, characterized in that: (2) Claim in which the electro-optic crystal plate is a PLZT plate (
1) Halftone display driving method of the solid-state display device described above.