JPH0497633A - Serial data receiver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a serial data receiving device suitable for receiving serial data with extremely poor S/N ratio, such as wireless data communication using weak radio waves.

2. Description of the Related Art As a conventional serial data receiving device of this type, for example, a receiving device using an asynchronous method is well known.As shown in FIG. The configuration is such that sampling is input near the center of the bit (C+, Cz, Cs...) after a delay time of .

Problems to be Solved by the Invention However, with the configuration of such a conventional serial data receiving device, it is impossible to establish bit synchronization in communication under a poor S/N situation where noise is frequently introduced.

In particular, in serial data communication using weak-level radio waves that satisfy the weak-level radio wave regulations, which have recently become popular for commercialization, such conventional configurations are impractical because the environment is extremely noisy. Not on point.

Furthermore, in order to solve such problems, conventional noise filters and PLL circuits, which are a type of filter, are often used. In the first place, a filter has the function of separating signals in terms of frequency, so in order to suppress noise, it is necessary to separate the noise frequency from the data transmission frequency, that is, the baud rate, and to do this, the data transmission speed is usually slowed down. In particular, when a PLL circuit is used, the cost is high, making it impractical to apply it to home appliances and the like.

The present invention solves such conventional problems, and provides a practical serial data receiving device at low cost that can achieve reliable bit synchronization and receive correct data even if the serial data is somewhat noisy. With the goal.

Means for Solving the Problems In order to solve the above problems, the serial data receiving device of the present invention divides the 1-bit length of the bit synchronization preamble signal composed of biphase codes by 2n (n is a natural number). A multi-point sampling input means for inputting multi-point sampling for each block, with each section as one block, and a logic value of 1'' in the block based on the sampling input data obtained by the multi-point sampling input means. 0", "undefined", and a permutation pattern of each block logic value from block 1 to block 2n obtained by the block logic determining means to determine the input bit synchronization value. The device is equipped with a bit synchronization establishing means for determining the phase relationship between the preamble signal and the block number and establishing bit synchronization.

Further, in another serial data receiving device of the present invention,
The block logic determining means uses the sampling input data in the first (an integer of 1≦i≦n) obtained by the multi-point sampling input means and the (n+i
) Based on the sampled manual data of the block, the bit synchronization establishment means performs a logical judgment on the first block based on the sampled manual data of the block, and the bit synchronization establishing means evaluates the logical values of each block from block 1 to block n obtained by the block logic judgment means. This device is configured to determine the phase relationship between the input preamble signal for bit synchronization and the block number from the permutation pattern, and establish bit synchronization.

Further, in another serial data receiving device of the present invention, the multi-point sampling input means is configured to perform multi-point sampling input processing for each block over a plurality of bits of the bi-sto synchronization preamble signal, A block data accumulation means is provided for accumulating the number of logic 1 (or logic 0) for the latest predetermined bits of the sampling input data of the same block number in each synchronization bit, and the block logic judgment means is configured to accumulate the accumulated data for each block. The block is configured to perform logical judgment on the block based on the above.

Further, in another serial data receiving device of the present invention, the block logic determining means calculates the accumulated data in the i-th (an integer of 1≦i≦n) block obtained by the pro-nk data accumulating means and the ( A logic judgment is made in the first block based on the accumulated data in the n+i)th block, and the bit synchronization establishing means determines each logic value from block 1 to block n obtained by the block logic judgment means. The block number is configured to determine the phase relationship between the input preamble signal for bit synchronization and the block number from the permutation pattern of , and establish bit synchronization.

Effect of the present invention With the above-described configuration, when a bit synchronization preamble signal composed of a biphase code is received, the multi-point zumbling input means inputs one of the preamble signals.
An interval obtained by dividing the bit length by 2n (n is a natural number) is defined as one block, and data sampling is input for each block. Therefore, 2n pieces of sampling input data are obtained per 1 bit of the preamble signal. Next, the block logic determining means determines whether the logic 1 or logic 0 constituting the input data is a logic 1 or a logic 0 for each of the 2n sampling input data.
, and from that value, the overall logic in the block is 1'', 0'.

It is judged as “undefined”.

Then, the bit synchronization establishing means derives the phase relationship between the input preamble signal and the serial number from the permutation pattern of the 2n block logical values obtained by the block logic determining means, and determines the phase relationship between the input preamble signal and the serial number, Establish bit synchronization for the reception of serial data.

In addition, when a pi-phase code is used as a preamble signal, by utilizing the fact that the logics in the i-th (integer 1≦i≦n) and (n10i)-th blocks are opposite to each other, both More accurate block logic judgment can be made using block data.

In addition, by continuously performing multi-point sampling for several bits of the preamble signal and integrating the data for each bit with the same block number, more accurate block logic can be calculated from the obtained integrated data. Can judge.

In addition, the block logic can be made even more accurate by using both the symmetry effect of the i-th and (n+i)-th block data by bi-phase coding and the overwriting effect by integrating the same bits of the preamble signal. Can judge.

Embodiments Hereinafter, embodiments of the present invention will be described based on the accompanying drawings. FIG. 1 is a block diagram of a serial data receiving apparatus according to an embodiment of the present invention.

Reference numeral 1 denotes an FM receiver, which uses an antenna 1a to capture a bit synchronization preamble signal having a biphase code structure and the following data signal, which have been FM-modulated and transmitted from a serial data transmitter provided separately, and transmit the original data signals. It is demodulated into a baseband format serial data signal 2. An example of the serial data is shown in FIG. 2, where A is a bit synchronization preamble signal section and B is a data signal section. or,
The preamble signal is composed of a biphase code in which section T in the figure is one bit.

3 is a multi-point sampling input means, which is composed of a shift register 4, a shift clock generator 5, a shift clock counter 6, and the like. The serial data signal 2 is sampled and input to the shift register 4 in synchronization with the shift clock signal 7 output from the shift clock generator 5. The shift clock counter 6 is configured to output a shift input completion signal 8 when the shift clock signal 7 reaches the number of stages in the shift register 4.

The shift clock generator 5 appropriately divides the original oscillation frequency generated by the crystal oscillator 9, etc. to create the period Δt of the shift clock signal, and generates/stops the shift clock signal under shift clock control from the CPU 12, etc. Controlled by signal 10. That is, the CPU 12 can enable the shift clock generator 5 using the shift clock control signal 10, generate the shift clock signal 7, and start reception processing. Thereafter, when the shift input completion signal 8 is input, the CPU 12 determines that the multi-point sampling input is completed and reads the sampling input data signal 11 from the shift register 4.

FIG. 3 is a timing diagram showing the operation of the multi-point sampling input means 3. In the same figure, (a) shows the preamble signal part of the serial data signal 2, and (b) shows the shift clock signal 7.
, (C) shows the shift input completion signal.

In this embodiment, the number of stages of the shift register 4 is 8, and when the shift clock signal 7 is emitted 8 times, the shift input completion signal 8 is generated.
This configuration is such that a shift input completion signal is output six times for one bit of a preamble signal.

That is, one bit of the preamble signal is divided into six blocks, and eight sampling points of input data are taken for each block and taken into the CPU 12. for example,
The sampling input data of block l is B' 0000
0000° and B'0001111 in block 2
1'', and in block 3 it is B'11111111'.

In FIG. 1, 13 is a data memory, and the cp
The sampling input data fetched from the shift register 4 by u12 is organized and stored for each bit number and each block number.

Reference numeral 14 denotes a data conversion means, which calculates the number of logical 1's or logical 0's constituting the captured sampling input data. For example, in the case of input data B'00011111', the number of logical 1's is 5 (the number of logical O's is 3), and so on.

The data memory 13 may store the sampling input data taken in from the shift register 4 as is, or may store data converted into a number of logic 1s (or logic 0s) by the data conversion means 14. Good too.

Next, reference numeral 15 denotes block logic determining means, which determines the logic of the block based on the number of logical l (or logical 0) of the human data for each block obtained by the data converting means 14. This can be easily achieved through microcomputer program processing. Table 1 shows an example of logical judgment specifications.

(Leaving space below) Table 1 Further, 16 is a bit synchronization establishing means, which uses the input preamble signal and block number from the permutation pattern of logical values from block l to block 6 determined by the block logic determining means 15. This method determines the phase relationship between the two bits and establishes the bit synchronization timing. This can also be easily achieved through microcomputer program processing. Table 2 shows the specifications of the logical value permutation pattern and phase relationship, and FIG. 4 shows its timing diagram.

Note that ΔT in FIG. 4 indicates the allowable error of bit synchronization timing.

Table 2 17 is a block data accumulating means that accumulates the number of logic 1s (or logic O) of sampling input data of the same block number for each bit number stored in the data memory 13. .

However, the bits to be accumulated are counted from the latest bit number and are constantly updated, for example, by 10 bits. In this way, by adding several bits of sampled input data of the preamble signal in the same phase, it becomes resistant to isolated noise and enables stable bit synchronization.

Next, another embodiment of the present invention will be described. By using a high-phase code as a preamble signal, as shown in FIG. The input data in the block becomes the same data in an ideal state if the logic is reversed.

Therefore, another block logic determination means 15 of the present invention is configured to perform block logic determination by correlating the data in the first block and the (n+i)th block data with each other. Table 3 shows an example of the logical judgment specifications. However, 2n is the number of block divisions (
n is a natural number), and 1 is a regularity satisfying l≦l≦n.

Table 3 Table 4 A 0 or an x mark indicates indeterminacy.

Further, another embodiment of the block logic determining means 15 includes a configuration in which the block is determined based on the sum of the first block data and the inverted value of the (n+i)th block data. Table 4 shows the specification for determining the phase relationship between the permutation pattern and the preamble signal based on the block logic value in relation to FIG.

Furthermore, if a logical judgment is made based on the first block data and the (n+i)th block data of the latest predetermined bits of accumulated block data obtained by the block data accumulating means 17, very high accuracy and high stability can be achieved. bit synchronization can be established.

In the embodiment described above, one bit of the preamble signal is
Although the case is shown in which the blocks are divided into 2 blocks, the present invention is of course not limited to this, and in general, the blocks are divided into 2n blocks (n is a natural number).

Further, although the multi-point sampling means has been described using a shift register or a shift clock generator, the present invention is not limited to this. Means for sampling input is also possible.

Effects of the Invention As described above, according to the serial data receiving device of the present invention, the following effects can be obtained.

(1) Multi-point sampling is input for each unit block in which the 1-bit length of the preamble signal is divided into 2n pieces (n is a natural number), and after logical judgment is made for each block, block 1
By deriving the phase relationship between the preamble signal and the block number from the logic value arrangement pattern of block 2n, even if there is some noise in each block, as long as the logic judgment value in the block does not change. Bit synchronization can be achieved without any problems.

In addition, even if there is enough noise to change the logic judgment value in a certain block, it is possible to infer the correct phase relationship by analogy using the symmetry of the biphase code, making the bits extremely resistant to noise. This is a synchronization method.

(2) By using a biphase code as a preamble signal, the i-th (an integer of 1≦i≦n) and the
Since the (n+i)th data can ideally be treated as the same data by inverting their logics, more accurate flock logic judgment can be made with fewer preamble signals.

(3) Multi-point sampling is performed continuously for several bits of the preamble signal, the data is accumulated for each same block number of each via, and the block logic is judged based on the accumulated data. It is resistant to noise and enables stable bit synchronization.

(4) Furthermore, the i-th and (
The symmetry effect of the n+i)th block data,
By using a configuration that uses both the overwriting effect by integrating the same bit portion of the preamble signal, it is possible to provide a serial data receiving device with a simple configuration and low cost that is capable of bit synchronization with higher precision and higher stability.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a serial data receiving device according to an embodiment of the present invention, FIG. 2 is a partial signal waveform diagram of the same device, FIG. 3 is a partial operation timing diagram of the same device, and FIG. Another part of the operation timing chart of the same device, FIG. 5 is a part of the operation timing diagram of the conventional example. 3...Multi-point sampling input means, 12...
... cpU, 13... Data memory, 14.
. . . Data conversion means, 15 . . . Block logic determination means, 16 . . . Bit synchronization establishment means,
17...Block data accumulation means. Name of agent: Patent attorney Shigetaka Awano

Claims (4)

[Claims] (1) Multi-point sampling for inputting multi-point sampling in each block, where one block is defined as an interval obtained by dividing the 1-bit length of the bit synchronization preamble signal composed of a bi-phase code by 2n (n is a natural number) and block logic determining means for determining a logical value in the block as "1", "0", or "indeterminate" based on the sampling input data obtained by the input means and the multi-point sampling input means. , determines the phase relationship between the input preamble signal for bit synchronization and the block number from the permutation pattern of the logical values of each block from block 1 to block 2n obtained by this block logic determination means, and establishes bit synchronization. A serial data receiving device equipped with means for establishing bit synchronization. (2) The block logic determining means selects the sampling input data in the i-th (integer of 1≦i≦n) obtained by the multi-point sampling input means and the (integer of 1≦i≦n)
Based on the sampling input data in the n+i)th block, a logic judgment is made in the i-th block, and the bit synchronization establishing means determines the logic value of each block from block 1 to block n obtained by the block logic judgment means. 2. The serial data receiving device according to claim 1, wherein the serial data receiving device is configured to establish bit synchronization by determining the phase relationship between the input preamble signal for bit synchronization and the block number from the permutation pattern. (3) The multi-point sampling input means is configured to perform multi-point sampling input processing for each block over multiple bits of the bit synchronization preamble signal, and also to perform multi-point sampling input processing for each block over multiple bits of the preamble signal for bit synchronization, and also to perform multi-point sampling input processing for each block over multiple bits of the preamble signal for bit synchronization. Logical 1 (or logical 0) for the latest predetermined bits
Provide block data integration means for integrating the number of
2. The serial data receiving device according to claim 1, wherein the block logic determining means is configured to determine the logic of the block based on the integrated data for each block. (4) The block logic determining means determines the i-th (integer of 1≦i≦n) obtained by the block data accumulation means.
The bit synchronization establishing means performs a logic judgment on the i-th block based on the integrated data in the block and the integrated data in the (n+i)th block, and the bit synchronization establishing means performs a logical judgment on the i-th block based on the integrated data in the block 1 obtained by the block logic judging means. The serial data according to claim 3, wherein the phase relationship between the input preamble signal for bit synchronization and the block number is determined from the permutation pattern of each logical value up to block n, and bit synchronization is established. Receiving device.