JPH0498374A - pattern recognition device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus that detects a target object from an image signal from an image sensor and performs pattern recognition such as positioning.

2. Description of the Related Art Conventionally, this type of pattern recognition apparatus performs recognition by applying pattern matching to a grayscale image obtained by converting an image from an image sensor such as a television camera into a multivalued image.

FIG. 5 is a block diagram showing the configuration of a conventional pattern recognition device.

In FIG. 5, a television camera 31 obtains an image of an object to be recognized and supplies it to an A/D converter 32. The A/D converter 32 converts the input image signal into a digital value and inputs it to the frame memory 33. The frame memory 33 stores the input binary input image for one screen. Further, in the conventional device, the standard pattern memory 34 cuts out an area of, for example, 16×16 pixels and stores it as a standard pattern. Cutout address generation circuit 3
5 sequentially generates cutting addresses for determining areas to be compared with the standard pattern in the input image of the frame memory 33. The cutout address from the cutout address generation circuit 35 is added to the sweep address from the sweep address generation circuit 36 in an adder 37, and is given to the frame memory 33 as a frame memory read address. This sweep address generation circuit 36 has a 16X1
A sweep address is generated for a six-pixel area, and this signal is supplied to the standard pattern memory 34 as a standard pattern memory read address.

Reference numeral 38 is a mismatch degree calculation circuit, and the mismatch degree calculation circuit 38 compares the input image outputted from the frame memory 33 and the standard pattern image outputted from the standard pattern memory 34, and outputs the degree of mismatch as the mismatch degree. , to the accumulator 39. This accumulator 39 is reset before the sweep address generation circuit 36 starts sweeping, and sweeps the degree of mismatch between the input image and the standard pattern image output from the degree of mismatch calculation circuit 38 in an area of 16 x 16 pixels. It is accumulated and held as an evaluation value.

The output of this accumulator 39 is input to a minimum value holding circuit 40. The minimum value holding circuit 40 resets the minimum value of this circuit before the cutting address generation circuit 35 starts cutting out the input image, and the output of the accumulator 39 is reset every time the sweep of the 16×16 pixel area is completed. The evaluation value held by the circuit 41 is compared with the minimum value held by this circuit, and if the evaluation value is smaller, the minimum value is replaced with the evaluation value, and a replacement pulse indicating the replacement is cut out and the address holding circuit 41
Output to. The extraction address holding circuit 41, when the replacement pulse from the minimum value holding circuit 40 is input,
This circuit stores the cutout address generated by the cutout address generation circuit 35 at that time.

The operation of such a conventional pattern recognition device will be explained.

In FIG. 5, a standard pattern memory 34 uses a portion of the shape to be recognized that captures features as a standard pattern from a digital input image obtained by operating a television camera 31, an A/D converter 32, and a frame memory 33. Let me remember it.

The following recognition operations consist of a first large loop operation that finds the minimum evaluation value while changing the extraction address of the frame memory 33, and a first large loop operation that calculates the evaluation value while sweeping the binary image memory read address and standard pattern memory read address. The desired second is divided into small loop operations. Here, the second loop operation is included in the first loop operation.

First, prior to the first large loop operation, the extraction address generation circuit 35 sends a minimum value reset to the minimum value holding circuit 40 to set the minimum value to a large value.

Next, a first large loop operation is entered, and the cutout address output from the cutout address generation circuit 35 is set to "8" in the X direction.
”, the minimum value of the evaluation is determined while sweeping the rectangular area of r8J in the Y direction.

An accumulator reset signal is output from the sweep address generation circuit 36 for one of the extracted addresses in the first large loop, and the evaluation value of the accumulator 39 is set to zero.

Next, a second small loop operation is entered, and the sweep address generation circuit 36 generates a sweep address to sweep a 16×16 area. This sweep address becomes the standard pattern memory read address, starting from the address indicating the upper left corner pixel of the standard pattern,
The standard pattern is output one after another so as to sweep a 16×16 area. The sweep address is added to the cutout address output from the cutout address generation circuit 35 in the adder 37 and becomes a frame memory read address of the frame memory 33. The frame memory read address is
First, starting from the cutout address of the input image, the data is output one after another so as to sweep a 16×16 area with this address as the upper left corner. The frame memory read address is sent to the frame memory 33 and determines the read address of the input image stored in the frame memory 33. The input image read out from the frame memory 33 as described above is sent to the mismatch degree calculation circuit 38.

On the other hand, the standard pattern read address is sent to the standard pattern memory 34, and the standard pattern image stored in the standard pattern memory 34 is read out. This standard pattern image is sent to the mismatch degree calculation circuit 38. The degree of mismatch between the corresponding pixels of the frame memory 33 and the rough input image and the standard pattern image is calculated, and the result is sent to the accumulator 3.
Sent to 9th. The accumulator 39 sweeps the 16×16 area of the frame memory 33 and the standard pattern memory 34 according to the instructions from the sweep address generation circuit 36, and calculates the -
The outputs from the mismatch calculation circuit 38 are added for each pixel.

16X of frame memory 33 and standard pattern memory 34
When the sweep of the 16 areas is completed, an evaluation value is obtained in the accumulator 39, and this value is sent to the minimum value holding circuit 40. In the minimum value holding circuit 40, the sweep address generation circuit 36
The evaluation value and the minimum value are compared based on the evaluation strobe signal from the address holding circuit 41, and when the evaluation value is smaller, the minimum value is replaced with the evaluation value and the replacement pulse is extracted.
Output to. This cutout address holding circuit 41 stores the cutout address from the cutout address generation circuit 15 when the replacement pulse is input.

16X of frame memory 33 and standard pattern memory 34
The second small loop operation for sweeping the 16 areas is completed, and then the evaluation strobe signal completes the comparison between the evaluation value and the minimum value, and the extraction address output from the extraction address generation circuit 35 is set as the next value. Continue execution of the first big loop. When the extraction address output by the extraction address generation circuit 35 sweeps the rectangular area where X and Y are respectively "8", the first large loop operation is completed, and the minimum evaluation value and the obtained XXY The value is determined and the target recognition operation is completed.

Problems to be Solved by the Invention However, the conventional recognition device described above sweeps a rectangular area where each cutout address X1Y is "8" (8 x 8 times).
However, since the 16x16 area of the standard pattern memory is swept, the total number of times the mismatch degree is processed is 16x16x8x.
8 times, because the mismatch degree calculation circuit calculates the product of the number of pixels of the cut rectangular area and the number of area pixels of the standard pattern memory, the number of times the mismatch degree calculation process is extremely large, and There is a problem in that the total time for the degree calculation process, that is, the recognition time becomes extremely long.

SUMMARY OF THE INVENTION An object of the present invention is to provide an excellent pattern recognition device that can solve the above-mentioned problems and reduce the recognition time without reducing the resolution of the recognition position.

Means for Solving the Problems In order to achieve the above object, the present invention provides input image processing means for digitizing an image signal obtained from an image sensor to obtain a digital image and storing the same in a frame memory; A standard pattern memory stores an input digital image as a standard pattern, and at the time of recognition, a pattern to be recognized is cut out from the input image processing means based on a cutout address, and the pattern to be recognized is divided into a plurality of groups each consisting of a plurality of pixels. , the cutout that minimizes the evaluation value obtained by adding up the degree of discrepancy between the representative value of each group and the representative value of the group corresponding to the recognized pattern of the standard pattern read from the similarly divided standard pattern memory, for all groups. The first means of obtaining addresses in groups,
The degree of mismatch between each pixel of the recognized pattern and the corresponding pixel of the standard pattern is added for all pixels, and the cutout address that gives the smallest evaluation value of the addition result is determined by the first method. It is provided with an address and a second means for determining the address for each pixel from among all the several pixels including the address and its vicinity.

Operation The present invention has the following effects due to the above-described configuration. That is, in the present invention, by the first means, an input image is divided into a plurality of groups each consisting of a plurality of pixels, and the minimum evaluation value in each group with respect to a similarly divided standard pattern and the cutout in each group are determined. After determining the position, the second means determines the minimum evaluation value in pixel units with respect to the standard pattern corresponding to the input image and the cutout position of the input image.

As a result, without reducing the resolution of the minimum recognizable pixel (recognition position), the product of the number of pixels in the cutout rectangular area S and the number of area pixels in the standard pattern memory, P, can be calculated as the square of the number of pixels G constituting the group. The recognition time is determined by the number of times of mismatch calculation processing Nb, which is equal to the product of the number of area pixels P of the standard pattern memory, the number G of pixels composing a group, and the number F of neighboring groups, added to the divided quotient. Since it can be recognized, it is possible to find the position of a pattern most similar in shape to a standard pattern containing grayscale information collected in advance from within an input image in a short recognition time. That is, regarding the pattern recognition time of the present invention compared to the conventional pattern recognition time, if the number of times of mismatch calculation is N1, the number of pixels in the cutout area is S, and the number of pixels in the standard pattern area is P, then the number of times Na of the conventional mismatch degree calculation is: Na=SXP. Further, when the number of group constituent pixels is G and the number of neighboring groups is F, the number of times Nb of mismatch degree calculation according to the present invention is Nb=C(SXP)/G)+PXGXF.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of a pattern recognition device according to an embodiment of the present invention.

In FIG. 1, a pattern recognition device 1 includes an input image processing means 2, a standard pattern memory 3, a first means 4,
and second means 5.

Here, the input image processing means 2 digitizes an image signal obtained from a television camera 11, which is an image sensor, using an A/D converter 12 to create a digital image, and stores this in a frame memory 13. The binary standard pattern memory 3 stores a binary standard pattern obtained by cutting out the input digital image as a standard pattern in advance and binarizing this standard pattern at a predetermined binarization level. During recognition, the first means 4 includes a standard pattern memory 3 configured by switching the switches 25a to 25e to the rBJ side, a data compression circuit 19 to be recognized, a standard pattern compression circuit 20, a mismatch calculation circuit 21, and an accumulation 22, a minimum value holding circuit 23, and a cutout address holding circuit 24. That is, first means 4
Then, the frame memory 13 of the input image processing means 2 cuts out the pattern to be recognized based on the cutout address,
The pattern to be recognized is divided into a plurality of groups each consisting of a plurality of pixels, and a representative value of each group is determined by the data compression circuit 19 to be recognized. The data compression circuit 20 obtains the representative value of the group corresponding to the pattern to be recognized of the standard pattern similarly divided and read from the standard pattern memory 3. The degree of mismatch between these representative values is determined by a mismatch calculation circuit 21. The degree of discrepancy calculated by the discrepancy calculation circuit 21 is calculated by the accumulator 2.
2 for all groups, and the minimum value holding circuit 23 and cutout address holding circuit 24 determine the cutout address with the smallest evaluation value for each group. The second means is the switching devices 25a to 25e at the time of recognition.
from a standard pattern memory 3, a recognized data compression circuit 19, a standard pattern compression circuit 20, a discrepancy calculation circuit 21, an accumulator 22, a minimum value holding circuit 23, and a cutout address holding circuit 24, which are configured by switching the data to the rAJ side. Become. In the second means 5, the frame memory 1 of the input image processing means 2
A mismatch calculation circuit 21 calculates the degree of mismatch between each pixel of the recognized pattern cut out from No. 3 based on the cutout address and the corresponding pixel of the standard pattern 3. The degree of mismatch obtained in this way is added up for all pixels in an accumulator 22.

The cut-out address whose evaluation value of the addition result is the smallest is determined by the minimum value holding circuit 23 and the cut-out address holding circuit 24.
Accordingly, the address obtained by the first means 4 is obtained for each pixel from among the entire several pixels including the address obtained in the first means 4 and its vicinity.

Furthermore, to explain the details of the above configuration, the television camera 1
1 is a device that obtains an image of a target object to perform a recognition operation, and outputs the image to an A/D converter 12; A/D
The converter 12 converts the input image processing signal into a digital value and outputs it to the frame memory 13. The frame memory 13 stores an input image of input digital values for one screen.

Reference numeral 15 denotes a cutout address generation circuit, and the cutout address generation circuit 15 sequentially generates a cutout address for determining an area to be compared with a standard pattern in the input image of the frame memory 13, for example, 8×8 times. . The group cutout address generation circuit 16 generates a group cutout address for determining a group unit area to be compared with the standard pattern in the frame memory 130 input image.
' is a circuit that occurs 4×4 times, skipping -addresses. Further, this sweep address generation circuit 17 is configured to operate in a 16X1 manner in the frame memory 13 and the standard pattern memory 3.
A sweep address for sweeping an area of 6 pixels is generated, and this signal is sent to the standard pattern memory 3 as a standard pattern memory read address. Cutout address generation circuit 1
The cutout address from 5 or the group cutout address from the group cutout generation circuit 16 is switched by the switch 25a, and added to the sweep address from the sweep address generation circuit 17 by the adder 18. is sent as a frame memory read address.

The image data read out from the frame memory 13 using the frame memory read address is transferred to the switch 25b.
Accordingly, the data is supplied to the recognized data compression circuit 19 or the direct line 26. In this embodiment, the recognition data compression circuit 19 inputs four pieces of pixel data indicated by the frame memory read address output from the adder 18 in the frame memory 13, and calculates the average value as a group representative value of the recognition pattern. It is supplied to the switching device 25c as a signal. The switch 25c supplies one of the recognized data compression circuit 19 or the direct line 26 to the mismatch degree calculation circuit 21.

Further, the pixel data read out from the standard pattern memory 3 by the sweep address from the sweep address generator 17 is transferred to the standard pattern compression circuit 20 by the switch 25d. Alternatively, it may be supplied to the direct line 27. The standard pattern compression circuit 20 inputs four pixel data from the standard pattern memory 3 in this embodiment, and uses the average value as the group representative value of the standard pattern to the switch 25e.
supply to. The output from the standard pattern compression circuit 20 or the direct line 27 is input to the switch 25e, which selects one of the two and applies it to the mismatch calculation circuit 21.

The mismatch degree calculation circuit 21 calculates the mismatch degree between the representative value of the group of recognized patterns from the recognized data compression circuit 19 and the representative value of the standard pattern from the standard pattern compression circuit 20, and accumulates the calculation results. It is given to the calculator 22. The accumulator 22 is reset before the sweep address generation circuit 17 starts sweeping, and accumulates the degree of mismatch output from the degree of mismatch calculation circuit 21 during the sweep of the 16×16 pixel area and holds it as an evaluation value. The output from the accumulator 22 is input to the minimum value holding circuit 23. The minimum value holding circuit 23 is configured to hold the main value before the group extraction address generation circuit 16 starts extraction of the input image in units of blocks, and before the extraction address generation circuit 15 starts extraction of the input image in units of pixels. The minimum value of the circuit is reset and becomes 16X1
Every time a group sweep of a 6-pixel area is completed, the evaluation value held by the accumulator 22 is compared with the minimum value held by this circuit, and if the evaluation value is smaller, the minimum value is evaluated. At the same time, a replacement pulse indicating the replacement is output to the cutout address holding circuit 24. This cutout address holding circuit 24 is a device that stores the cutout address or group cutout address when the replacement pulse is input. The switchers 25a to 25e are configured to switch to "B" when calculating the degree of mismatch in units of groups, and to "A" when calculating the degree of mismatch in units of pixels.

Next, the operation of the above embodiment will be explained.

FIG. 2 is a diagram explaining the operation timing.

Here, the vertical axis in FIG. 2 shows the cutout address generation circuit 15.
Or the minimum value reset signal output from the group extraction address circuit 16, the extraction address generated from the extraction address generation circuit 15, the group extraction address generation circuit 1
6, an accumulator reset signal from the sweep address generation circuit 17, an evaluation strobe signal,
Standard pattern memory read address, frame memory successive address output from adder 18, mismatch degree calculation circuit 21
The degree of inconsistency output by , the minimum value address held by the extraction address holding circuit 23, and the state timing of the switches 25a to 25e are shown, and the horizontal axis shows time t.

FIG. 3 is a diagram illustrating the address of an input image of a frame memory consisting of 23 pixels in both the X and Y directions.

At the timing when the cutout address in FIG. 2 is "1", the frame memory address of X="1" and Y-"1" indicated by "1" in FIG. 3 is output, and the group cutout address is "3". ”
At the timing of , X=“3” and Y indicated by “3” in Figure 3.
= Outputs the frame memory address of "1". Thereafter, the group extraction address is increased by 1 in the same way, and the rectangular area of ``8'' is swept in the X direction and ``8'' in the Y direction.Finally, the address of the frame in Figure 2 is rl
At the timing of 45J, the X indicated by "145" in Figure 3
=r7J, Y=outputs the group extraction address of r7J. Further, once this cutout address is determined, a 16×16 pixel area with this cutout address as the upper left pixel is to be evaluated.

FIG. 4 is a diagram for explaining the address of the standard pattern in the standard pattern memory, which is composed of 16 pixels in both the X direction and the Y direction.

The operation will be specifically explained using FIG. 1, FIG. 2, FIG. 3, and FIG. 4 mentioned above.

In the above embodiment, from the input image obtained by operating the television camera 11, A/D converter 12, and frame memory 1.3, a part of the shape to be recognized that captures the feature is cut out as a standard pattern. It is set in the standard pattern memory 3 as a standard pattern.

The following recognition operation is a 4×
4 first large loop operations and frame memory 13
The second step is to compress the data of the 16x16 pixel recognition area into groups and totalize the degree of mismatch in each group (calculate the evaluation value) while sweeping the frame memory successive addresses and standard pattern memory successive addresses in the memory. A small loop, a third large loop operation of 16 x 16 pixels to find the minimum value for each pixel while changing the extraction address of the frame memory 13, and a third large loop operation of 16 x 16 pixels while sweeping the frame memory successive address and standard pattern memory read address. The process is divided into a fourth small loop operation that calculates the cumulative total (evaluation value) of the degree of mismatch in pixel units.

Note that the second small loop operation is included in the first large loop, and the fourth small loop operation is included in the fourth large loop.

First, prior to the first large loop operation, the switch 25
a to 25e are set to the group operation side of the rBJ side. In addition, a minimum value reset signal is sent from the group extraction address generation circuit 16 to the minimum value holding circuit 23 (time t), and the minimum value of the minimum value holding circuit 23 is set to an appropriately large value. It enters one large loop operation (time t).

In the first large loop operation, the extraction address output from the group extraction address generation circuit 16 is divided into a rectangular area of "8" in the X direction and "8" in the Y direction, as shown in FIGS. 2 and 3. Find the minimum evaluation value while skipping rIJ in a sweeping manner.

In the -th large loop operation, the extraction address generation circuit 1
As shown in Figures 2 and 3, the output address of step 5 is changed to sweep the rectangular area of ``9'' in the X direction and ``9'' in the Y direction, while finding the minimum evaluation value. .

Next, prior to the second small loop operation, the sweep address generation circuit 17 outputs a reset signal to the accumulator 22 to set the accumulator 22 to zero. When entering the second small loop operation (time 1), the sweep address generation circuit 17
generates a sweep address to sweep a 16x16 area. The sweep address is added to the group extraction address selected by the switch 25a in the adder 18, and becomes a frame memory read address. The frame memory read address starts from the cutout address of the input image, and in this embodiment, one group of four pixels is swept in the order of right side, bottom, and diagonal bottom right, and then it is swept to the next group. continue. Then, the 16×16 area with the upper left corner at the group cutout address is divided into 64 groups, and each group is sequentially swept and output. The frame memory read address is sent to the frame memory 13 to determine the subsequent address of the input image stored in the frame memory 13. As a result, the pixel data to be recognized read out from the frame memory 13 is transferred to the switching device 25.
Recognized data compression circuit 19 selected in b and 25c
In this embodiment, four pixels are input in group units.

The recognition target data compression circuit 19 calculates the magnitude values for each group, in this embodiment, the average value of four pixels.

On the other hand, the standard pattern successive addresses start from the top left of the standard pattern, that is, the address "1" in FIG. Sweep. In this way, the standard pattern memory 3 is divided into "64" groups each consisting of four pixels, and the standard pattern readout address for performing the sweep in group units for all groups is output. Thereby, the standard pattern pixel data read out from the standard pattern memory 3 is input to the standard pattern compression circuit 20 selected by the switch 25d or 25e in units of groups, for four pixels in this embodiment. In the standard pattern compression circuit 20, a representative value for each group, in this embodiment, an average value of four pixels is taken. The inconsistency calculation circuit 21 calculates the inconsistency between the representative value of the recognized data from the recognized data compression circuit 19 and the standard pattern representative value from the standard pattern compression circuit 20. The discrepancies from the discrepancy calculation circuit 21 are accumulated and held in an accumulator 22. When the sweep of the 16×16 area of the frame memory 13 and the standard pattern memory 3 in groups, that is, the second small loop is completed (time 13), the evaluation value has been obtained in the accumulator 22, and this value is held as the minimum value. The evaluation value is compared with the minimum value using the evaluation value strobe signal, and when the evaluation value is smaller, the minimum value is replaced with the evaluation value, and a replacement pulse is output to the cutout address holding circuit 24. The cutout address holding circuit 24 holds the group cutout address output from the group cutout address generation circuit 16 in accordance with the replacement pulse, and stores the group cutout address with the minimum evaluation value.

On the other hand, when the evaluation value is greater than or equal to the minimum value, neither the minimum value is replaced nor the cutting pulse is output. When this comparison is completed, execution of the first large loop is continued using the group extraction address output from the group extraction address generation circuit 16 as the next value. Cutout address generation circuit 15
When the output address of ``1'' is completed in the rectangular area of ``8'' for each of X and Y, the first large loop operation is completed at time 1. ), the cutout address holding circuit 24 stores
The address of Y is being obtained for each group. In this embodiment, the frame memory 13 is
r97J (X= r5J in Figure 3, Y= r5
Suppose that the address of J) is requested. This minimum evaluation value extraction address for each group is sent to the extraction address generation circuit 15.

Next, prior to the third large loop operation, the switch 25
a to 25e are set to rAJ, that is, the operation side in pixel units. Further, the cutout address generation circuit 15 sends a minimum value reset signal to the minimum value holding circuit 23 to set the minimum value to an appropriately large value, and enters a third large loop operation (time 15).

In the third large loop operation, the cutout address generation circuit 1
As shown in FIGS. 2 and 3, the extraction address outputted by No. 5 is the pixel in the vicinity of the minimum evaluation value extraction address "97" for each group obtained by the first large loop operation, in this embodiment. Then, X = "3" ~ r8J, Y-r3J ~ "8"
Find the minimum evaluation value while sweeping the 36-pixel area surrounded by .

Prior to the fourth small loop operation, the sweep address generation circuit 17 outputs an accumulator reset signal to make the evaluation value of the accumulator 22 zero. When we enter the fourth small loop operation (
At time t5), the sweep address generation circuit 17
A sweep address is generated to sweep the area. The sweep address is added by the adder 18 to the extraction address from the extraction address generation circuit 15 selected by the switch 25a, and becomes a frame memory read address. The frame memory successive addresses are first output so as to sequentially sweep a 16×16 area with the cutout address of the input image as the upper left corner. The frame memory successive address is sent to the frame memory 13 to determine the successive address of the input image stored in the frame memory 13. Thereby, the recognized pixel data read from the frame memory 13 is output to the mismatch calculation circuit 21 via the direct line 26 selected by the switches 25b and 25c.

On the other hand, the standard pattern successive address first sweeps a 16×16 area starting from the upper left of the standard pattern, that is, the address "1" in FIG. Thereby, the standard pattern pixel data read from the standard pattern memory 3 is supplied to the mismatch calculation circuit 21 via the direct line 27. In the mismatch calculation circuit 21, the frame memory 13
- The degree of discrepancy between the recognized data from the direct line 27 and the standard pattern pattern from the standard pattern memory 3/direct line 27 is determined. The degree of inconsistency from the degree of inconsistency calculating circuit 21 is accumulated and held in an accumulator 22. Upon completion of the sweep of the 16x16 area of the frame memory 13 and the standard pattern memory 3, i.e. the fourth small loop, the accumulator 2
2 has an evaluation value, and this value is applied to the minimum holding circuit 2.
Send to 3. The minimum holding circuit 23 compares the evaluation value and the minimum value using the evaluation strobe signal output from the sweep address generation circuit 17, and when the evaluation value is smaller, replaces the minimum value with the evaluation value and uses the replacement pulse as the cutout address. It is output to the holding circuit 24.

The cutout address holding circuit 24 holds the cutout address output from the cutout address generation circuit 16 in accordance with the replacement pulse, and stores the cutout address with the minimum evaluation value.

On the other hand, when the evaluation value is greater than or equal to the minimum value, neither the minimum value is replaced nor the cutting pulse is output. When this comparison is completed, execution of the third large loop is continued using the extraction address output from the extraction address generation circuit 16 as the next value. When the cutout address output from the cutout address generation circuit 15 finishes capturing the rectangular areas of "6" for each of X and Y in this embodiment, the third large loop operation is completed and the cutout address is transferred to the cutout address holding circuit 24. In this case, the X and Y addresses that have obtained the minimum evaluation value within the rectangular area are determined in pixel units, and the recognition operation is then completed. When the sweep of the 16×16 area of the frame memory 13 and the binary standard pattern memory 3 (that is, the fourth small loop) is completed (time [6), the evaluation value has been obtained in the accumulator 24, and this value is The signal is sent to the minimum holding circuit 25.

The minimum holding circuit 25 compares the evaluation value and the minimum value using the evaluation strobe signal output from the sweep address generation circuit 16, and when the evaluation value is smaller, replaces it with the minimum value and extracts the replacement pulse. Output to 26. The cutout address output from the cutout address generation circuit 15 is held according to the replacement pulse, and the cutout address with the minimum evaluation value is stored. On the other hand, neither the evaluation value changes to the minimum value nor outputs the cutting pulse. When this comparison result is completed, the execution of the third large loop is continued using the extraction address output from the extraction address generation circuit 15 as the next value. When sweeping a rectangular area where the extraction address output by the extraction address generation circuit 15 is "9" in each of X and Y,
To end the third large loop operation, time 1. ), the minimum evaluation value within the rectangular area and the X and Y addresses from which this value was obtained are determined, and the intended recognition operation is completed.

In this way, according to the above embodiment, the input image of the frame memory 13 is divided into a plurality of groups, and the cumulative total of the degree of discrepancy between the representative values of the corresponding groups of similarly divided standard patterns is minimized for all groups. After finding the extraction address for each group, select the extraction address where the evaluation value obtained by adding up the mismatch between the pixels of the recognized pattern and the corresponding standard pattern for all pixels is the smallest.
It is possible to recognize an image containing shading by determining the value for each pixel from among the entire several pixels including the vicinity of the address previously determined for each group. Further, in the above embodiment, it is also possible to divide the group into four pixels, square divisions such as nine pixels or 16 pixels, or rectangular divisions such as large pixels or 13 pixels. Further, although the representative value of each group was used as the average value within each group, other methods such as the median value may also be considered. Furthermore, each evaluation value obtained for each fourth group is memorized, and
From the distribution of these evaluation values when the 1Y address is used as a parameter, a method of finding a pattern similar to the standard pattern with a resolution of a fraction of a pixel can also be considered. In the above embodiment, the frame memory 13.1
When importing data from the quasi-pattern memory 3 to the discrepancy calculation circuit 21, both representative values are obtained, but a standard pattern memory for representative values and a frame memory are prepared, and a standard pattern memory for representative values is used. It is also conceivable to store representative values grouped in advance in the frame memory for representative values, and to transfer data in parallel when data is transferred from the A/D converter 12 to the frame memory 13.

〔Effect of the invention〕

As explained above, as is clear from the above embodiment, the present invention divides an input image of a frame memory into a plurality of groups, and calculates the total degree of discrepancy between representative values of corresponding groups of similarly divided standard patterns. After determining the extraction address for each group that has the minimum cumulative value for the group, the evaluation value obtained by adding the degree of mismatch between the pixels of the recognized pattern and the corresponding standard pattern for all pixels is the smallest. By determining the extraction address for each pixel from among the entire several pixels including those in the vicinity of the address previously determined for each group, it becomes possible to recognize images containing shading without reducing the resolution of the recognition position. In addition, there is an advantage that the number of times the degree of mismatch is calculated can be reduced, that is, the recognition time can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of a pattern recognition device according to an embodiment of the present invention, Fig. 2 is a timing chart of the same device, and Fig. 3 shows pixel addresses on the frame memory, cutout address sweep area, and FIG. 4 is a diagram showing the arrangement of pixels on a binary standard pattern memory, and FIG. 5 is a block diagram showing a conventional device. DESCRIPTION OF SYMBOLS 1... Pattern recognition device, 2... Input image processing means, 3... Standard pattern memory, 4... First means,
5...Second means, 11...TV camera, 12.
...A/D converter, 13...Frame memory, 1
5... Cutout address generation circuit, 16... Group cutout address generation circuit, 17... Sweep address generation circuit, 18... Adder, 19... Recognized data compression circuit, 20... - Standard pattern compression circuit, 21... Mismatch calculation circuit, 22... Accumulator, 23... Minimum value holding circuit, 24... Extraction address holding circuit. Name of agent: Patent attorney Takahaka Awano (1 person) Dimensions and pulse

Claims (1)

[Scope of Claims] An input image processing means that digitizes an image signal obtained from an image sensor to obtain a digital image, and stores this in a frame memory; and a standard pattern memory that stores the input digital image as a standard pattern. , At the time of recognition, a pattern to be recognized is cut out from the input image processing means based on the cutout address, the pattern to be recognized is divided into a plurality of groups each consisting of a plurality of pixels, and a representative value of each group and a standard value divided in the same manner are extracted. A first means for determining, for each group, a cut-out address that minimizes the evaluation value obtained by adding up the degree of mismatch between the standard pattern read from the pattern memory and the representative value of the group corresponding to the recognized pattern for all groups; The degree of mismatch between each pixel of the recognition pattern and the corresponding pixel of the standard pattern is added for all pixels, and the cutout address that has the smallest evaluation value of the addition result is the address obtained by the first method. and second means for determining pixel by pixel from all the several pixels including the vicinity thereof.