JPH05102305A - 半導体集積回路の自動レイアウト方法 - Google Patents

半導体集積回路の自動レイアウト方法

Info

Publication number
JPH05102305A
JPH05102305A JP3260187A JP26018791A JPH05102305A JP H05102305 A JPH05102305 A JP H05102305A JP 3260187 A JP3260187 A JP 3260187A JP 26018791 A JP26018791 A JP 26018791A JP H05102305 A JPH05102305 A JP H05102305A
Authority
JP
Japan
Prior art keywords
wiring
lattices
grid
integrated circuit
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3260187A
Other languages
English (en)
Inventor
Akihiro Sato
昭宏 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP3260187A priority Critical patent/JPH05102305A/ja
Publication of JPH05102305A publication Critical patent/JPH05102305A/ja
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】 決められた格子の上を定められた配線層で配
線するアルゴリズムを用いた半導体集積回路の自動レイ
アウト方法で配線した配線の長さを短かくする。 【構成】横方向の格子１および縦方向の格子２に加えて
新たに斜め方向の格子３，４を設け、それぞれの格子上
に主に使う配線層を定める。これにより配線すると、Ａ
点Ｂ点間の配線パタン５、Ｃ点Ｄ点間の配線パタン６の
ようになる。 【効果】配線の長さを最大０．７倍に短かくすることが
でき、配線抵抗と配線容量が減るので動作速度が速くな
る。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体集積回路の自動レ
イアウト方法に関し、特に決められた格子の上を定めら
れた配線層で配線するアルゴリズムを用いた自動レイア
ウト方法に関する。
【０００２】
【従来の技術】従来の決められた格子の上を定められた
配線層で配線するアルゴリズムを用いた半導体集積回路
の自動レイアウト方法は、例えば図３に示すように、第
１の配線層を主に横方向の格子１１上の配線に使い、第
２の配線層を主に縦方向の格子１２上の配線に使ってい
た。さらに、３層以上の配線層を使う場合は、第３の配
線層を第１の配線層と同一の横方向の格子１１上、第４
の配線層を第２の配線層と同一の縦方向の格子１２上、
というように順次割り当てて使っていた。
【０００３】図４は図３の格子に従って実際に配線した
パタン図である。図４において、横方向に第１の配線層
１５があり、縦方向に第２の配線層１６があり、各配線
層１５，１６の接続パタン１７で電気的に接続されてい
る。これらは、Ａ，Ｂ点，Ｃ，Ｄ点間の電気的接続をす
るための配線パタンである。
【０００４】
【発明が解決しようとする課題】このような従来の半導
体集積回路の自動レイアウト方法では、たとえ３層以上
の配線層を使っても横方向または縦方向の格子１１，１
２上にしか配線しないので、配線層を増やしても配線が
しやすくなるだけで、配線の長さはあまり短かくならな
いという問題点があった。
【０００５】本発明の目的は、前記問題点を解決し、配
線の長さを短かくする半導体集積回路の自動レイアウト
方法を提供することにある。
【０００６】
【課題を解決するための手段】本発明の半導体集積回路
の自動レイアウト方法の構成は、少なくともひとつの横
方向の格子上の配線に使う配線層と、少なくともひとつ
の縦方向の格子上の配線に使う配線層と、少なくともひ
とつの斜め方向の格子上の配線に使う配線層とを用いる
ことを特徴とする。
【０００７】
【実施例】図１は本発明の一実施例で使用される配線格
子図である。図１において、横方向の格子１と縦方向の
格子２に加えて、右上がり斜め方向の格子３と右下がり
斜め方向の格子４とを設定し、それぞれの格子１，２，
３，４上の配線に主に使う配線層として、第１から第４
の配線層を割り当てる。
【０００８】図２は図１の格子図を用いて配線パタンを
行ったパタン図である。
【０００９】図２において、第１の配線層７，第２の配
線層８，第３の配線層５，第４の配線層６とがあり、各
配線層間の接続パタン９が接続点等に設けられている。
【００１０】図２では、Ａ点Ｂ点間，およびＣ点Ｄ点間
を配線した例で、従来の図４と比べて、配線の長さが
０．７〜０．８倍に短かくなっている。
【００１１】
【発明の効果】以上説明したように、本発明は、従来の
横および縦方向の格子上の配線に使う配線層に加えて、
斜め方向の格子上の配線に使う配線層を用いることによ
り、配線の長さを最大０．７倍に短かくすることがで
き、配線抵抗と配線容量とが減るので、動作速度が速く
なるという効果を有する。
【図面の簡単な説明】
【図１】本発明の一実施例の半導体集積回路の自動レイ
アウト方法で使用される配線格子図である。
【図２】図１の格子に沿って作成した配線パタン図であ
る。
【図３】従来の自動レイアウト方法で使用される配線格
子図である。
【図４】図３の格子に沿って作成した配線パタン図であ
る。
【符号の説明】
１，１１ 横方向の格子 ２，２２ 縦方向の格子 ３ 右上がり斜め方向の格子 ４ 右下がり斜め方向の格子 ５，６，１５，１６ ２点間の配線パタン
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 7353−4Ｍ Ｈ０１Ｌ 21/88 Ａ

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 少なくともひとつの横方向の格子上の配
    線に使う配線層と、少なくともひとつの縦方向の格子上
    の配線に使う配線層と、少なくともひとつの斜め方向の
    格子上の配線に使う配線層とを用いることを特徴とする
    半導体集積回路の自動レイアウト方法。
JP3260187A 1991-10-08 1991-10-08 半導体集積回路の自動レイアウト方法 Pending JPH05102305A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3260187A JPH05102305A (ja) 1991-10-08 1991-10-08 半導体集積回路の自動レイアウト方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3260187A JPH05102305A (ja) 1991-10-08 1991-10-08 半導体集積回路の自動レイアウト方法

Publications (1)

Publication Number Publication Date
JPH05102305A true JPH05102305A (ja) 1993-04-23

Family

ID=17344541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3260187A Pending JPH05102305A (ja) 1991-10-08 1991-10-08 半導体集積回路の自動レイアウト方法

Country Status (1)

Country Link
JP (1) JPH05102305A (ja)

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Publication number Priority date Publication date Assignee Title
US6262487B1 (en) 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
KR100402222B1 (ko) * 1999-11-17 2003-11-13 가부시끼가이샤 도시바 자동 설계 방법, 노광용 마스크 세트, 반도체 집적 회로장치, 반도체 집적 회로 장치의 제조 방법 및 자동 설계프로그램을 기록한 기록 매체
US6738960B2 (en) 2001-01-19 2004-05-18 Cadence Design Systems, Inc. Method and apparatus for producing sub-optimal routes for a net by generating fake configurations
US6745379B2 (en) 2001-08-23 2004-06-01 Cadence Design Systems, Inc. Method and apparatus for identifying propagation for routes with diagonal edges
US6795958B2 (en) 2001-08-23 2004-09-21 Cadence Design Systems, Inc. Method and apparatus for generating routes for groups of related node configurations
US6802049B2 (en) 2000-12-06 2004-10-05 Cadence Design Systems, Inc. Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies
US6848091B2 (en) 2000-12-06 2005-01-25 Cadence Design Systems, Inc. Partitioning placement method and apparatus
US6859916B1 (en) 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US6877146B1 (en) 2001-06-03 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6886149B1 (en) 2002-01-22 2005-04-26 Cadence Design Systems, Inc. Method and apparatus for routing sets of nets
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6892369B2 (en) 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US6904580B2 (en) 2000-12-06 2005-06-07 Cadence Design Systems, Inc. Method and apparatus for pre-computing placement costs
US6907593B2 (en) 2000-12-06 2005-06-14 Cadence Design Systems, Inc. Method and apparatus for pre-computing attributes of routes
US6931616B2 (en) 2001-08-23 2005-08-16 Cadence Design Systems, Inc. Routing method and apparatus
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US6944841B1 (en) 2002-01-22 2005-09-13 Cadence Design Systems, Inc. Method and apparatus for proportionate costing of vias
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6957411B1 (en) 2001-06-03 2005-10-18 Cadence Design Systems, Inc. Gridless IC layout and method and apparatus for generating such a layout
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US6957410B2 (en) 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US6973634B1 (en) 2002-01-22 2005-12-06 Cadence Design Systems, Inc. IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US6988257B2 (en) 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US6996789B2 (en) 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7003754B2 (en) 2000-12-07 2006-02-21 Cadence Design Systems, Inc. Routing method and apparatus that use of diagonal routes
US7003752B2 (en) 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US7010771B2 (en) 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7013451B1 (en) 2002-01-22 2006-03-14 Cadence Design Systems, Inc. Method and apparatus for performing routability checking
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7024650B2 (en) 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7047513B2 (en) 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7055120B2 (en) 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7058913B1 (en) 2001-09-06 2006-06-06 Cadence Design Systems, Inc. Analytical placement method and apparatus
US7069530B1 (en) 2001-06-03 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for routing groups of paths
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US7080342B2 (en) 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US7080336B2 (en) 2000-12-06 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for computing placement costs
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7093221B2 (en) 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US7107564B1 (en) 2001-06-03 2006-09-12 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US7117468B1 (en) 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US7143382B2 (en) 2001-08-23 2006-11-28 Cadence Design Systems, Inc. Method and apparatus for storing routes
US7171635B2 (en) 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7216308B2 (en) 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
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US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
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* Cited by examiner, † Cited by third party
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US6436804B2 (en) 1998-06-23 2002-08-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6645842B2 (en) 1998-06-23 2003-11-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6262487B1 (en) 1998-06-23 2001-07-17 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
KR100402222B1 (ko) * 1999-11-17 2003-11-13 가부시끼가이샤 도시바 자동 설계 방법, 노광용 마스크 세트, 반도체 집적 회로장치, 반도체 집적 회로 장치의 제조 방법 및 자동 설계프로그램을 기록한 기록 매체
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US7013450B2 (en) 2000-12-06 2006-03-14 Cadence Design Systems, Inc. Method and apparatus for routing
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US6795958B2 (en) 2001-08-23 2004-09-21 Cadence Design Systems, Inc. Method and apparatus for generating routes for groups of related node configurations
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US6973634B1 (en) 2002-01-22 2005-12-06 Cadence Design Systems, Inc. IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US7114141B1 (en) 2002-01-22 2006-09-26 Cadence Design Systems, Inc. Method and apparatus for decomposing a design layout
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US6944841B1 (en) 2002-01-22 2005-09-13 Cadence Design Systems, Inc. Method and apparatus for proportionate costing of vias
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US6957409B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for generating topological routes for IC layouts using perturbations
US6996789B2 (en) 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7171635B2 (en) 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7047513B2 (en) 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7080342B2 (en) 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US6988257B2 (en) 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7003752B2 (en) 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US7093221B2 (en) 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US7216308B2 (en) 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US6892369B2 (en) 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US7010771B2 (en) 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7506295B1 (en) 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
US7514355B2 (en) 2004-06-24 2009-04-07 Fujitsu Microelectronics Limited Multilayer interconnection structure and method for forming the same

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