JPH0510472Y2 - - Google Patents

Description

[Detailed description of the invention] Industrial application field The present invention relates to an IF (intermediate frequency) processing circuit for VTRs, and in particular to a so-called front end in which a tuner part and an IF processing circuit are incorporated in a VTR (video tape recorder). Regarding improvement of parts.

Background Art In color television, AGC is used to automatically control the gain of the receiver according to the strength of the received radio waves, to always obtain a constant video detection output, and to reduce contrast fluctuations.
(Automatic Gain Control) circuit is used. Such an AGC circuit uses detected video signals to determine the strength of input radio waves, and controls the gain of the tuner and video IF amplification circuit accordingly. Types of such AGC circuits include average value type, peak value type, and keyed type. The keyed AGC circuit obtains a keying pulse (also referred to as a keyed pulse) from a flyback pulse during the horizontal retrace period to turn on (activate) the keying stage. In the keyed AGC circuit, the AGC voltage is the video signal period (horizontal scanning period)
It has features such as being unaffected by noise mixed into the system, and being able to operate while following sudden fluctuations in input radio waves and disturbances caused by flutter from airplanes, etc. Because of these characteristics, color televisions often use keyed AGC circuits in their IF processing circuits.

Problems to be solved by the invention By the way, it is conceivable to use a keyed AGC circuit as an IF processing circuit in VTRs as well, expecting the above characteristics. However, since VTRs do not have flyback transformers, flyback pulses cannot be used as keying pulses, and therefore a keyed AGC circuit cannot be used.

Therefore, the present invention attempts to make it possible to employ a keyed AGC circuit even in a VTR by adding a circuit for generating keying pulses synchronized with a horizontal synchronization signal to the IF processing circuit.

Means for solving the problems In order to achieve the above purpose, the VTR according to the present invention is
The IF processing circuit for use includes at least a video IF amplification circuit,
The present invention is characterized in that it includes a keyed AGC circuit and a keying pulse generation circuit, and the keying pulse generation circuit includes a synchronization pulse generator and a pulse shaper.

Function The video IF amplification circuit amplifies the composite video signal at an intermediate frequency. The keyed AGC circuit turns on the key during a keying pulse period in response to a change in the level of the input signal, and controls the gain of the tuner and/or the video IF amplifier circuit. In the keying pulse generation circuit, the synchronization pulse generator generates pulses synchronized with the horizontal synchronization signal from the composite video signal, and the pulse shaper shapes the synchronization pulses into pulses with the time constant required for the keying pulse. Then, a keying pulse is generated to turn on the keyed AGC.

Embodiment Figure 1 shows an embodiment of the present invention for a VTR with keyed AGC that demodulates SECAM broadcasting signals.
A block diagram of the IF processing circuit is shown, and in the figure,
The front end of the VTR includes Tuner 1 and
An IF processing circuit 2 is provided. The IF processing circuit 2 is
It is composed of an audio processing circuit 3 and a video processing circuit 4.

The audio processing circuit 3 includes a 4.5MHz detection circuit 5, an audio
It includes an IF amplifier circuit 6, an FM detection circuit 7, and a low frequency amplifier circuit 8. The operation of this audio processing circuit 3 is well known and will therefore be omitted.

The video processing circuit 4 includes a video IF amplification circuit 9, a video detection circuit 10, a video amplification circuit 11, and a keyed AGC.
It includes a circuit 12 and a keying pulse generation circuit 20 which is a feature of the present invention. The video IF amplification circuit 7 is
It usually consists of three to four stages of amplifier circuits, and wide-band amplifies the composite video signal at an intermediate frequency (50MHz band). The video detection circuit 10 detects the composite signal (ie, the modulated video signal) amplified by the video IF amplifier circuit and extracts the video signal. This video signal is amplified by the video amplification circuit 11 into a signal (mainly a luminance signal) of a required magnitude. For this reason, the video amplification circuit 11 is composed of a plurality of stages of amplification circuits.

The keying pulse generation circuit 20 includes a tuner 1
a synchronization pulse generator 21 for generating pulses synchronized with a horizontal synchronization signal from a composite video signal inputted from a composite video signal; It is composed of a pulse shaper 22. The details will be described later with reference to FIG.

The keyed AGC circuit 12 generates and derives a gain control signal by turning on the keying stage during the horizontal blanking period based on the output change detection signal detected by the video amplifier circuit 11 and the keying pulse given from the keying pulse generation circuit 20. is applied to the tuner 1 and/or the video IF amplifier circuit 9. In addition,
Although the illustration shows a case where the IF processing circuit 2 is composed of an audio processing circuit 3 and a video receiving circuit 4,
Since the definition of the IF processing circuit differs depending on what is included in the common unit as the front end,
It is not limited to what is illustrated. For example, the audio processing circuit 3
In the case where the video receiving circuit 4 is incorporated into another unit, the video receiving circuit 4 becomes an IF processing circuit. In short, the IF of this invention
The processing circuits that are incorporated into a common unit include at least the video IF amplifier circuit 9 and the keyed AGC.
12 and a keying pulse generation circuit 20 are required.

FIG. 2 shows a specific circuit of the keying pulse generation circuit 20 which is a feature of the present invention. In this configuration, the synchronous pulse generator 21 uses, for example, an IC manufactured by Siemens (type LA7808), and includes a synchronous separation circuit 21a, a horizontal pulse oscillator 21b, and an automatic frequency control (AFC) circuit 21c.
A plurality of integrating circuits 23 and 24 are connected to the input/output terminals of the synchronous pulse generator 21 in a related manner.
The pulse shaper 22 uses, for example, μPD4528 manufactured by Nippon Denki Co., Ltd., and includes two one-shot multis 22a and 22b. This pulse shaper 22
The one-shot multi terminals 22a, 22b
Time constant circuits 25 and 26 for determining the time constant of are connected in relation to each other.

FIG. 3 is a waveform diagram of signals A to H at various parts to help explain the operation of the keying pulse generating circuit 20.

Next, the operation of the keying pulse generation circuit 20 will be described in detail with reference to FIGS. 2 and 3.

A composite video signal A of a desired channel output from the tuner 1 is input to the synchronization separation circuit 21a. One cycle (1H) of this composite video signal A consists of a horizontal scanning period and a horizontal blanking period, and includes a color television signal in which a luminance signal and a carrier color signal are weighted in the horizontal scanning period, and a horizontal blanking signal in the horizontal blanking period. Contains a sync signal (horizontal sync pulse) and color burst signal.

The synchronization separation circuit 21a extracts the horizontal synchronization signal B from the composite video signal A and supplies it to the AFC circuit 21c. The AFC circuit 21c receives as a feedback input the signal H integrated by the integrating circuit 24 consisting of a resistor _R2 and a capacitor _C2 , and derives a signal C synchronized with the period of the horizontal synchronizing signal and out of phase.
This signal C is integrated by an integrating circuit 23 consisting of a resistor R ₁ and a capacitor C ₁ and is applied to the horizontal pulse oscillator 21b as a signal D for controlling the oscillation frequency. Horizontal pulse oscillator 21b
changes its oscillation frequency in accordance with the signal D, and as a result derives a pulse signal E that is synchronized with the period of the horizontal synchronizing signal and out of phase, and supplies it to the one-shot multi 22a.

The one-shot multi 22a is triggered by the rising edge of the pulse signal E, and outputs a high-level signal F only during a fixed time period t1 set by a time constant circuit 25 consisting of a variable resistor _R3 and a capacitor _C3 .
is derived and given to the one-shot multi 22b.
The one-shot multi 22b is triggered by the falling edge of the signal F, and derives a high-level signal G only for a fixed time t2 set by a time constant circuit 26 consisting of a variable resistor _R4 and a capacitor _C4 . This signal G has a high-level appearance phase that is synchronized with the horizontal synchronization signal, and a high-level period (i.e., time
t2) extends slightly before and after the low level period of the horizontal synchronizing signal. This signal G is derived as a keying pulse, and the keyed AGC circuit 1
given to 2. Therefore, the time constant circuits 25 and 26
The time constant of , that is, the resistance value of variable resistors R ₃ and R ₄ is,
The high level period of the keying pulse G and its cycle (or frequency) are adjusted in advance so that the above relationship is established. In this way, the keying pulse G
The reason why the high-level period of the horizontal synchronizing signal is chosen to be slightly wider before and after the low-level period of the horizontal synchronizing signal is because the horizontal synchronizing signal is only a part of the horizontal retrace period. This is to cause the keyed AGC circuit 12 to work over almost the entire line period.

Thus, it has no flyback transformer.
Even in a VTR, a keying pulse G can be created whose period and phase are synchronized with the horizontal synchronizing signal and whose pulse width (high level period) is the width necessary to operate the keyed AGC circuit 12.

Effects of the invention Since the invention is configured as explained above, even in a VTR without a flyback transformer,
The keyed pulse required to operate the keyed AGC circuit can be created, and keyed AGC circuits can also be used on VCRs.
This has the effect of making it possible to utilize the characteristics of circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an intermediate frequency processing circuit for a VTR according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram of a keying pulse generation circuit that is a feature of the present invention, and FIG. FIG. 2 is a waveform diagram of each part. 1... Tuner, 2... IF processing circuit, 3...
Audio processing circuit, 4... Video receiving circuit, 5...
4.5MHz detection circuit, 6...Audio IF amplifier circuit, 7...
...FM detection circuit, 8...Low frequency amplification circuit, 9...
Video IF amplifier circuit, 10...Video detection circuit, 11
...Video amplification circuit, 12...Keyed AGC circuit,
20... Keying pulse generation circuit, 21... Synchronous pulse generator, 22... Pulse shaper.

Claims (1)

[Claims for Utility Model Registration] At least a video IF amplifier circuit, a tuner and/or a video
Keyed AGC to control the gain of IF amplifier circuit
circuit, and a keying pulse generation circuit that generates a keying pulse for keying on a keyed AGC circuit, and the keying pulse generation circuit includes a synchronization pulse generator that generates a pulse synchronized with a horizontal synchronization signal from a composite video signal. , a pulse shaper that shapes a synchronization pulse into a pulse with a time constant necessary for a keying pulse to derive a keying pulse, and the synchronization pulse generator includes a synchronization separation circuit that extracts a horizontal synchronization signal from a composite video signal. , an AFC circuit that inputs the horizontal synchronization signal extracted by this synchronization separation circuit and derives a signal that is synchronized with the period of the horizontal synchronization signal and whose phase is shifted, and an AFC circuit that inputs the output signal of this AFC circuit and derives its oscillation frequency. and a horizontal pulse oscillator that derives a pulse signal synchronized with the period of a horizontal synchronization signal and out of phase with the period of the horizontal synchronization signal, and the pulse shaper is triggered by the pulse signal derived from the horizontal pulse oscillator and generates a pulse signal for a predetermined period of time. The output signal of the first one-shot multi is input to synchronize with the horizontal synchronization signal only for a predetermined period, and the high-level period is the low level of the horizontal synchronization signal. An IF processing circuit for a VTR, characterized in that it includes a second one-shot multi for deriving a keying pulse that is slightly spread before and after the level period.