JPH051076Y2 - - Google Patents

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Publication number
JPH051076Y2
JPH051076Y2 JP1983126029U JP12602983U JPH051076Y2 JP H051076 Y2 JPH051076 Y2 JP H051076Y2 JP 1983126029 U JP1983126029 U JP 1983126029U JP 12602983 U JP12602983 U JP 12602983U JP H051076 Y2 JPH051076 Y2 JP H051076Y2
Authority
JP
Japan
Prior art keywords
hemispherical
case
electrode plate
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1983126029U
Other languages
Japanese (ja)
Other versions
JPS6033438U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12602983U priority Critical patent/JPS6033438U/en
Publication of JPS6033438U publication Critical patent/JPS6033438U/en
Application granted granted Critical
Publication of JPH051076Y2 publication Critical patent/JPH051076Y2/ja
Granted legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は、例えば大電力用半導体装置用マウン
トケースに適用して好適な半導体マウント用ケー
スに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor mounting case suitable for application to, for example, a mounting case for a high-power semiconductor device.

大電力用半導体装置のマウント方式として、従
来平型ケースやスタンド型ケースが一般的である
が、これらのケースを使用する素子に於ては、平
方センチメートル当り数百キログラム以上の加圧
をして使用するのが普通である。
Conventionally, flat cases and stand-type cases are commonly used as mounting methods for high-power semiconductor devices, but devices using these cases are used under pressure of several hundred kilograms or more per square centimeter. It is normal to do so.

また半導体素子とMoやW等の温度補償板及び
ケース金属板との鑞付に際しては、鑞材として
AuSiやApSb、又はAlSi等の所謂ハードソルダー
が用いられることが多い。
In addition, when brazing semiconductor elements with temperature compensating plates such as Mo and W, and case metal plates, use
So-called hard solders such as AuSi, ApSb, or AlSi are often used.

一般にこれら大電力半導体素子のマウントに際
しては素子をはじめ金属板類の厚み精度すなわち
平行度は高圧加重を加える為、極めて高く要求さ
れるのが普通である。
Generally, when mounting these high-power semiconductor devices, extremely high thickness accuracy, ie, parallelism, of the device and other metal plates is generally required because high pressure loads are applied.

以上は1個の素子をマウントするに際しての留
意点であるが、更に複数個の素子を同一ケースに
並列マウントする場合に於ては、従来の様なやり
方では極めて製造が困難となる。
The above are points to keep in mind when mounting one element, but when a plurality of elements are mounted in parallel in the same case, it becomes extremely difficult to manufacture using conventional methods.

本考案はかかる点に鑑み、従来の様な平行度を
あまり気にすることなく、しかも複数個の素子を
同一ケースにマウントする際にも極めて容易にで
きる様な構造の半導体マウント用ケースを提供す
ることを主たる目的とする。
In view of these points, the present invention provides a case for semiconductor mounting that has a structure that allows mounting of multiple elements in the same case extremely easily without having to worry about parallelism as much as in the past. The main purpose is to

本考案の内容は、半導体装置を鑞付する半球形
状金属ブロツクと、その金属ブロツクと曲率を同
じくする半球形状凹部を有する金属板とから成る
半導体マウント用ケースにある。
The subject matter of the present invention is a semiconductor mounting case comprising a hemispherical metal block to which a semiconductor device is brazed, and a metal plate having a hemispherical recess having the same curvature as the metal block.

以下図面に従つて更に本考案の一実施例につい
て詳述する。
An embodiment of the present invention will be further described in detail below with reference to the drawings.

第1図及び第2図は各々本考案の単一素子用の
マウントケースの分解図及び断面図を示す。図中
1は半導体素子、2は温度補償板、3は凹半球形
状金属ブロツク(例えばCu等)、4はブロツク3
の凹曲率と一致する凹部5を有する下側金属板
(下部電極)、2′は上側温度補償板、6は上側金
属板(上部電極)を示す。
1 and 2 show an exploded view and a sectional view, respectively, of a mounting case for a single device according to the present invention. In the figure, 1 is a semiconductor element, 2 is a temperature compensation plate, 3 is a concave hemispherical metal block (for example, Cu, etc.), and 4 is block 3.
2' is an upper temperature compensating plate, and 6 is an upper metal plate (upper electrode).

第3図は3個の各素子を並列マウントするため
のケースを表わし、第1図例のものがちようど3
個並列に大きな下部電極4′に設置される構造に
なつている。
Figure 3 shows a case for mounting three elements in parallel.
The structure is such that the electrodes are arranged in parallel on a large lower electrode 4'.

第4図は一個の素子につき、加圧した状態の説
明に供する図であり、同図Aは鑞材7の厚みに不
均等な分布があつた場合を示し、上部電極板6に
荷重Fを加えようとする図である。同図Bは荷重
Fを完全に加え、上部電極6と下部電極4との間
に素子及び温度補償板2が圧接された状態を示
す。この場合、下部電極4の曲率面5に沿つて半
球形状ブロツク3が矢印の方向に回転し、上部電
極板6と下部電極板4との主要平面は正確に平行
になる。そして加重Fは曲率面5部分で平面に垂
直な法線方向に加重の法線成分fに分割される。
FIG. 4 is a diagram for explaining the state in which pressure is applied to one element. Figure A shows a case where the thickness of the solder material 7 is unevenly distributed, and a load F is applied to the upper electrode plate 6. This is a diagram to be added. Figure B shows a state in which the load F is completely applied and the element and temperature compensating plate 2 are pressed between the upper electrode 6 and the lower electrode 4. In this case, the hemispherical block 3 rotates in the direction of the arrow along the curved surface 5 of the lower electrode 4, and the main planes of the upper electrode plate 6 and the lower electrode plate 4 become exactly parallel. Then, the weight F is divided into normal components f of the weight in the normal direction perpendicular to the plane at the curvature surface 5 portion.

尚、上述例は平型ケースの場合のみならず、ス
タツドケースの場合にも応用でき、半球形状金属
ブロツクは必ずしも半球でなくとも、下記電極4
の曲率面5にフイツトする面をもつていれば、同
様の効果が得られることは当然のことである。
Note that the above example can be applied not only to the case of a flat case but also to the case of a stud case, and the hemispherical metal block does not necessarily have to be a hemisphere.
It goes without saying that the same effect can be obtained if it has a surface that fits the curvature surface 5 of.

以上述べた如く本考案によれば、半導体装置を
鑞付けした半球形状金属ブロツクと、該金属ブロ
ツクの半球面と曲率を同じくして相互に滑動する
半球形状凹部を有する下部電極板と、半導体装置
の上面に接して押圧する上部電極板とより構成し
た半導体マウント用ケースにおいて、上部電極板
の押圧時に上記半導体装置との接触面が傾斜した
とき、半球形状金属ブロツクの半球面が下部電極
板の半球状凹面に対し滑りを生じて上記傾斜を解
消して上部電極板からの押圧力が半導体装置に均
等に加えられるように構成したので、 鑞付けによる各部に対する平行度が許容範囲外
になつた半球形状金属ブロツクを用いても、上記
半球形状金属ブロツクが下部電極に対して傾斜を
解消するように滑ることになるので、製造段階で
鑞付けの精度を厳格にする必要がなくなり工数の
低減となる。更にマウントされる半導体装置、上
下温度補償板、鑞材の各々の厚みがどの様な分布
を持つていたとしても皆確実に均等加圧され、従
来の様な厚みの精度に神経を使う必要がないし、
鑞材も必ずしもハードソルダーでなくとも良く、
作業温度の低下も可能である。
As described above, according to the present invention, a hemispherical metal block to which a semiconductor device is brazed, a lower electrode plate having a hemispherical recess having the same curvature as the hemispherical surface of the metal block and sliding relative to each other, and a semiconductor device In a semiconductor mount case composed of an upper electrode plate that is pressed in contact with the upper surface, when the contact surface with the semiconductor device is inclined when the upper electrode plate is pressed, the hemispherical surface of the hemispherical metal block is pressed against the lower electrode plate. Since the structure was configured so that the pressure force from the upper electrode plate was evenly applied to the semiconductor device by causing slippage on the hemispherical concave surface and eliminating the above-mentioned inclination, the parallelism of each part due to brazing was outside the permissible range. Even if a hemispherical metal block is used, since the hemispherical metal block slides against the lower electrode to eliminate the inclination, there is no need to ensure strict brazing accuracy during the manufacturing stage, resulting in a reduction in man-hours. Become. Furthermore, no matter how the thickness distribution of the mounted semiconductor device, upper and lower temperature compensator plates, and solder material is, it is ensured that they are all equally pressurized, and there is no need to pay attention to thickness accuracy like in the past. No,
The solder material does not necessarily have to be hard solder,
A reduction in working temperature is also possible.

更により大電力を目差して、大電力半導体素子
の同一ケースへの複数個並列マウントの場合に於
ては全素子とも均等な荷重印加が可能となる為極
めて有効なものとなる。
Furthermore, in the case of mounting a plurality of high-power semiconductor devices in parallel in the same case with the aim of achieving even higher power, this method is extremely effective since it is possible to apply an equal load to all the devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は単一素子用マウント用ケー
スの分解図及び断面図、第3図は複数個並列マウ
ントの一例としての3素子並列マウント用の本考
案のケースの略図、第4図A,Bは本案ケースに
マウントした素子へ荷重が加わつた時の状態を説
明する為の略線図である。 1……半導体素子、2,2′……温度補償板、
3……半球形状金属ブロツク、4,4′……下部
電極金属ブロツク、5……曲率面、6……上部電
極金属、7……鑞材。
Figures 1 and 2 are an exploded view and a sectional view of a case for mounting a single element, Figure 3 is a schematic diagram of the case of the present invention for mounting three elements in parallel as an example of mounting multiple elements in parallel, and Figure 4 A and B are schematic diagrams for explaining the state when a load is applied to the element mounted on the case of the present invention. 1... Semiconductor element, 2, 2'... Temperature compensation plate,
3... Hemispherical metal block, 4, 4'... Lower electrode metal block, 5... Curved surface, 6... Upper electrode metal, 7... Brazing material.

Claims (1)

【実用新案登録請求の範囲】 1 半導体装置を鑞付けした半球形状金属ブロツ
クと、該金属ブロツクの半球面と曲率を同じく
して相互に滑動する半球形状凹部を有する下部
電極板と、半導体装置の上面に接して押圧する
上部電極板とより構成した半導体マウント用ケ
ースにおいて、 上部電極板の押圧時に上記半導体装置との接
触面が傾斜したとき、半球形状金属ブロツクの
半球面が下部電極板の半球状凹面に対し滑りを
生じて上記傾斜を解消して上部電極板からの押
圧力が半導体装置に均等に加えられるように構
成したことを特徴とする半導体マウント用ケー
ス。 2 上記下部電極板は夫々上部電極板及び半導体
装置を鑞付けした複数個の半球形状金属ブロツ
クが載置できる複数の半球形状凹部を形成した
実用新案登録請求の範囲第1項記載の半導体マ
ウント用ケース。
[Claims for Utility Model Registration] 1. A hemispherical metal block to which a semiconductor device is brazed, a lower electrode plate having a hemispherical recess that has the same curvature as the hemispherical surface of the metal block and slides against each other, and a semiconductor device. In a case for a semiconductor mount consisting of an upper electrode plate that is pressed in contact with the upper surface, when the contact surface with the semiconductor device is tilted when the upper electrode plate is pressed, the hemispherical surface of the hemispherical metal block is pressed against the hemispherical surface of the lower electrode plate. 1. A case for a semiconductor mount, characterized in that the case is configured to cause sliding on a concave surface to eliminate the above-mentioned inclination so that a pressing force from an upper electrode plate is evenly applied to a semiconductor device. 2. The semiconductor mount according to claim 1, wherein the lower electrode plate has a plurality of hemispherical recesses on which a plurality of hemispherical metal blocks each having an upper electrode plate and a semiconductor device brazed thereon are formed. Case.
JP12602983U 1983-08-13 1983-08-13 Semiconductor mount case Granted JPS6033438U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12602983U JPS6033438U (en) 1983-08-13 1983-08-13 Semiconductor mount case

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12602983U JPS6033438U (en) 1983-08-13 1983-08-13 Semiconductor mount case

Publications (2)

Publication Number Publication Date
JPS6033438U JPS6033438U (en) 1985-03-07
JPH051076Y2 true JPH051076Y2 (en) 1993-01-12

Family

ID=30286714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12602983U Granted JPS6033438U (en) 1983-08-13 1983-08-13 Semiconductor mount case

Country Status (1)

Country Link
JP (1) JPS6033438U (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593580Y2 (en) * 1979-08-03 1984-01-31 サンケン電気株式会社 Semiconductor chip support device

Also Published As

Publication number Publication date
JPS6033438U (en) 1985-03-07

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