JPH05108698A - Vector processor - Google Patents

Abstract

(57) [Abstract] [Purpose] A vector processing device having a function of verifying an interlock that occurs when a load access unit and a data use unit perform chain processing on a vector register. The purpose is to generate an interlock of a complicated pattern at the time of execution and verify the cooperation process early. [Structure] Regardless of whether the load access unit 1 and the data use unit 3 are chained to the vector register 2 and whether the data is supplied from the loaded access unit 1 to the vector register 2, the data use unit 3 is externally connected. The interlock generating unit 5 for locking is provided, and the interlock period and the interlock releasing period are dynamically changed. The interlock is generated by taking a logical sum of a plurality of logical products of a plurality of set mask data and an internal signal group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device having a function of verifying an interlock generated when a load access part and a data use part perform chain processing on a vector register.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional vector processing apparatus, which uses a main memory unit (MSU) 8 including a load access unit 1, a vector register 2, a store access unit 6 and an arithmetic unit 7. A section 3 is provided. Here, especially the arithmetic unit 7 of the data use unit 3 is configured to continuously read the data loaded from the main memory 8 into the vector register 2 by the load access unit 1. The store access unit 6 is also configured to continuously read the data in the vector register 2 if there is no interference due to access competition in the main memory 8.

However, the load access unit 1 does not always make the data supply to the vector register 2 continuous due to the competition of the main memory access or the like, and subsequent instructions continuously read the data from the vector register 2. It's not always possible. Therefore, when the load access unit 1 and the data use unit 3 operate in a chain with respect to the vector register 2, the subsequent data use unit 3 overtakes the data supply to the vector register 2 by the preceding load access unit 3. The interlock detection circuit 4 monitors so as not to read the data, and the data use unit 3 is interlocked when the data read from the vector register 2 is interrupted.

The interlock detection circuit 4 for performing interlock control in the chain operation of the load access unit 1 and the data use unit 3 and the interlock processing circuit of the data use unit 3 are very large and complicated. ing. On the other hand, in the test process of the vector computer, it is verified whether or not the load access unit 1 and the data use unit 3 are operating normally in a chained state.

In order to perform this verification, it is necessary to input an instruction sequence that causes the vector processing devices to operate in a chain. Further, in order to generate the interlock condition in the vector processing device that is performing the chain processing, it is necessary to forcibly create the condition that the load access unit 1 cannot continuously supply the data to the vector register 2. As this method, another processing device such as a CPU or an IO processor is made to access the main memory, and the load access unit 1 is caused to perform the processing by the contention of the main memory access. Data is placed in a storage area where data cannot be read continuously.

There is also a vector processing apparatus provided with an N-bit counter or the like, forcibly interlocked at a regular period, and combined with this and a test program to verify the normal operation at the time of interlocking. ..

[0007]

However, in such a conventional verification method, in order to operate the load access part and the data use part of the vector processing device in a chain and generate the interlock condition, it is complicated. It is necessary to combine various instructions in, and a great deal of time is spent developing the test program for that.

In the case where the vector processing device itself forcibly generates the interlock, the interlock pattern is unique because the interlock is generated or released only once every N cycles. However, there is a problem that it cannot be sufficiently verified because it is far from the complicated interlock generation pattern that occurs when the program is actually executed.

The present invention has been made in view of the above conventional problems, and an interlock similar to a complicated pattern generated at the time of program execution with a simple structure is generated during the running of a test program to cause a load access unit. It is an object of the present invention to provide a vector processing device capable of early verifying the cooperative processing of the data use unit and the data use unit.

[0010]

FIG. 1 illustrates the principle of the present invention. First, the present invention comprises a vector register 2, a load access unit 1 for transferring data from the main storage device 8 to the vector register 2, and a data use unit 3 for reading data from the vector register 2 for processing. A chain process is performed in which the data using unit 3 uses the data written in the vector register 2 by the load access unit 1 without waiting for the end of the load instruction to the vector register 2 being executed by the access unit 1. It is possible, and when the supply of data from the load access unit 1 to the vector register 2 is interrupted and there is no more data to be read from the vector register 2 to the data use unit 3, an interlock detection for interlocking the data use unit 3 is performed. Part 4
The target is a vector processing device equipped with.

In the present invention for such a vector processing device, the chain processing of the load access unit 1 and the data use unit 3 for the vector register 2 and the presence / absence of data supply from the load access unit 1 to the vector register 2 Regardless of the above, an interlock generation unit 5 for interlocking the data use unit 3 from the outside is provided, and the interlock period and the interlock release period are dynamically changed.

Here, the interlock generating unit 5 is
-As a lock setting part, it stores predetermined max data.
First mask register group 11 for generating interlock
And the mask output and vector of the first mask register group 11
Internal signal group A of the processor ₀ ~ A_n The theory of conjunction with
Interlock device to set the latch 17 in a reasonable manner
The constant condition detection circuit 13 is provided.

As an interlock releasing unit, a second mask register group 12 for releasing interlock storing predetermined mask data, each mask output of the second mask register group 12 and other internal signals of the vector processing device itself. Group B ₀
.About.B _n, and an AND output of the logical product output and the interlock release condition detection circuit 14 for resetting the latch 17.

Further, the mask data set in the first mask register group 11 for interlock generation provided in the interlock setting section is incremented by a predetermined number N every time the interlock latch is set to a value. Every time the latch 17 is reset, the mask data set in the first + N circuit 15 as a mask register updating unit to be updated and the second mask register group 12 for interlock release provided in the interlock setting release unit is reset. And a second + N circuit 16 as a mask register updating means for updating to a value incremented by a predetermined number N,
The mask data can also be changed dynamically.

Further, as the mask register updating means,
A shift circuit or a random number instead of the + N circuits 15 and 16
A circuit may be used. Meanwhile, interlock
The interlock setting part of the generator 5 is a vector
Internal signal group A of the processor itself₀ ~ A_n Only logical conditions
Set the latch 17 by directly taking (arbitrary logic).
An interlock setting condition detection circuit 13 is provided, and
-As an unlocking unit, other than the vector processing device itself
Internal signal group B₀ ~ B _n Only logical conditions (arbitrary logic)
Interlock solution that directly resets latch 17
The removal condition detection circuit 14 may be provided. this
In this case, the mask register groups 11 and 12 are not always necessary.
There is no.

[0016]

According to the vector processing device of the present invention having such a configuration, the interlock is set and released by taking the logical sum of the logical products of the plurality of mask data and the internal signal group of the vector processing device. And the mask data is also incremented and changed each time the mask data is set or reset to dynamically create an interlock condition.

Therefore, an interlock having a complicated pattern equivalent to that which occurs when the load access unit and the data use unit are chained during program running is irrelevant to the presence or absence of a load instruction and chained state due to running of the test program. Can be generated in a pseudo manner, and the verification of the circuit unit that controls the interlock can be performed quickly.

[0018]

FIG. 2 is a block diagram of an embodiment showing the overall structure of the present invention. In FIG. 2, a load access unit 1 loads data from the main memory (MSU) 8 and writes it in the vector register 2. A data use unit 3 uses the contents of the vector register 2, and is composed of an arithmetic unit 7, a store access unit 6, and the like. The calculation unit 7 of the data use unit 3 reads the data from the vector register 2 and performs the calculation, and then stores the result in the vector register 2 again. Further, the store access unit 6 of the data use unit 3 stores the data read from the vector register 2 in the main storage device 8.
Store to.

Reference numeral 4 denotes an interlock detection circuit, which recognizes the chain state of the load access unit 1 and the data use unit 3, and the number DN1 of data written to the vector register 2 by the load access unit 1 and the data use unit 3 The number of read data DN2 is counted and the interlock is detected.
That is, when the number of read data DN2 matches the number of write data DN1 and the vector register 2 becomes empty, the interlock setting is detected. Detects unlocking.

Further, 5 is an interlock generating unit for forcibly setting and releasing the interlock, which is newly provided according to the present invention. FIG. 3 is a block diagram of an embodiment of the interlock generator 5 shown in FIG. 3, when initially describing the setting circuit of the interlock, 11 denotes a first mask register group for interlocking generating comprises a plurality of mask latch 11 ₀ to 11 _n, forcibly generate an interlock It is previously set n of bits of the mask data into n mask latch 11 ₀ to 11 _n for.

The mask output of the first mask register group 11 is given to an interlock setting condition detection circuit 13 which detects a compulsory interlock setting condition. Further, the internal signal groups A _{0 to} A _n of the vector processing device itself are also connected to the interlock setting detection circuit 13. Therefore, the interlock setting condition detection circuit 13 operates in the first mask register group 1
The interlock setting condition is detected by the logical sum of the logical products of the mask outputs from 1 and the internal signal groups A _{0 to} A _n, and the latch 17 is set to the interlock setting state.

Further, each mask output of the first mask register group 11 is input to the +1 circuit 15, and when the +1 circuit 15 receives the detection output from the interlock setting condition detection circuit 13, the value obtained by adding +1 to each mask output is newly added. Mask data of each mask latch 11 _{0 of} the first mask register group 11
To 11 _n to update the mask data. Further, the inverted output that becomes 1 when the latch 17 is reset is fed back to the interlock setting condition detection circuit 13, and the detection output is performed under the condition that the interlock 17 is in the reset state to perform the set operation. Let

Next, the interlock release circuit section of FIG. 3 will be described. Reference numeral 12 is a second mask register group for interlock release, and a plurality of mask latches 12 _{0 to} 12 _n.
And n for forcibly releasing the interlock
The mask data of bit is n mask latches 12 ₀ to 1
It is preset to 2 _n . The mask output of the second mask register group 12 is applied to the interlock release condition detection circuit 14 which detects a forced interlock release condition.
Further, the interlock setting detection circuit 14 is connected to other internal signal groups B _{0 to} B _n of the vector processing device itself.

Therefore, the interlock release condition detection circuit 1
Reference numeral 4 detects the interlock release condition by the logical sum of the logical products of the mask outputs from the second mask register group 12 and the internal signal groups B _{0 to} B _n, and resets the latch 17 to the interlock released state. Further, each mask output of the second mask register group 12 is input to the +1 circuit 16 and +1
When the circuit 16 receives the detection output from the interlock release condition detection circuit 14, the value obtained by adding +1 to each mask output is set as new mask data, and is given to each mask latch 12 _{0 to} 12 _n of the second mask register group 12. Update the mask data.

Further, the interlock release condition detection circuit 1
An output that becomes 1 when the latch 17 is set is fed back to 4, and the detection output is performed on condition that the interlock 17 is in the set state, and the reset operation is performed.
The internal signal groups A _{0 to} A _n of the vector processing device are changing every moment depending on the operating state. The interlock setting condition detection circuit 13 includes the internal signal groups A _{0 to} A _n and the internal signals A ₀ to A _n.
Generating an interlock condition by taking the logical sum of a plurality of logical product of the mask latch 11 ₀ to 11 _n mask signal from the first mask register group 11 corresponding to each of the A _n.

When the interlock setting condition detection circuit 13 detects the setting condition and produces an output, the latch 17 is set and notifies the data use unit 3 of FIG. 2 of the interlock. Since the interlock setting condition detection circuit 3 receives the inverted output of the latch 17,
The interlock is established only when is reset.

On the other hand, the interlock setting condition detection circuit 1
When the interlock is detected in 3, the mask output from the mask latches 11 _{0 to} 11 _n provided in the first mask register group 11 is incremented by +1 by the +1 circuit 15 and set in the mask latches 11 _{0 to} 11 _n. The mask data is updated and a new interlock setting condition is created.

On the other hand, the interlock release condition detection circuit 1
4 is similar to the interlock setting condition detection circuit 13,
The mask latches 12 _{0 to} 12 of the second mask register group 12
_The timing of releasing the compulsory interlock is detected by taking the logical sum of the logical outputs of the respective mask outputs of _{n and} the other internal signal groups B _{0 to} B _n generated in the vector processing device.

The interlock latch 7 is reset by the output of the interlock release condition detection circuit 4, and the interlock of the data use unit 3 is released. The interlock release condition detection circuit 14 establishes the release condition only when the latch 17 is in the set state. When the interlock is further released, the outputs from the mask latches 12 _{0 to} 12 _{n of} the second mask register group 12 are incremented by +1 by the +1 circuit 16 and set in the mask latches 12 _{0 to} 12 _n to update the mask data. ..

By the processing of the interlock generating unit 5 as described above, regardless of the presence / absence of a load instruction, and whether the load access unit and the data use unit are operating in a chained manner, it is aperiodic (random). Interlocks can be generated. Next, the overall operation will be described with reference to FIG. Normally, the interlock detector 4 recognizes a chained state between the preceding load instruction and the succeeding instruction that uses the data of the preceding load instruction. Interlock detector 4
When the chain operation is recognized, the number of data DN1 written to the vector register 2 by the preceding load instruction and the number DN2 of data read by the subsequent instruction from the vector register 2 are counted, and the data read by the subsequent instruction is the vector register 2 An interlock is detected at the time when it no longer exists (at the time when DN1 = DN2), and the stop of the read process of the vector register 2 and the stop of the process to the arithmetic unit 7 or the store access unit 6 of the data use unit 3 are notified. To do.

On the other hand, when the interlock generation circuit 5 becomes effective for the verification by running the test program, as shown in FIG.
As shown in the embodiment, the interlock is generated irregularly and the interlock detector 4 is notified. The interlock detector 4 receives the signal from the interlock generator 5 regardless of whether or not the load access unit 1 writes to the vector register, or whether or not the load instruction itself exists, and has no relation to the chain state. And an interlock is generated in the data use unit 3.

In the embodiment of FIG. 3, the mask register groups 11 and 12 for latching mask data are used for setting and releasing the interlock, but the internal signal group is used without using the mask data. A _{0 to} A _n and B _{0 to} B _n may be directly applied to the interlock setting condition detecting circuit 13 and the interlock releasing condition detecting circuit 14 to take an arbitrary logical condition, for example, a logical sum.

Further, as the mask register updating means, the mask data set in the mask register groups 11 and 12 is +
Although it is updated by one circuit 15 and 16, it may be updated by using a + N circuit in which the increment number N is arbitrarily set. Further, as the mask register updating means,
A similar function can be obtained by using a shift circuit or a random number circuit instead of the + N circuits 15 and 16.

[0034]

As described above, according to the present invention, in the vector processing device, a complicated timing similar to the interlock that occurs when the load access part and the data use part are chained by the execution of the program is provided. It is possible to generate a pseudo interlock regardless of the presence or absence of load instructions and chain status due to the running of the test program, and the circuit that controls the interlock can be verified early and the reliability of verification can be improved. Can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment showing the overall configuration of the present invention.

FIG. 3 is a block diagram of an embodiment of an interlock generator of FIG.

FIG. 4 is an explanatory diagram of a conventional device.

[Explanation of symbols]

1: load access unit 2: vector register 3: data use unit 4: interlock detection unit 5: interlock generation unit 6: store access unit 7: operation unit 8: main memory unit (MSU) 11: for interlock generation First mask register group 12: Second mask register group for releasing interlock 11 _{0 to} 11 _n , 12 _{0 to} 12 _n : Mask latch 13: Interlock setting condition detecting circuit 14: Interlock releasing condition detecting circuit 15, 16 : +1 circuit 17: Interlock latch

Claims (4)

[Claims] 1. A vector register (2), a load access unit (1) for transferring data from a main memory (8) to the vector register (2), and reading data from the vector register (2). And a data use unit (3) for performing processing, wherein the load access unit (1) executes a vector operation without waiting for completion of a load instruction to the vector register (2) being executed by the load access unit (1). It is possible to perform a chain process in which the data use unit (3) performs processing using the data written in the register (2), and further, data can be supplied from the load access unit (1) to the vector register (2). When the data read from the vector register (2) to the data use unit (3) is lost, the data use unit (3) is lost.
In a vector processing device provided with an interlock detection unit (4) for interlocking a memory, a chain process of a load access unit (1) and a data use unit (3) for the vector register (2), and the load access Regardless of whether or not data is supplied from the unit (1) to the vector register (2), an interlock generation unit (5) for interlocking the data use unit (3) from the outside is provided, and an interlock period and an interlock period are provided. A vector processing device characterized by dynamically changing a lock release period. 2. The vector processing device according to claim 1, wherein the interlock generation unit (5) is a first mask register for interlock generation, which stores predetermined mask data, as an interlock setting unit. Group (11), each mask output of the first mask register group (11) and the internal signal group (A _{0 to} A) of the vector processing device itself.
_n ) and an interlock setting condition detection circuit (13) for setting a latch (17) by taking the logical sum of the logical product with _n ), and as an interlock releasing section, an interlock releasing section for storing predetermined mask data is provided. A second mask register group (12), each mask output of the second mask register group (12), and another internal signal group (B _{0 of the} vector processing device itself).
~ B _n ) and the logical sum of the logical product output and the latch (1
7. A vector processing device comprising an interlock release condition detection circuit (14) for resetting 7). 3. The vector processing device according to claim 2, wherein a mask register update for updating the mask data set in the first mask register group (11) for interlock generation provided in the interlock setting unit. As means, there is provided a first + N circuit (15), a shift circuit or a random number circuit for updating to a value incremented by a predetermined number N each time the interlock latch is set, and the interlock setting canceling section. As a mask register updating means for updating the mask data set in the second mask register group (12) for releasing the interlock provided in, the value incremented by a predetermined number N every time the latch (17) is reset. Second + N to update to
A vector processing device comprising a circuit (16), a shift circuit or a random number circuit. 4. The vector processing device according to claim 1, wherein the interlock generating unit (5) serves as an interlock setting unit for the internal signal group (A _{0 to} A _n ) of the vector processing device itself. An interlock setting condition detection circuit (13) for setting the latch (17) by taking an arbitrary logic is provided, and as an interlock release unit, another internal signal group (B _{0 to} B _n ) of the vector processing device itself is provided. An interlock release condition detection circuit (14) for resetting a latch (17) by taking an arbitrary logic, and a vector processing device.