JPH051157Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a timer device, and particularly to a timer device suitable as means for automatically stopping power supply to a hot-wire rear window of an automobile.

[Prior Art] Various types of timer devices or timer circuits have been known in the past, but in the case of a timer device used as a means for automatically stopping power supply to a hot-wire rear window of an automobile, there are the following: There are control conditions that are required in relation to vehicles and drivers. In other words, in order to ensure rearward visibility of automobiles, the rear window is equipped with a hot wire, that is, an electric heater (hereinafter simply referred to as a heater), and the load current of the heater is large and the power consumption is large. It is necessary to operate the switch frequently, and forgetting to turn the switch off results in a large power loss. For this reason, a timer device is installed that automatically stops the power supply after a predetermined time after the switch is turned on.
First of all, it is of course necessary that the switch be stopped reliably after a predetermined period of time has elapsed, and secondly, consideration must be given to the operability of the switch so as not to interfere with the operation of the vehicle.

For example, the conventional timer circuit shown in Fig. 5 controls the heater power supply relay L ₁ by using the time for the charge accumulated in the capacitor C ₁ to discharge. Compared to conventional timers, there is no risk that the timer will stop, and the timer will surely stop due to discharge. Therefore, the former requirement is satisfied.

However, in the case of the above-mentioned timer circuit, a switch is required for setting and canceling the timer as described in Japanese Utility Model Application Publication No. 59-20732.
Since it is necessary to switch the operating direction of SW ₁ , there is a risk of erroneous operation. For this reason, the timer circuit described in this publication uses a combination of a one-way switch and a flip-flop to enable setting and cancellation of the timer circuit, and to prevent chattering. However, regarding this timer circuit,
The power consumption when the circuit is off is large, and the capacitor is charged and discharged repeatedly during operation, which may shorten the life of the capacitor. and,
The circuit configuration is complicated.

On the other hand, with the recent progress in integrated circuit technology, general-purpose timer ICs have become widespread, and by using these timer ICs, timer devices can be created with a simple configuration.

Figure 6 is for a timer commonly known as 555.
This is a block diagram of an IC, and this timer IC555 usually has a capacitor C _p and a resistor R _p as shown in Figure 6.
is connected. That is, when constant voltage Vcc is applied to the circuit, capacitor C _p starts charging via resistor R _p . Capacitor C _p is the first comparator CM
When the voltage at the inverting input terminal of No. 1 is charged to the reference voltage 2/3Vcc determined by the three resistance division ratios and applied to the non-inverting input terminal via the threshold terminal P6, the first comparator CM1 outputs and resets the RS flip-flop FF. As a result, a high (H) level signal is output from the terminal, the output terminal P3 becomes low (L) level, and the transistor TR0 becomes conductive, so that the capacitor C _p is discharged via the discharge terminal 7. Therefore, the charging time until the capacitor C _p reaches the reference voltage 2/3 Vcc is the time during which an H level signal is output from the output terminal P3. Note that P1 is a ground terminal, P2 is a trigger terminal, P4 is a reset terminal, and P5 is a control terminal.

[Problems to be solved by the invention] However, if a timer device is created using a timer IC as described above, the charging time of the capacitor will be the timer time, so the charging time will be longer due to repeated charging and discharging. Or, depending on the usage situation, the timer device may not stop. Therefore, as mentioned above, it is preferable to use the discharging time of the capacitor in a timer device for a rear window with heated wire, but in the case of the above-mentioned timer IC, the initial charging voltage of the capacitor C _p Setting is difficult, and there remains a problem in ensuring reliable inversion operation of the RS flip-flop when discharge is complete. Further, even if the one-way switch described above is applied to a timer IC, new problems arise, and simply combining these cannot be applied to a timer device for a heated rear window of an automobile.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a timer device which can set and cancel a timer by operating a switch in the same direction, and which has a simple circuit configuration, consumes little power, and performs stable timer operation.

[Means for Solving the Problems] In order to solve the above-mentioned problems and achieve the above objectives, the present invention adopts the following configuration.

That is, the timer device of the present invention takes either a first state or a second state in response to an input signal, and outputs a signal having a different level between the first state and the second state; a first comparison means inputting a first input signal and comparing it with a first reference value; and inverting the output means to a second state when the first input signal exceeds the first reference value; is input and compared with a second reference value which is lower than the first reference value, and when the level is lower than the second reference value, the output means is switched to the first reference value.
a first comparison means interposed between the comparison determination means and the output means and turned on by a one-way operation;
It has a contact mechanism and a second contact mechanism, and when the first contact mechanism is off, the first comparison means maintains the first reference value, and when the first contact mechanism is turned on, the output signal of the output means is a switch means which inputs the value into the first comparison means and replaces it with the first reference value; a second contact mechanism; and an output signal of the output means is introduced from the input end through the switch means to reach a predetermined value. A signal corresponding to the accumulated value is output from the input terminal to the first comparing means as the first input signal, and is released at a predetermined time by turning off the second contact mechanism. a delay means for outputting the second input signal to the means; and a delay means interposed between the output means connected via the second contact mechanism and the input end of the delay means, and the second contact mechanism first setting means for setting the predetermined value to a level lower than the high-level output signal of the output means and higher than the first reference value in response to the ON operation of the first setting means; second setting means for maintaining the output signal output as the second input signal to the second comparison means at a predetermined value lower than the second reference value after completion of release of the signal accumulated in the means; It is prepared.

[Operation] In such a timer device, when setting the timer, the first contact mechanism and the second contact mechanism are turned on by operating the switch means in one direction, thereby first setting the high level of the output means of the comparison judgment means. The output signal is input to the first comparing means and replaced with the first reference value, and is also input to the delay means via the first setting means and the second contact mechanism. The input signal of this delay means is set by the first setting means to a predetermined value lower than the high level output signal but higher than the first reference value. Then, by turning off the switch means, the first comparison means is returned to the first reference value, and the delay means starts outputting a signal corresponding to the accumulated value, and this output signal is sent to the first comparison means to return the first reference value to the first reference value. Input as an input signal. Therefore, this input signal is definitely determined to be at a higher level than the first reference value in the first comparing means, and the outputting means is determined to be at a higher level than the first reference value.
The state is reversed and the output signal is low level.

On the other hand, the output signal of the delay means is also input to the second comparison means as a second input signal, and the output means maintains the second state as long as the signal is equal to or greater than the second reference value. Then, when a predetermined period of time has elapsed and the output signal corresponding to the accumulated value of the delay means falls below the second reference value, the output means is inverted to the first state and becomes a high level output signal. As described above, the timer operation is started by the ON operation of the first contact mechanism and the second contact mechanism of the switch means, and after the OFF operation, the low level output signal of the output means is inverted to a high level after a predetermined period of time has elapsed. Timer operation completes.

If you want to cancel the timer operation midway through, operate the switch means in the same direction as when setting the timer, and first, when the first contact mechanism and the second contact mechanism are turned on, the output means is at a low level, so the output is accumulated in the delay means. signals are emitted all at once. Next, when the operation of the switch means is released, the first contact mechanism and the second contact mechanism are turned off, and the output signal of the delay means is compared with the first reference value and the second reference value, the output signal is Since the signal is at a low level, it falls below the second reference value and the output means is inverted to the first state. Therefore, the timer operation is interrupted. In this case, due to the relationship between the first comparison means, the second comparison means, and the switch means, when the switch means is operated, the output means may enter the second state and malfunction. The second
Since the predetermined value is maintained at a lower level than the second reference value of the comparison means, the timer operation can be reliably interrupted without malfunction.

[Embodiments] Hereinafter, preferred embodiments of the timer device of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, in which a heater L is installed in the rear window and has one end grounded.
The other end is connected to a power supply +B via a relay RY and an ignition switch (not shown), and the relay RY that controls the energization of this heater L is energized for a predetermined time, thereby supplying power to the heater L for a predetermined time. ,
Its heat generation action removes fog from the rear window.

In this embodiment, the well-known timer IC "555" (hereinafter simply referred to as timer IC) 10 is used as the comparison and determination means referred to in the present invention, and the switching means is a non-locking two-circuit push-type delay switch (hereinafter referred to as "timer IC"). (simply referred to as a delay switch) 20. That is, it is a non-lock type push switch that remains in a predetermined position only when a knob (not shown) is pressed and returns to its original position when the pressing force is removed, and two circuits are controlled on and off by two switches. One switch turns on with a delay from the other switch and turns off before the other. The general structure of this delay switch 20 will be described later, but its specific structure is described in Utility Application No. 111244/1989 filed by the applicant of the present invention. A delay means 30 consisting of a parallel circuit of a capacitor C1 and a resistor R3, a first setting means 40 including resistors R1 and R2, and a Zener diode ZD
A second setting means 50 including 2 is provided.

One end of the heater L is grounded, and the other end is the relay RY.
It is connected to the power supply +B by an ignition switch (not shown) through the contacts of the ignition switch (not shown). relay
A parallel circuit of the coil of RY, the diode D1, and the Zener diode ZD1 is connected to the power supply +B via a resistor R4, and is also connected to the output terminal P3 of the timer IC10. Thus, a constant voltage Vcc is obtained at the connection point between the resistor R4 and the Zener diode ZD1, and is connected to the power supply terminal P8 and reset terminal P4 of the timer IC 10 to supply the constant voltage Vcc.

In the timer IC 10, the constant voltage Vcc supplied to the power supply terminal P8 is divided between it and the ground terminal P1 by three resistors RO having the same resistance value, and a first reference value, which is the first reference value according to the present invention, is divided between the constant voltage Vcc and the ground terminal P1. The connection point that outputs the voltage 2/3 Vcc is connected to the control terminal P5 and the inverting input terminal of the first comparator CM1, which is the first comparison means according to the present invention, and outputs the second reference voltage 1/3 Vcc, which is the second reference value. The connection point is connected to a non-inverting input terminal of a second comparator CM2, which is a second comparison means. The non-inverting input terminal of the first comparator CM1 is connected to the threshold terminal P6, and the second
The inverting input terminal of comparator CM2 is connected to trigger terminal P2. The output terminals of the first and second comparators CM1 and CM2 are connected to the reset terminal R and the set terminal S of the RS flip-flop FF, respectively. The output terminal of the RS flip-flop FF is connected to the output terminal P3 via an inverter, the collector is connected to the discharge terminal P7, and the emitter is connected to the base of a grounded transistor TR0.

Thus, the RS flip-flop FF and the inverter constitute the output means according to the present invention, and when the RS flip-flop FF is in the set state, an H (high) level voltage signal is output from the output terminal P3, and the RS flip-flop FF When is reset, an L (low) level signal is output. still,
In this embodiment, the constant voltage Vcc is supplied to the reset terminal P4 as described above, and no reset occurs as long as it is connected to the power supply +B.

The delay switch 20 has first fixed contacts 21a, 21
b and a first movable contact 21c and constitute a first contact mechanism, and a second fixed contact 2
2a, 22b and a second movable contact 22c constituting a second contact mechanism, the first movable contact 21c and the second movable contact 22
c in conjunction with the first fixed contacts 21a, 21, respectively.
b. It is configured to slide on the second fixed contacts 22a, 22b. The first fixed contact 21a is the first
The movable contact 21c and the second fixed contact 22a are in constant contact with the second movable contact 22c, respectively, and the first fixed contact 2
1b is set longer than the second fixed contact 22b. Therefore, the first and second movable contacts 21c, 22
When c slides from the stop position, first the first fixed contact 21b contacts the first movable contact 21c and conducts with the first fixed contact 21a, and then the second fixed contact 22b contacts the second movable contact 22c. second fixed contact 22
When conducting with a and returning to the stop position, the order of opening is the opposite. In addition, the first and second movable contacts 21c, 2
2c is provided with an automatic return mechanism (not shown), and after the first and second movable contacts 21c and 22c are pressed and slid, they automatically return to the original stop position when the pressing force is removed. Configured to return.

The output terminal P3 of the timer IC 10 is connected to the first fixed contact 21b, and the control terminal P5 is connected to the first fixed contact 21a, so that the first movable contact 2
The output terminal P3 and the control terminal P5 are electrically connected and disconnected by sliding of the terminal 1c. Further, the output terminal P3 of the timer IC 10 is connected to the second fixed contact 22a via the resistor R1 of the first setting means 40, and the resistor R2 of the first setting means 40 has one end connected to the resistor R1 and the second fixed contact 22a. The other end is grounded via a diode D2. Therefore, the voltage Vcc output from the output terminal P3 is divided by the first setting means 40 into R ₂ /R ₁ +R ₂ Vcc (where R ₁ and R ₂ are the resistance values of the resistors R1 and R2). It is supplied to the second fixed contact 22a.

Note that the values of R _{1 and R 2 are set according to the timer time so that R 2 /} R ₁ +R ₂ Vcc becomes 2/3 Vcc or _more .

The threshold terminal P6 of the timer IC10 is the second
The second fixed contact 22b is connected to the fixed contact 22b.
One end of a capacitor C1 constituting the delay means 30 is connected to. The other end of capacitor C1 is grounded via diode D2, and capacitor C1
A discharging resistor R3 is connected in parallel to the resistor R3. The ground terminal P1 of the timer IC 10 is similarly grounded via the diode D2.

Further, one end of the capacitor C1 is connected to the second setting means 50.
Timer IC via barrel Zener diode ZD2
10 trigger terminal P2. The Zener voltage of the Zener diode ZD2 is set to a predetermined value lower than 1/3 Vcc of the second reference voltage. Incidentally, a light emitting diode LED1 for an indicator when the relay RY is activated is connected to the discharge terminal P7 of the timer IC10 via a resistor R5 to a connection point between the Zener diode ZD1 and the resistor R4. Furthermore, a dimming circuit 60 is connected to the connection point between the light emitting diode LED1 and the resistor R5. That is, a light emitting diode LED for lighting is connected between the input terminal TL, to which the power +B voltage is supplied when the tail lamp (not shown) is turned on, and the diode D2.
2 is provided in parallel with a series circuit of a resistor R7 and a transistor TR1, and a Zener diode ZD.
3 is connected. The base of transistor TR1 is resistor R7, and the emitter is a light emitting diode.
Each is connected to the cathode of LED2, and the collector is connected to the resistor R5 and the light emitting diode through the resistor R6.
Connected to the connection point of LED1.

Regarding the first embodiment having the above configuration, the initial state,
The operations at the time of set (start of timer operation), time-up (completion of timer operation), and cancel (interruption of timer operation) will be explained with reference to the time charts of FIGS. 2 and 3.

First, in the initial state when the ignition switch (not shown) is turned on and connected to the power supply +B (the delay switch 20 is in the state shown in FIG. 1), the timer is activated.
Since there is no input signal to the trigger terminal P2 and threshold terminal P6 of IC10, the RS flip-flop
Since FF is in the set state and the output signal of output terminal P3 is at H level (approximately Vcc), the relay is activated.
RY is not driven (at time t0, h in Figure 2). Furthermore, even if there is a fluctuation in the temporary H level, the relay RY will not malfunction due to the presence of the diode D1.

Next, at the time of setting, the first and second movable contacts 21c, 22c of the delay switch 20 are switched from this state.
When the first fixed contacts 21a and 21
b becomes conductive (at this time, the second fixed contacts 22a,
22b is open). As a result, the output terminal P3 and the control terminal P5 are brought into conduction, and the inverting input terminal of the first comparator CM1 becomes H level, that is, the potential is approximately Vcc via the control terminal P5. Therefore, the initial state is maintained (time t1 in FIG. 2a). In FIG. 2, at t1, the first switch 21 is on, at t2, the second switch 22 is on, and at t3, the second switch 22 is on.
is off, t4 is the first switch 21 is off, and t9
indicates the timing of completion of timer operation.

When the first and second movable contacts 21c and 22c are further slid, the first fixed contacts 21a and 21b are electrically conductive and the second fixed contacts 22a and 22b are electrically conductive. As a result, the output terminal P3 is electrically connected to the threshold terminal P6 via the first setting means 40 and also to the capacitor C1.

Therefore, the potential of the non-inverting input terminal of the first comparator CM1 is R ₂ /R ₁ +R ₂ Vcc, which is lower than the potential Vcc of the inverting input terminal, and the trigger terminal P2 is lower by the forward voltage of the Zener diode ZD2. are at substantially the same potential and are 1/3 Vcc or more, so the initial state is still maintained (at time t2 in Figure 2b).

On the other hand, the capacitor C1 is charged until it reaches the above-mentioned R ₂ /R ₁ +R ₂ Vcc. The setting is completed by charging the capacitor C1, and the first and second movable contacts 21
When c and 22c are released and begin to automatically return to their original positions, the timer starts operating.

That is, when the delay switch 20 is reset, the second fixed contacts 22a and 22b are first opened, and the charge accumulated in the capacitor C1 starts discharging via the resistor R3, and the charge is discharged according to the time constant of the capacitor C1 and the resistor R3. It gradually discharges. The rest is still the same as the initial state. And the first fixed contact 21a,
When 21b is opened, the control terminal P5 is opened,
The potential of the inverting input terminal of the first comparator CM1 becomes 2/3 Vcc (at time t4 in FIG. 2a). At this time, the potential of the non-inverting input terminal, that is, the potential of the threshold terminal P6 is the potential of the capacitor C1, and is 2/3.
It is at a higher level than Vcc (at time t4 in Figure 2b). Therefore, the first comparator CM1 outputs an output, the RS flip-flop FF is reset (R), and the output from the output terminal is inverted (time t4 in FIGS. 2c and d).
Therefore, the output of the output terminal P3 becomes L level, and a potential difference is created in the coil of the relay RY, and the relay RY is driven and power is supplied to the heater L (time t4 in FIG. 2h).
Note that as shown in h in Figure 2, the output of output terminal P3 is not necessarily 0, and a certain amount of potential (for example, about 1 volt) remains depending on the IC components, etc., but this does not cause problems in the operation of relay RY. do not have.

When a predetermined period of time elapses from the start of discharging the capacitor C1, a time-up occurs. That is, when the potential of the capacitor C1 decreases due to discharge and the potential of the trigger terminal P2 falls below the potential 1/3 Vcc of the non-inverting input terminal of the second comparator CM2, the second comparator CM2 outputs and the RS flip-flop FF is set (S). (t9 of e, f, g in Figure 2)
Time). As a result, the output of the output terminal P3 is reversed to H level, the relay RY is deactivated, and the power supply to the heater L is cut off (time t9 in Fig. 2h).

As described above, if the capacitor C1 is discharged and the potential of the trigger terminal P2 falls below 1/3 Vcc, a time-up occurs, but when canceling, the potential of the trigger terminal P2 is set to a level lower than 1/3 Vcc and above a predetermined value. It becomes necessary to maintain the Therefore,
A Zener diode ZD2 whose Zener voltage is this predetermined value is provided as a second setting means, and the reason thereof will be explained below along with its operation at the time of cancellation.

When canceling the timer device, that is, when the delay switch 20 is activated before the capacitor C1 starts discharging and completes discharging, the output of the output terminal P3 becomes L level before the potential of the trigger terminal P2 reaches 1/3 Vcc. It is in. Therefore, in this state, the switch means 20 is operated, and first the first fixed contacts 21a, 2
When 1b becomes conductive, the control terminal P5 becomes conductive with the output terminal P3, and the inverting input terminal of the first comparator CM1 becomes L level (for example, about 1V). Subsequently, when the second fixed contacts 22a and 22b are brought into conduction, the threshold terminal P6 is brought into conduction with the output terminal P3 which is at the L level, and becomes the L level at once. In this state, the control terminal P5, the threshold terminal P6, and the trigger terminal P2 are all electrically connected to the L level output terminal P3. At this time, since the inverting input terminal of the first comparator CM1 is at the L level, the second reference voltage at the non-inverting input terminal of the second comparator CM2 is 1/2 of the L level (approximately 1V), that is, approximately
0.5V, and if we remove the Zener diode ZD2, the L level, or approximately 1V, can be secured because the trigger terminal P2 is electrically connected to the output terminal P3, and therefore, theoretically, the second comparator CM
2 is not activated and the current state can be maintained. Therefore, when proceeding from this state to the next operation of the delay switch 20, first the second fixed contacts 22a,
22b is disconnected, and the trigger terminal P2 is connected to the capacitor C.
1 potential (approximately 1V), and further the first fixed contact 2
When 1a and 21b are opened, the control terminal P5 is opened, so that the first reference voltage returns to 2/3Vcc and the second reference voltage returns to 1/3Vcc. Therefore the second comparator
RS because the potential of the non-inverting input terminal (1/3Vcc) of CM2 is higher than the potential of the inverting input terminal, approximately 1V.
The flip-flop FF is set (S), and the output terminal P3 becomes H level, completing the timer operation.

However, in the above region where the potential is low, the operation of the timer IC10 becomes unstable, especially when the control terminal P5 becomes L level, even though the potential of the trigger terminal P2 is higher than the potential of the non-inverting input terminal of the second comparator CM2. 2nd comparator
It has been experimentally confirmed that CM2 is activated and malfunction occurs. Therefore, the trigger terminal P
2, a Zener diode ZD2 is connected to the second reference voltage 1/3Vcc (for example,
4V) is maintained at a lower level potential (for example, 3V). By doing this, when the control terminal P5 becomes L level during the cancel operation described above, the second comparator
The inverting input terminal side of CM2 is reliably maintained at a high level, and the above-mentioned operation is performed smoothly.

A time chart of the above operation is shown in Figure 3.
In FIG. 3, t5 indicates the timing when the first switch 21 is on, t6 indicates the timing when the second switch 22 is on, t7 indicates the timing when the second switch 22 is off, and t8 indicates the timing when the first switch 21 is off.

Regarding the operation of the indicator light emitting diode LED1, when the output terminal P3 becomes L level, the transistor TR0 turns on and the resistor R5
A current is supplied to the light emitting diode LED1 through
is being heated.

In addition, when the dimming circuit 60 lights up the rear illumination light (not shown), voltage is supplied to the TL terminal and the illumination light emitting diode LED2 lights up, and at the same time, TR1 is turned on and the current flowing to the light emitting diode LED1 flows through the resistor R6. The current flowing through the light emitting diode LED1 is therefore reduced, resulting in so-called dimming.

As described above, according to the first embodiment, the device consumes less power, and since the discharge of the capacitor C1 is used, there is no risk that the timer device will not stop, and when the timer is set, the resistor R ₁ ,
Not only can the potential of the threshold terminal P6 be set accurately by _R2 , but also the potential of the trigger terminal P2 is maintained at a predetermined value by the Zener diode ZD2 during canceling, so that the operation during canceling is also reliable. Moreover, the delay switch 20
Because it utilizes the system, set and reset (cancel) operations are reliable and there is no risk of malfunction. or,
The parts structure is simple, the number of parts is small, and it can be manufactured at low cost. Furthermore, when using the timer IC, a light emitting diode LED1 for indicator is added.
Since the discharge terminal P7 is used as a switch, a driver circuit is not required.

Figure 4 shows the second embodiment of the present invention.
The same parts as those in the embodiment are given the same reference numerals. The main difference between the second embodiment and the first embodiment is that the first embodiment uses a delay switch 2 as a switching means.
0 is used, a normal automatic reset type switch 70 is used, and a diode D3 is used in place of the Zener diode ZD2.

First, the switch 70 is of an automatic return type and may be of any type, such as an opposing contact switch or a sliding switch, and has a common fixed contact 70b and a first fixed contact 7.
1a to form a first contact mechanism, and a second movable contact 72c to open and close common fixed contact 70b and second fixed contact 72a to form a second contact mechanism. , the second movable contacts 71c and 72c are configured to interlock with each other. Then, the first fixed contact 71a is connected to the timer IC1.
0 output terminal P3, and the second fixed contact 72
a is connected to the threshold terminal 6 of the timer IC 10 via a voltage dividing circuit of resistors R1 and R2 and a diode D4, and is also connected to a parallel circuit of a capacitor C1 and a resistor R3 and a trigger terminal P2. Common fixed contact 70b is timer IC10
The anode side is connected to the control terminal P5 of
4) is connected to the cathode side of diode D3. Therefore, this diode D3 is not only used for discharging the capacitor C1, but also has the functions of both the first setting means and the second setting means according to the present invention. The coil of relay RY is equipped with a stabilizing Zener diode ZD3.
The rest of the configuration is the same as the first embodiment, so the explanation will be omitted.

Next, the operation of the second embodiment configured as described above will be explained. In the initial state, as in the first embodiment, the output of output terminal P3 is at H level (approximately Vcc), and the relay
RY is not driven.

At the time of setting, when the switch 70 is activated and the first and second movable contacts 71c and 72c contact the first fixed contacts 71a and 72a, first the control terminal P5
conducts with the output terminal P3, and the potential rises to H level. Note that when the first and second movable contacts 71c and 72c are interlocked and actuated simultaneously, they will come into contact with the first and second fixed contacts 71a and 72a, respectively, but they will not be at the same time and only one of them will. Become the first. In this case, even if the temporary second movable contact 72c contacts the second fixed contact 72a first, the H level output of the output terminal P3 is supplied from the first fixed contact 71a, so the second fixed contact 72a Current does not flow first to the side. That is, as far as the output of the output terminal P3 is concerned, the second fixed contact 72a side will be output later.

Therefore, after the control terminal P5 is electrically connected to the output terminal P3, the H level output of the output terminal P3 is divided by the resistors R1 and R2, and the voltage drop of the diode D4 is subtracted and then supplied to the threshold terminal P6. Ru. At this time, although the control terminal P5 has a higher potential, no current flows to the threshold terminal P6 side due to the presence of the diode D3. At the same time, charging of the capacitor C1 starts and is charged until it reaches the potential of the threshold terminal P6. Note that since the trigger terminal P2 has a higher level than the non-inverting input terminal of the second comparator CM2, it is not activated.

Next, when the switch 70 is released and the first and second movable contacts 71c and 72c automatically return, the control terminal P
5 is open, and the first reference voltage of the first comparator CM1 becomes 2/3Vcc. At this time, the threshold terminal P6 becomes 2/2 due to the charging voltage of the capacitor C1.
Since the voltage exceeds 3Vcc, the first comparator CM1 outputs an output, and the RS flip-flop FF is reset (R), so that the output of the output terminal P3 is inverted and becomes L level. In this case, since the diode D3 is connected between the control terminal P5 and the threshold terminal P6, the latter is always set to a higher level than the former by the forward voltage Vf (for example, about 0.7V) of the diode D3. , therefore the first comparator CM
1 will definitely output.

Then, the charge accumulated in the capacitor C1 is gradually discharged, and the potential of the trigger terminal P2 becomes 1/3
When the voltage falls below Vcc, the second comparator CM2 outputs an output, the RS flip-flop is set (S), and the output of the output terminal P3 is inverted and becomes H level, completing the timer operation.

At the time of cancellation, the switch 70 is operated with charge accumulated in the capacitor C1, and as described above, the second fixed contact 72a is activated.
At the same time or first, the first fixed contact 71a is turned on. In this case, since the output of the output terminal P3 is at L level, the potential of the control terminal P5 is also at L level.
Then, the charge accumulated in the capacitor C1 will be discharged from the control terminal P5 side via the diode D3. At this time, diode D4 prevents discharge from resistor R2.

When the capacitor C1 completes discharging, the L level of the control terminal P5 changes to the first comparator CM1.
The potential of the inverting input terminal of the second comparator CM2 becomes the potential of the non-inverting input terminal of the second comparator CM2, and the potential of the trigger terminal P2 becomes a problem.
At this time, the potential of the trigger terminal P2 is the control terminal P5.
is higher than the potential by the forward voltage Vf of the diode D3, and the second comparator CM2 does not operate. That is, when switch 70 is activated, RS flip-flop FF is not inverted.

When the switch 70 is opened, that is, the first and second movable contacts 71c and 72c are automatically reset, the second reference voltage of the second comparator CM2 becomes 1/3 Vcc, so the potential on the trigger terminal P2 side is at a lower level. Then,
The second comparator CM2 outputs an output, and the RS flip-flop FF is set (S), so that the output of the output terminal P3 becomes H level, and the timer operation ends. According to this embodiment, the same effects as in the first embodiment can be obtained using a normal switch instead of a delay switch.

[Effects of the invention] As described above, according to the timer device of the invention,
Since the switch means only needs to be operated in the same direction when setting and canceling the timer, there is no risk of erroneous operation, and in both cases, the first setting means and the second setting means ensure that the timer operation is started and finished. You can get the effect that you can. In particular, in the present invention, when canceling the timer operation midway through, the timer operation is interrupted by operating the switch means in one direction and then releasing it, and even if the switch means is continued to be operated, the signal of the delay means will not be activated. is released, the timer operation does not start again, and stable timer operation can be ensured. Furthermore, the circuit configuration can be simplified and consume less power than the conventional technology. For example, as a specific example, it is possible to apply a timer IC as described above, which also provides the effects of reducing the number of parts and reducing costs.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the timer device according to the first embodiment of the present invention, Fig. 2 is a time chart showing the operation of the timer device when it is set, and Fig. 3 is a time chart showing the operation of the timer device when it is cancelled. 4 is a circuit diagram of a timer device according to the second embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional timer circuit, and FIG. 6 is a circuit diagram of a timer device using a conventional timer IC. It is a diagram. 10...Timer IC (comparison/judgment means), P1...
Ground terminal, P2...Trigger terminal, P3...Output terminal, P4...Reset terminal, P5...Control terminal,
P6...Threshold terminal, P7...Discharge terminal,
P8...Power supply terminal, CM1...First comparator (first comparing means), CM2...Second comparator (second comparing means), FF...RS flip-flop (output means), 20...Delay switch (switching means) ), 21...first switch, 21a...first fixed contact, 21b...first fixed contact, 21c...first movable contact, 22...second switch, 22a...
Second fixed contact, 22b...Second fixed contact, 22c
...Second movable contact, 30...Delay means, 40...
First setting means, 50... Second setting means, 60...
Dimming circuit, 70... switch (switch means),
L...Heater, RY...Relay, +B...Power supply.

Claims (1)

[Claims for Utility Model Registration] (1) An output that takes either a first state or a second state according to an input signal and outputs a signal with different levels of height in the first state and second state. means and
a first comparing means inputting a first input signal and comparing it with a first reference value, and inverting the output means to a second state when the first reference value is exceeded;
a second reference value which inputs the input signal and compares it with a second reference value having a lower level than the first reference value, and inverts the output means to the first state when the input signal falls below the second reference value; a first contact mechanism and a second contact mechanism that are interposed between the comparison and determination means and the output means and are turned on by operation in one direction; When the first contact mechanism is off, the first comparing means
switch means for maintaining a reference value of and inputting an output signal of the output means to the first comparison means to replace the first reference value by turning on the first contact mechanism; The output signal of the output means is introduced from the input end and accumulated until it reaches a predetermined value, and is released at a predetermined time by turning off the second contact mechanism, so that a signal corresponding to the accumulated value is transmitted from the input end to the first The first input signal is outputted to the comparison means, and the second
a delay means for outputting the second input signal to the comparison means; and a delay means interposed between the output means connected via the second contact mechanism and the input end of the delay means, and the second contact a first setting means for setting the predetermined value to a level lower than the high level output signal of the output means and higher than the first reference value in response to the ON operation of the mechanism; a second setting means for maintaining an output signal outputted as the second input signal to the second comparison means at a predetermined value lower than the second reference value after completion of release of the signal accumulated in the delay means; A timer device comprising: (2) The switch means includes a first switch and a second switch that is interlocked with the first switch and closes with a delay and opens in advance of the first switch, The output means are commonly connected to the input terminal of the first comparison means for setting the first reference value through a switch, and the first setting means is connected to the input terminal of the delay means through the second switch. the first setting means is connected to the input end, and the first setting means is connected to the output means, and the first setting means is connected to the output means.
2. The timer device according to claim 1, wherein the setting means includes a plurality of resistors that divide the output of the output means at a predetermined ratio. (3) The timer device according to claim 2, wherein the second setting means is a Zener diode interposed between the input terminal of the delay means and the second comparison means. . (4) The switch means has a common fixed contact, a first movable contact that is connected to and disconnected from the first fixed contact, and a first movable contact that is disconnected and disconnected from the second fixed contact and that operates in conjunction with the first movable contact. a switch having two movable contacts, the common fixed contact being commonly connected to an input terminal for setting the first reference value of the first comparing means, and the first fixed contact being connected to the output means. and the second fixed contact is connected to the input end of the delay means via the first setting means, and the first setting means and the second setting means connect the anode side to the input end of the delay means. 2. The timer device according to claim 1, further comprising a diode whose cathode side is connected to the common fixed contact. (5) The timer according to any one of claims 1 to 4, wherein the delay means comprises a capacitor and a resistor for discharging the charge accumulated in the capacitor. Device.