JPH051183Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field This invention is intended for use in audio intermediate frequency signals (SIF
signal) related to demodulation circuits.

(b) Prior art A plurality of different television signals, e.g.
In the PALB/G method and the PALI method, the carrier frequencies of the SIF signals are different, 5.5MHz and 6.0MHz, respectively.
Devices that can receive these television signals (television receivers, video tape recorders (VTRs), etc.) need to distinguish between SIF signals. Based on this determination, trap switching in the VIF circuit and display to the user are performed.

FIG. 3 shows a conventional SIF signal discrimination circuit. 1
0 is f1 (e.g. 5.5MHz) or f2 (e.g.
6.0MHz) SIF signal input terminal, 12 is a demodulation circuit for FM demodulating the SIF signal, 1
4 is an audio signal output terminal. 16 is one SIF
A bandpass filter (BPF) that allows only the signal to pass, 18 is an amplifier circuit, 20 is an AM detection circuit,
22 is a discrimination circuit, and 24 is an SIF signal discrimination result output terminal.

In the above circuit, only one SIF signal is passed through the BPF 16, this signal is amplified by the amplifier circuit 18, and it is subjected to AM detection. Based on the presence or absence of this AM detection output, the frequency (f1 or f2) of the input SIF signal is determined.

However, since the above circuit discriminates SIF signals by AM detection, it is susceptible to noise and is prone to malfunction, especially in areas with weak electric fields.

For this reason, there is a method disclosed in Japanese Patent Application Laid-Open No. 171180/1983. That is, two different frequencies of SIF
The signal is discriminated based on the output of an FM detection circuit that can obtain different outputs.

However, in this Japanese Patent Application Publication No. 58-171180,
2 FM detection circuits for SIF discrimination and FM detection circuits for demodulating SIF signals and obtaining audio signal output.
The configuration is complicated.

For this reason, the applicant has filed an application for utility model registration (11) filed on March 12, 1985 (Utility model registration application 147968
In ``SIF signal discrimination circuit'', we proposed a circuit that performs SIF discrimination using an audio FM demodulation circuit. This example will be explained with reference to FIGS. 4 and 5. FIG. 4 is a circuit block diagram, and FIG. 5 is a diagram showing demodulation characteristics (S curve) of the FM demodulation circuit.

In Fig. 4, 10 is the SIF signal input terminal;
26 is a bandpass filter that allows f1 and f2 to pass through, 12 is an FM demodulation circuit, C3 is a coupling capacitor serving as a DC cut means, 14 is a demodulated audio signal output terminal, 28 is an integrating circuit, and 30 is a reference voltage VR. It is a voltage comparison circuit (detection circuit) and outputs discrimination outputs 30a and 30b that are inverted from each other of the voltage comparison circuit 30. 31 is the power terminal, D
1 and D2 are light emitting diodes for display.

The characteristics of the demodulation circuit 12 are set as shown in FIG. Center frequency f1 of the first SIF signal (e.g.
5.5MHz), and the center frequency f2 of the second SIF signal (for example, 6.0MHz), the center frequency f0 of the S curve of the demodulation circuit 12 is f1<f0<f2,
(f1+f2)/2 is equal to the frequency f0.

Furthermore, the center frequency f1 of the first SIF signal
is the center frequency f in the S curve 90 in FIG.
It is located at the center of the straight line portion 90a of 0 or less.
Furthermore, the center frequency f2 of the second SIF signal is the straight line portion 90 of the S curve 90 that is equal to or higher than the center frequency f0.
It is located in the center of b. Therefore, the characteristics of the demodulation circuit 12 are such that the upper and lower straight portions 90a and 90b do not affect the demodulation of the respective SIF signals.

When an SIF signal with a center frequency of f1 or f2 is input to the SIF signal input terminal 10, the demodulation circuit 1
The output of 2 is a demodulated audio signal having a DC level corresponding to the center frequency of the input SIF signal [Fig.
1,92] is obtained.

Regardless of the input SIF signal, the output of the demodulation circuit 12 is supplied to the audio signal output terminal 14 via the DC cut capacitor C3, so the difference in the DC component is not reflected in the output. It will not occur.

On the other hand, the signal component is smoothed by an integrating circuit 28 including a resistor R1 and a capacitor C4, and different DC voltages are applied to the voltage comparison circuit 30 depending on the difference in center frequencies f1 and f2.

The reference voltage VR of the voltage comparison circuit 30 has a frequency f
The output voltage is set equal to the output voltage of the demodulation circuit 12 corresponding to 0, and the outputs 30a and 30 are set equal to the output voltage of the demodulation circuit 12 corresponding to 0.
The state of b changes. In other words, the first SIF signal f
If 1 is input, output 30a is L, output 30
b becomes H. When the second SIF signal f2 is input, the output 30a becomes H and the output 30b becomes L.

If the first SIF signal is being input, the light emitting diode D1 will be lit, and if the second SIF signal is being input, the light emitting diode D2 will be lit.

(c) Problems that the invention attempts to solve: However, f1
If the demodulation characteristic of the demodulation circuit is made wideband so that f2 is located, the level of the demodulated audio signal becomes small.

(d) Means for solving the problem The present invention includes a first switching means for switching the bandwidth of the linear portion of the S curve of the demodulation circuit between narrowband and wideband, and switching the center frequency of the demodulation circuit to f1 or f2. a second switching means, and deriving an average DC level of the output signal from the demodulation circuit which has become broadband by the first switching means during the detection period;
An SIF comprising an integrating means, and a holding means for determining the center frequency of the SIF signal input to the demodulation circuit based on the signal from the integrating means, and holding the result of this determination and supplying it to the second switching means.
This is a signal demodulation circuit.

(e) Effect: In the present invention, during the detection period, the demodulation circuit is set to a wide band by the first switching means, and the carrier frequency of the SIF signal is determined in the same way as the conventional example shown in FIG. The result of this determination is then held in the holding means. After the detection period, the first switching means sets the demodulation circuit to a narrow band, and the second switching means is controlled by the output of the holding means to switch the center frequency of the demodulation circuit.

(f) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2. 40 is a BPF that passes the SIF signal with carrier frequency f1, and 42 is a BPF with carrier frequency f2.
This is a BPF that allows SIF signals to pass through. C1, L1
are a coil and a capacitor that determine the center frequency f2 of the demodulation circuit 12. R2 is S of the demodulation circuit 12
Make the slope of the curve gentler (make it broadband)
It is a damping resistance for C2 is demodulation circuit 1
This is a capacitor for shifting the center frequency of 2 to f1. 28 is an integrating circuit (integrating means). Reference numeral 14 denotes an audio signal output terminal, and an audio mute circuit such as an amplifier circuit whose gain decreases when an audio mute pulse is input is connected to the latter stage. 4
4 is a holding circuit (holding means) that discriminates the carrier frequency of the SIF signal and holds the discrimination result (note that the reference voltage is omitted). SW3 and SW4 are third and fourth switches. SW1 is a first switch (first switching means) that switches the demodulation band of the demodulation circuit 12 between narrowband and wideband, and SW2 is a second switch (second switching means) that switches the center frequencies f1 and f2 of the demodulation circuit. 46 is a gate pulse terminal to which a detection period signal (gate pulse signal) is input. Note that this gate pulse signal is generated when the power is turned on and when switching channels. Also, as this gate pulse signal, for example,
AFT day-to-day pulse or audio mute pulse (these two pulse signals will be explained later)
may be used directly. Furthermore, if the pulse width of the AFT defective pulse or audio mute pulse is not appropriate, a gate pulse with an appropriate width may be created using a variable pulse width circuit that extends or shortens the pulse width. Further, when audio muting is performed using an audio muting pulse, the gate pulse width may be set narrower than the width of the audio muting pulse.

In addition, AFT day-to-day pulse is published in Japanese Unexamined Patent Publication No. 1983
As shown in No. 137727, this is a well-known pulse signal that disables the AFT circuit for a certain period of time in order to prevent the AFT circuit from malfunctioning when the power is turned on or when switching channels. The audio mute pulse is a well-known pulse signal that reduces the gain of the audio signal amplification circuit for a certain period (pulse width period) in order to eliminate noise generated when switching channels and turning on the power. .

The above operation will be explained. When the power is turned on and when switching channels, a gate pulse signal created by shortening the audio mute signal, for example, is input to the gate pulse terminal, and the first, second, third, and fourth switches SW1, SW2, SW3, and SW4 are All are closed (on state). Therefore, whether the SIF signal of f1 or the SIF signal of f2 is input to the SIF signal input terminal, the SIF signal is input to the demodulation circuit 12. At this time, the first and second switches SW1, SW
2 is in the on state, the demodulation characteristic becomes wideband as shown in FIG. 2a, and the center frequency becomes f1. Therefore, as can be seen from FIG. 2, the potential at point D of the integrating circuit 28 becomes V1 when the SIF signal of f1 is input, and f
When the SIF signal of 2 is input, it becomes V2. Holding circuit 44
detects the potential at point D and determines the carrier frequencies f1 and f2 of the input SIF signal. When the carrier frequency of the SIF signal is f1, a high level signal is output from the terminal 44a and the second and third switches SW2 and SW
Turn on 3. At this time, the second and third switches
Since SW2 and SW3 have already been turned on by the gate pulse signal, there is no change. Also, SIF
When the carrier frequency of the signal is f2, a high level signal is output from the terminal 44b to turn on the fourth switch SW4. Incidentally, at this time, the fourth switch SW4 is already turned on by the gate pulse signal, so there is no change.

At the end of the input of the gate pulse to the gate pulse terminal 46 (at the end of the detection period), the holding circuit 44 maintains the output during the detection period. SIF during detection period
If the carrier frequency of the signal is determined to be f1, a high level signal continues to be output from the terminal 44a after the detection period ends. Therefore, as the gate pulse signal disappears, the first and fourth switches SW1 and SW4 are turned off. Therefore, the demodulation circuit 12 has BPF4.
Only the SIF signal of f1 is inputted via the SIF signal f1, and the demodulation characteristic of the demodulation circuit 12 becomes a narrow band characteristic with a center frequency of f1 as shown in FIG. 2b (b).

Also, during the detection period, the carrier frequency of the SIF signal is changed to f2.
If it is determined that this is the case, the high level signal continues to be output from the terminal 44b after the detection period ends. Therefore, as the gate pulse signal disappears, the first, second, and third switches SW1, SW2, and SW3 are turned off. Therefore, the demodulation circuit 12 receives f2 via the BPF 42.
Only the SIF signal is input, and the demodulation circuit 12
The demodulation characteristic becomes a narrow band at the center frequency f2, as shown in Fig. 2b.

(g) Effects of the invention As described above, according to the invention, the circuit can be used both as a circuit for determining the carrier frequency of an SIF signal and as a demodulation circuit. Furthermore, the level of the audio signal from this demodulation circuit does not decrease.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing demodulation characteristics. FIG. 3 is a diagram showing a first conventional example. FIG. 4 is a diagram showing a second conventional example, and FIG. 5 is a diagram for explaining FIG. 4. 10... SIF signal input terminal, 12... Demodulation circuit, SW1... First switch (first switching means), SW2... Second switch (second switching means), 28... Integrating circuit (integrating means) 44 ...Holding circuit (holding means).

Claims (1)

[Claims for Utility Model Registration] An SIF signal input terminal into which a first SIF signal whose center frequency is F1 and a second SIF signal whose center frequency is f2 are input, and a demodulation circuit that performs FM demodulation of the first and second SIF signals. , a SIF signal demodulation circuit comprising: first switching means for switching the bandwidth of the straight line portion of the S curve of the demodulation circuit between a narrow band and a wide band; and a center frequency of the demodulation circuit set to the f1 or f2.
an integrating means for deriving the average DC level of the output signal from the demodulating circuit which has become broadband due to the first switching means during the detection period; An SIF signal demodulation circuit characterized by comprising: a holding means that discriminates the carrier frequency of the input SIF signal, holds this discrimination result even after the end of the detection period, and supplies it to the second switching means. .