JPH05120881A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] To obtain a semiconductor memory device having a divided word line type SRAM with a small through current, a large operation margin, and a high degree of integration. [Structure] The local decoder circuit comprises a boost circuit for raising the local word line output by three N-type MOS transistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a local decoder circuit is highly integrated in an SRAM adopting a divided word line system.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a part of a memory cell array composed of M columns and N rows of memory cells of a conventional SRAM (static semiconductor memory device), in which Y is a column selection signal. (Output signal of column address signal decoding circuit).

Next, the operation will be described. When reading arbitrary cell data from the memory cell array of M rows and N columns, first, the row decoder selects one word line connected to the cell to be read from the M rows,
Launch this. Then, the data of all the memory cells connected to this word line appear on the bit line connected to that memory cell.

Next, the column decoder selects one bit line pair from the bit lines in which the data of the memory cell appears, and electrically connects it to the I / O line. As a result, one cell data selected by the row decoder and the column decoder appears on the I / O line, which is amplified by the sense amplifier, passes through the output buffer, and is read.

During the above read operation, a current flows from the bit line load transistor into all the memory cells connected to the selected word line, so that a shoot-through current as indicated by an arrow in the figure constantly occurs. It will flow. As the memory capacity increases, the number of columns also increases, and the through current further increases.

FIG. 4 shows a decoder circuit of the divided word line type SRAM disclosed in Japanese Patent Laid-Open No. 62-28516, in which B is a block signal.

In this circuit, the output of the row decoder is controlled by _n block signals B _n , and the word line is set to 1
It is subdivided into / n. By doing so, the number of memory cells selected by the word line is reduced to N / n, so that the bit line load current can be reduced and the through current shown in FIG. 5 can be reduced. Therefore, in order to reduce the shoot-through current, the larger the division number n, the better.

By the way, one local decoder circuit has a main word line and a block selection signal B as shown in the figure.
It is configured by a 2-NAND circuit having _n as an input and an inverter circuit.

FIG. 6 shows a conventional divided word line type SRAM.
3 is a circuit diagram showing a local decoder circuit in the decoder circuit of FIG. As shown in the figure,
The local decoder circuit is composed of three N-type MOS transistors and three P-type MOS transistors.

Since this local decoder circuit is composed of a NAND circuit and an inverter circuit, the main word line rises to the "H" level, and
Only when the block signal is also at "H" level, the local word line outputs up to the maximum V _CC -V _TH level.

If the number of divisions n is increased for the purpose of reducing the shoot-through current, the number of local decoder circuits, that is, the number of transistors, increases, and the chip size increases.

[0012]

Since the conventional semiconductor memory device is configured as described above, if the number of divisions n is increased to reduce the shoot-through current, that is, if the number of local decoder circuits is increased, the local decoder circuit is increased. Is 3 N-type M
Since it is composed of the OS transistor and the three P-type MOS transistors, the number of transistors is increased, and it is necessary to separate the P-type transistor region and the N-type transistor region. However, the local word line outputs only up to the maximum V _CC -V _TH level, and there is a problem that the operation margin is small.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor memory device capable of reducing a through current and occupying a small area to increase the degree of integration. ..

[0014]

In a semiconductor memory device according to the present invention, a local decoder circuit includes a first N-type MOS transistor which is a driver transistor, and the first N-type MOS transistor.
Second N-type MOS transistor, which is a load element, in which the drain electrode and the source electrode of the N-type MOS transistor are connected to form an inverter circuit, and V _CC is the gate electrode and the second N-type MOS transistor is the source electrode. A boost circuit for raising the potential of the local word line, which comprises a third N-type MOS transistor connecting the gate electrodes of the MOS transistors respectively, is provided, and the main electrode is provided with a main word line on the gate electrode of the first N-type MOS transistor. A block selection signal is connected to the drain electrode of the second N-type MOS transistor, and a main word line is connected to the drain electrode of the third N-type MOS transistor.

The semiconductor memory device according to the present invention is
The local decoder circuit includes the boost circuit, the gate electrode of the first N-type MOS transistor is an inverted signal of the block selection signal, the drain electrode of the second N-type MOS transistor is a main word line, and Third
The block selection signal is connected to the drain electrode of the N-type MOS transistor.

Further, in the semiconductor memory device according to the present invention, the local decoder circuit includes the boost circuit,
The gate electrode of the first N-type MOS transistor has:
The main word line is connected to the drain electrode of the second N-type MOS transistor, the main word line is connected to the drain electrode of the third N-type MOS transistor, and the block selection signal is connected.

[0017]

In the semiconductor memory device according to the present invention, the local decoder circuit is composed of three N-type MOS transistors to form a boost circuit for raising the output of the local word line, so that the number of transistors forming the local decoder circuit is reduced. The degree of integration can be increased, and the local word line output is not deteriorated.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an address decoder circuit in a semiconductor memory device according to an embodiment of the present invention, in which NT ₁ , NT ₂ , and NT ₃ are N-type M.
OS transistors B ₁ and B ₂ are block selection signals for selecting an arbitrary local decoder circuit subdivided into 1 / n blocks.

As shown in the figure, one local decoder circuit includes three N-type MOS transistors NT ₁ , NT ₂ ,
It is composed of NT ₃ . V _CC is applied to the gate electrode of NT _3.
, The drain electrode is connected to the main word line, and the source electrode is connected to the NT ₂ gate electrode. N
The source electrode of T ₁ is grounded, the gate electrode is connected to the / main word line, the drain of NT ₂ is connected to the block selection signal B ₁ , and the drain electrode of NT ₁ and NT are connected.
_{The two} source electrodes are commonly connected to the local word line.

Next, the operation will be described. First, when the output of the main decoder and the main word line become "H" and / main word line becomes "L" by the row address signal, N
T ₁ is turned off, but the potential of the gate electrode of NT ₂ is NT
_It goes to the level of V _CC -V _TH via ₃ . At this time, the level of the block selection signal B ₁ is "L".

After that, when the block selection signal B ₁ changes from “L” to “H”, NT ₂ is on, but NT ₁ is still off. Therefore, the inverter output consisting of NT ₁ and NT ₂ , that is, the local output. The word line potential gradually rises.
Correspondingly, the potential of the gate electrode of the NT _2, the gate of NT ₂ - by capacitive coupling between the drain - source / gate
The potential rises.

At this time, the rate at which the potential of the gate electrode of NT ₂ rises is determined by the ratio of the gate capacitance of NT _{2 and} the gate capacitance of NT ₃ , and if NT ₂ is much larger than that of NT ₃ , The potential of the gate electrode rises by the same amount as the voltage rise of the source electrode or drain electrode of NT ₂ . However, at this time, the potentials of the gate electrode and the source electrode of NT ₃ are both at the V _CC level and NT ₃ is in the off state. Therefore, when the local word line potential rises,
Similarly, the potential of the drain electrode of NT ₃ , that is, the gate electrode of NT ₂ also rises, so the potential of the local word line rises to the maximum V _CC level, and the gate potential of NT ₂ also rises to 2
It rises to V _CC -V _TH .

Thus, in the above embodiment, NT ₁ , N
Since the boost circuit is composed of T ₂ and NT ₃ ,
The output potential of the local word line is not limited to V _CC -V _TH and can be increased to the maximum V _CC level. Therefore, even if the through current is reduced and the occupied area is reduced by the divided word line method, the characteristics can be improved. It is possible to obtain a semiconductor memory device having a large operation margin without causing the deterioration of.

Next, a second embodiment of the present invention will be described. 2 is a block diagram showing the configuration of an address decoder circuit in a semiconductor memory device according to a second embodiment of the present invention. In the figure, NT ₄ , NT ₅ , and NT ₆ are N-type MOS transistors, and Bn and / Bn are. 1 / each
A block selection signal and a block selection signal for selecting an arbitrary local decoder circuit subdivided into n blocks.

Also in the second embodiment, one local decoder circuit is composed of three N-type MOS transistors NT ₄ , NT ₅ and NT ₆ as shown in the figure, and is the same as in the first embodiment. Configures the boost circuit. NT
_The / block selection signal Bn is connected to the gate electrode of _4, the ground potential is connected to the source electrode, and the drain electrode is connected to the local word line in common with the source electrode of NT ₅ . The power supply potential is applied to the gate electrode of NT ₆ .
The block selection signal / Bn is connected to the drain electrode, and the source electrode is connected to the gate electrode of NT ₅ . The main word line is connected to the drain electrode of NT ₅ .

Also in this case, as in the first embodiment, when the main word line and the block selection signal Bn become "H" level, the output of the inverter composed of NT ₄ and NT ₅ , that is, the output of the local word line. _Can increase to the maximum V _CC , so that even if the number of divisions of the address decoder circuit is increased to reduce the through current, a semiconductor memory device having a high degree of integration and a large operation margin can be obtained.

Next, a third embodiment of the present invention will be described. FIG. 3 is a block diagram showing the structure of an address decoder circuit in a semiconductor memory device according to a third embodiment of the present invention. In the figure, NT ₇ , NT ₈ , and NT ₉ are N-type MOS transistors, and Bn is 1 / n. This is a block selection signal for selecting an arbitrary local decoder circuit subdivided into individual blocks.

Also in this second embodiment, one local decoder circuit is composed of three N-type MOS transistors NT ₇ , NT ₈ and NT ₉ as shown in the figure, and is the same as in the first embodiment. Configures the boost circuit. NT
_The / main word line is connected to the gate electrode of _7, the ground potential is connected to the source electrode, and the drain electrode is connected to the local word line in common with the source electrode of NT ₈ . A power supply potential is connected to the gate electrode of NT _9, a block selection signal Bn is connected to the drain electrode, and a source electrode is connected to the gate electrode of NT ₈ . The main word line is connected to the drain electrode of NT ₈ .

Also here, as in the first and second embodiments, when the main word line and the block selection signal Bn become "H" level, the output of the inverter composed of NT ₇ and NT ₈ , that is, the local word. Since the output of the line can be increased up to the maximum V _CC , even if the number of divisions of the address decoder circuit is increased to reduce the shoot-through current, it is possible to obtain a semiconductor memory device having a high degree of integration and a large operation margin. You can

[0030]

As described above, according to the semiconductor memory device of the present invention, the local decoder circuit includes three N type Ms.
By configuring the boost circuit that raises the local word line output by the OS transistor, the output potential of the local word line is not limited to V _CC -V _TH and can be increased to the maximum V _CC level. Through current is reduced, the number of transistors forming the local decoder circuit is reduced, the degree of integration can be increased, and a local word line output is not generated.
There is an effect that a semiconductor memory device with a large operation margin can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an address decoder circuit in a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a structure of an address decoder circuit in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a structure of an address decoder circuit in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a decoder circuit of a conventional divided word line type SRAM.

FIG. 5 is a diagram showing a part of a memory cell array of a conventional semiconductor memory device.

FIG. 6 is a circuit diagram showing a conventional local decoder circuit as a transistor circuit.

[Explanation of symbols]

NT _{1 to} NT ₉ N-type MOS transistor Bn block selection signal / Inversion signal of Bn block selection signal

Claims (3)

[Claims] 1. A semiconductor memory device comprising an address decoder circuit divided into a plurality of local decoder circuits by a divided word line system, wherein the local decoder circuit is a driver transistor having a gate electrode connected to a main word line. There is a first
Second load transistor, which is an inverter circuit in which a block selection signal is connected to the drain electrode of the first N-type MOS transistor and the drain electrode of the first N-type MOS transistor is connected to the source electrode thereof. An N-type MOS transistor and a third N-type MOS transistor in which V _CC is connected to the gate electrode, a main word line is connected to the drain electrode, and the gate electrode of the second MOS transistor is connected to the source electrode are provided. A semiconductor memory device characterized by the above. 2. The semiconductor memory device according to claim 1, wherein the gate electrode of the first N-type MOS transistor is:
An inversion signal of the block selection signal is connected in place of the main word line, and a main word line is connected in place of the block selection signal to the drain electrode of the second N-type MOS transistor. A semiconductor memory device, wherein a block selection signal is connected to a drain electrode of an N-type MOS transistor instead of a main word line. 3. The semiconductor memory device according to claim 1, wherein the drain electrode of the second N-type MOS transistor comprises:
A semiconductor memory device, wherein a main word line is connected instead of the block selection signal, and a block selection signal is connected to the drain electrode of the third N-type MOS transistor instead of the main word line.