JPH0512362A - Circuit network input method to circuit simulator - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the work efficiency of a circuit network input method to a circuit simulator in the preliminary evaluation of the circuit design of a semiconductor integrated circuit. [Structure] Macro cell file 2 for each logic element in the logic circuit to be evaluated and its connection relation
It is described in the input card 21 using the macro cell in 2.
The computer automatically processes the information described in the input card 21 and replaces it with the electronic circuit network.
Get 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit network input method to a circuit simulator, and more particularly to a circuit network input method to a circuit simulator in a preliminary evaluation of a circuit design of a semiconductor integrated circuit.

In designing and manufacturing a large scale integrated circuit (LSI), generally, as shown in FIG. 7, a user of the LSI sets specifications such as external conditions and design requirements at the time of ordering (step 101), and then manufactures the LSI. The maker designs a specification that defines the details of the operation of the LSI, and then performs a logic design based on the specification design data (step 102). Next, the specifications are disassembled (step 103), and a logic diagram embodied up to the level of each logic gate as a unit is designed (step 104), and a layout design for designing an LSI mask pattern is performed. Is performed (step 105).

The data after the layout design is passed to the manufacturing process as a mask pattern, a mask (MASK) is manufactured (step 106), and then a wafer is processed using the mask (step 107) to manufacture an LSI. .

In the design and manufacturing process of such an LSI,
The layout design, which is the most important design process, is performed in more detail according to the flowchart of FIG. In FIG. 8, after the logic circuit is designed (step 20
1) After examining the floor plan for the layout and wiring of logic gates based on the logic diagram (step 202), the actual M
The circuit is evaluated by a desk study that does not have ASK data (step 203).

The operation is confirmed by the above circuit evaluation (step 204). If it is defective, the logic circuit design or floor plan is examined again, and if it is normal, the layout work is started (step 205). Then, MASK obtained based on the data after the layout work is completed.
The data is verified (step 206) and electronic circuit evaluation is performed using the actual MASK data (step 20).
7).

In such a layout design, the circuit evaluation in the desk study without the actual MASK data in step 203 is performed by a circuit simulator so as not to cause a malfunction due to sudden layout work. Is to verify the electrical performance and eliminate design mistakes. However, in recent years, LSIs have tended to become larger and larger, and the work of LSI design has been differentiated in recent years. Therefore, logic designers and layout designers may be different, which makes them more efficient and error-prone. It is necessary to input the network data into the circuit simulator without the need.

[0007]

2. Description of the Related Art The circuit evaluation of an LSI using a circuit simulator is generally performed according to the flowchart shown in FIG. In the figure, based on the designed logic circuit diagram 301, a critical path is identified (step 302) and a floor plan is examined (step 303), and a logic circuit diagram composed of each logic element (gate) obtained as a result. To an electronic circuit diagram composed of active elements (transistors) and passive elements (capacitors, resistors, etc.) to create an input card of the circuit simulator (step 304). At that time, an accompanying process such as making the wiring into a passive element is performed in consideration of the actual MASK pattern.

The data of the input card thus created is input to the circuit simulator to execute the circuit simulation (step 305).

Here, when an input card of a circuit simulator is conventionally created, for example, inverters 41, 48, 50, 51, 52, a clocked inverter 42, a 2-input NOR circuit 43 and a 2-input NAND circuit as shown in FIG. Four
4, 47, 2-input AND circuit 45, 3-input NOR circuit 4
6. Replace the logic circuit diagram composed of each logic element such as the latch circuit 49 with an electronic circuit network composed of active elements and passive elements such as P-channel transistors and N-channel transistors as shown in FIG. Parameters were set for each element. In FIG. 11, the circuit parts corresponding to those in FIG. 10 are designated by the same reference numerals. In the electronic circuit network of FIG. 11, the inverters 41, 4
8, 50, 51 and 52 are C-MOS inverters, and the other logic gates are also P-channel and N-channel field effect transistors.

After the replacement with the electronic circuit network by the above-mentioned artificial work, an input card having the description as shown in FIGS. 12 and 13 is prepared. In both figures, the leftmost 6-digit number is a sequential number, the second from the left shows the capacitance name (the one with C at the beginning) or the transistor name (the one with M at the beginning), and the third from the left onward. In the case of a capacitive element, the attribute, node 1, node 2, junction area 1, junction area 2 are described respectively, and in the case of a transistor element, the attribute, drain, source and gate connection nodes, substrate, channel length and channel width. Is described. The input card described in this way is inserted into the circuit simulator.

[0011]

However, when describing the input card of the circuit simulator in the related art, first, referring to FIG.
After the person replaces the logic circuit as shown in Fig. 11 with the electronic circuit network as shown in Fig. 11 in his / her head, the parameters (junctions) for each element such as transistor, capacitor (capacitor), and resistor after the replacement Since the area, channel length, channel width, etc.) were set for each element, errors due to human work were likely to occur.

Further, although the replaced electronic circuit network conventionally includes a large number of frequently appearing circuit parts, the parameters are set for each element, and moreover, in the recent circuit networks, Due to the increasing scale, the work efficiency was extremely poor and the work required a long time.

The present invention has been made in view of the above points,
An object of the present invention is to provide a method for inputting a circuit network to a circuit simulator which enhances work efficiency and has versatility of the circuit network.

[0014]

FIG. 1 shows a flow chart for explaining the principle of the method of the present invention. The method of the present invention is a circuit network input method to a circuit simulator for replacing a logic circuit with an electronic circuit network and inputting the circuit into a circuit simulator for evaluation of a designed logic circuit when designing a layout of a semiconductor integrated circuit. It is configured to include the first to third steps 11 to 13.

Here, in the first step 11, a macro cell, which is a logic element in which a plurality of types of parameters are set, is prepared in advance as a library based on the frequency of use in the logic circuit.

In the second step 12, each logic element in the logic circuit to be evaluated and its connection relation are described in the input card by using the macro cell of the library.

In the third step 13, the logic circuit to be evaluated is automatically replaced with the circuit network based on the input card, and then input to the circuit simulator.

[0018]

In the present invention, since the replacement of the logic circuit diagram with the electronic circuit network is automatically performed in the third step 13, the user of the circuit simulator uses the general purpose in the second step 12. An input card from the logic circuit to the circuit simulator can be described and created only by understanding a typical logic element (for example, a NAND circuit, a NOR circuit, an inverter, etc.) and considering the connection relationship of those logic elements.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a procedure explanatory view of an embodiment of the method of the present invention. In the figure, reference numeral 21 is an input card, which is described and created by a user of the circuit simulator by a method described later. 22
Is a macro cell file, which is a plurality of types of logic elements (gates) that are likely to be frequently used in a normal logic circuit, and stores a set of logic elements (this is called a macro cell) whose parameters are preset. ing.

As the above macro cell, for example, FIG.
There are a plurality of types of logic elements as shown in (A) to (I).
3A, 3B, and 3C, the gates of P-channel and N-channel field effect transistors (FETs) are commonly connected to the input terminal A, and the two FETs and drains are output terminals. C-MOS commonly connected to X
Although they are common in that they are inverters, FIG.
Specific names “FV01” and “F” shown in (B) and (C), respectively.
The parameters of the V02 ”and“ FV05 ”inverters (driving capability, channel width, channel length, etc.) are set to different predetermined values.

The macrocell shown in FIG. 3D has an input terminal A.
1 and A2 and output terminal X, and two P channel F
2-input NA consisting of ET and two N-channel FETs
The unique name of the ND circuit is "FA02". Figure 3
The macro cell shown in (E) is a three-input NAND circuit with a proper name “FA03”, has three input terminals A1 to A3 and one output terminal X, and includes three P-channel FETs and three N-channel FETs. Become.

FIG. 3F shows a two-input NOR circuit having a proper name "FR02", which has two input terminals A1 and A2 and one output terminal X, and has two P-channel FETs and two N-channel FETs. Consists of. FIG. 3G is a clocked inverter having a proper name “FCV1”, in which two P-channel FETs and two N-channel FETs are connected in series, and the top P-channel FET and the bottom N-channel FET are connected. Connect both gates to the input terminal A, and from the top 2
The gates of the 1st and 3rd FETs are connected to input terminals CX and C, respectively.
And their drains at the output terminal X
Is commonly connected to.

Further, FIG. 3H shows a 2-input AND circuit and a 3-input AND circuit.
It is a composite gate circuit of the input NOR circuit, which is shown in FIG.
It has the same connection as the composite gate circuit composed of the input AND circuit 45 and the 3-input NOR circuit 46, and has a proper name "F" having four input terminals A1 to A4 and one output terminal X.
It is a composite gate circuit of "H06". Further, FIG. 3 (I) shows a latch circuit, which has the same circuit configuration as the latch circuit 49 shown in FIG. 10 and has two C outputs from the clocked inverter.
One of the -MOS inverters is connected to the input terminal of one C-MOS inverter and the output terminal of the other C-MOS inverter, and the proper name is "FLV1". Parameters are set in all of the above macro cells.

Returning to FIG. 2 again, 23 is a process parameter file, which is a parameter of the device forming condition when the circuit simulator is executed (for example, the amount of ion implantation for obtaining the required resistance per unit area or capacitance per unit area). Other) is stored in advance. This macrocell file 2
2 and each data from the process parameter file 23 is used for converting the data of the input card 21 in the conversion procedure 25.

Here, when the logic circuit to be evaluated is as shown in FIG. 10, the user of the circuit simulator uses the input card 21 described as shown in FIG. 4 based on the connection relationship with each logic element in FIG. All you have to do is create it. In FIG. 4, the leftmost six-digit number is a sequential number, the second leftmost three-digit code is the macro name, and the third leftmost four-digit code is the macrocell shown in FIGS. 3A to 3I. The unique name of the symbol, the code from the left end on the fourth and subsequent symbols indicates to which node the terminal of the macro cell is connected.

As a result, the sequential number "0
"00002" has a macro name "F01" and a unique name "F01".
V01 "shown in FIG. 3 (A) (4 in FIG. 10).
It is described that the input terminal A (corresponding to 1) is connected to the node “N0001” and the output terminal X is connected to the node “N0002”. Further, in the sequential number “000003”, the input terminal A of the clocked inverter (corresponding to 42 in FIG. 10) shown in FIG. 3G having the macro name “F02” and the proper name “FCV1” is the node “N00”.
01 ”, the output terminal X is connected to the node“ N0004 ”, the input terminal C is connected to VDD, and the input terminal CX is connected to VGG.

In the same manner, the user of the circuit simulator then determines that the logic element of the logic circuit shown in FIG. 10 corresponds to which macrocell of the plurality of macrocells of the macrocell file 22 and which node the input terminal and the output terminal of that macrocell are. Write only based on what is connected to. As a result, the input card can be described by only 11 macro cells in macro cell units without considering the electronic circuit network as shown in FIG. 11 and without setting the numerical parameters for each element. , Compared to the case of describing the conventional input card shown in FIGS. 12 and 13,
An input card can be created very easily by a person who has no knowledge of electronic circuits.

The input card 21 having the contents described as shown in FIG. 4 is instructed by the control card 24 of FIG. 2 for control (for example, not outputting a list, listing out an input card) when executing a program. Also, necessary data is taken in from the macrocell file 22 and the process parameter file 23 according to the conversion procedure 25, and is automatically processed by the computer that executes the conversion procedure 25. As a result, the output list 26 is output from the computer as needed, while the logic circuit shown in FIG. 10 is automatically replaced (converted) by the electronic circuit network shown in FIG. 11 and FIG. The conversion card 27 having the description content shown in FIG. 6 is obtained.

That is, as shown in FIGS. 5 and 6, the description content of the conversion card 27 is substantially the same as the conventional input card of FIGS. 12 and 13 except that the description method of the second element name from the left end is slightly different. 11 shows the same description contents as those of the conventional input card of FIGS. 12 and 13, and shows the electronic circuit network of FIG.

The conversion card 27 is used for executing the circuit simulator as shown by 28 in FIG. 2, and the analysis result is accumulated in the signal file 29 and is output to the output list 30 as needed.

[0031]

As described above, according to the present invention, the user of the circuit simulator determines that each logic element of the logic circuit diagram corresponds to which macro cell prepared in advance and which node is connected to which macro cell. Since it is possible to create an input card considering only the presence, it is not necessary to set each element such as numerical parameters of a large-scale electronic circuit network, and work efficiency can be greatly improved compared to the conventional method. In addition, since the replacement of the logic circuit with the electronic circuit network is automatically performed, mistakes due to human intervention can be eliminated, which greatly contributes to the improvement of the quality of the semiconductor integrated circuit. Those who have such characteristics can obtain an electronic circuit diagram.

[Brief description of drawings]

FIG. 1 is a flowchart for explaining the principle of the present invention.

FIG. 2 is a procedure explanatory view of an embodiment of the method of the present invention.

FIG. 3 is a circuit diagram of each example of a macro cell.

FIG. 4 is a description example of an input card created by the method of the present invention.

FIG. 5 is a description example (1) of a conversion card obtained by the method of the present invention.

FIG. 6 is a description example (No. 2) of the conversion card obtained by the method of the present invention.

FIG. 7 is an explanatory diagram of an LSI design and manufacturing process.

FIG. 8 is a flowchart for explaining a layout design.

FIG. 9 is a flowchart for explaining an actual work of circuit evaluation.

FIG. 10 is a circuit diagram of an example of a logic circuit.

FIG. 11 is a circuit diagram of an example of an electronic circuit network input to the circuit simulator.

FIG. 12 is a description example (1) of a conventional input card.

FIG. 13 is a description example (2) of the conventional input card.

[Explanation of symbols] 11 First step 12 Second step 13 Third step 21 Input Card 27 Convert Card

Claims (2)

[Claims] 1. A method for inputting a circuit to a circuit simulator, wherein the logic circuit is replaced with an electronic circuit network and input to a circuit simulator for evaluation of the designed logic circuit in layout design of a semiconductor integrated circuit, A first step (11) of preparing a macrocell, which is a logic element in which a plurality of types of parameters are set, as a library based on the frequency of use in the logic circuit, and each step in the logic circuit to be evaluated. A second step (12) of describing the logic elements and their connection relationship in the input card by using the macro cell of the library; and the logic circuit to be evaluated based on the input card in the electronic circuit network. Circuit simulator including a third step (13) of automatically replacing Method of inputting network to computer. 2. The third step (13) is characterized in that an output card in which each element name and parameter of the automatically replaced electronic circuit network is described is generated as an input for the circuit simulator. A method for inputting a circuit network to the circuit simulator according to claim 1.