JPH0512812Y2 - - Google Patents
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- Publication number
- JPH0512812Y2 JPH0512812Y2 JP15602284U JP15602284U JPH0512812Y2 JP H0512812 Y2 JPH0512812 Y2 JP H0512812Y2 JP 15602284 U JP15602284 U JP 15602284U JP 15602284 U JP15602284 U JP 15602284U JP H0512812 Y2 JPH0512812 Y2 JP H0512812Y2
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- Prior art keywords
- transistor
- current
- collector
- constant current
- transistors
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- 238000010586 diagram Methods 0.000 description 5
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
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- 230000003503 early effect Effects 0.000 description 1
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- Continuous-Control Power Sources That Use Transistors (AREA)
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案は、IC（集積回路）化に適し、低電源電
圧でも安定に定電流を発生することが出来、かつ
消費電流の少い定電流回路に関するものである。[Detailed explanation of the invention] (a) Industrial application field This invention is suitable for IC (integrated circuit), can stably generate constant current even at low power supply voltage, and has low current consumption. It is related to current circuits.
(ロ) 従来の技術
ダイオードとトランジスタとを用いる定電流回
路が、特開昭54−81760号公報に示される如く従
来公知である。この定電流回路は、第２図に示さ
れる如く、電源（＋VCC）とアースとの間に直列
接続された第１抵抗１と第１及び第２ダイオード
２及び３とから成る直列回路と、ベースが前記第
１抵抗１と第１ダイオード２との接続点に、コレ
クタが出力端子４に、エミツタが第２抵抗５を介
してアースに接続されたトランジスタ６とから成
り、前記出力端子４に定電流を得るものである。
しかして、第２図の場合、前記出力端子４の出力
電流I0は、I0＝VD／R1（ただし、VDはダイオード
の順方向電圧降下、R1は第２抵抗５の抵抗値）
と表わすことが出来るが、電源電圧が所定値以上
ある間は、前記ダイオードの順方向電圧降下VD
が略一定となる為、前記出力電流I0が定電流にな
る。しかしながら、電源電圧が所定値以下に低下
し、第１及び第２ダイオード２及び３に流れる電
流が減少すると、前記第１及び第２ダイオード２
及び３の順方向電圧降下も減少し、前記出力電流
I0が減少する。実際には、電源電圧が約1.5V程度
に低下すると前記出力電流が定電流性を失なつて
くる。(b) Prior Art A constant current circuit using a diode and a transistor is conventionally known as shown in Japanese Patent Application Laid-open No. 81760/1983. As shown in FIG. 2, this constant current circuit includes a series circuit consisting of a first resistor 1 and first and second diodes 2 and 3 connected in series between a power supply (+V CC ) and ground; A transistor 6 has a base connected to the connection point between the first resistor 1 and the first diode 2, a collector connected to the output terminal 4, and an emitter connected to the ground via the second resistor 5. This is to obtain a constant current.
Therefore, in the case of FIG. 2, the output current I 0 of the output terminal 4 is I 0 =V D /R 1 (where, V D is the forward voltage drop of the diode, and R 1 is the resistance of the second resistor 5. value)
However, while the power supply voltage is above a predetermined value, the forward voltage drop of the diode is V D
is substantially constant, so the output current I 0 becomes a constant current. However, when the power supply voltage drops below a predetermined value and the current flowing through the first and second diodes 2 and 3 decreases, the first and second diodes 2
The forward voltage drop of and 3 is also reduced, and the output current
I 0 decreases. In reality, when the power supply voltage drops to about 1.5V, the output current loses its constant current property.
(ハ) 考案が解決しようとする問題点
上述の如く、第２図に示す如き回路構成では、
出力電流が電源電圧に依存し、電源電圧の低下に
応じて減少するので、特に1.5Vの乾電池を電源
として使用する機器（0.9V迄補償）に用いるこ
とが出来ないという問題があつた。(c) Problems to be solved by the invention As mentioned above, in the circuit configuration shown in Figure 2,
Since the output current depends on the power supply voltage and decreases as the power supply voltage drops, there was a problem in that it could not be used particularly in equipment that uses 1.5V dry batteries as a power supply (compensation up to 0.9V).
(ニ) 問題点を解決するための手段
本考案は、上述の点に鑑み成されたもので、ベ
ース及びエミツタが共通接続された第１及び第２
トランジスタと、該第１及び第２トランジスタの
共通エミツタと電源との間に接続された抵抗と、
前記第１及び第２トランジスタの共通ベースと電
源との間に接続されたシヨツトキーダイオード
と、コレクタが前記第１トランジスタのコレクタ
に接続されたダイオード接続型の第３トランジス
タと、該第３トランジスタのコレクタ・エミツタ
間に接続された抵抗と、前記第３トランジスタと
ミラー関係に接続されるとともに、コレクタが前
記第２トランジスタのコレクタに接続された第４
トランジスタと、前記第２及び第４トランジスタ
のコレクタ電流の差電流を取り出す電流ミラー回
路と、該電流ミラー回路を構成するトランジスタ
とベース及びエミツタが共通接続され、コレクタ
が前記第１及び第２トランジスタのベースに共通
接続された定電流トランジスタとを備える点を特
徴とする。(d) Means for solving the problem The present invention has been made in view of the above points, and includes a first and a second emitter whose base and emitter are commonly connected.
a resistor connected between a common emitter of the first and second transistors and a power source;
a Schottky diode connected between a common base of the first and second transistors and a power supply; a diode-connected third transistor whose collector is connected to the collector of the first transistor; and the third transistor. a resistor connected between the collector and emitter of the transistor, and a fourth transistor connected in a mirror relationship to the third transistor, and whose collector is connected to the collector of the second transistor.
a transistor, a current mirror circuit for extracting a difference current between the collector currents of the second and fourth transistors, a base and an emitter of the transistor constituting the current mirror circuit are commonly connected, and the collector is connected to the collector current of the first and second transistors; A constant current transistor is commonly connected to the base.
(ホ) 作用
本考案に依れば、定電流回路の出力電流が第３
トランジスタのコレクタ・エミツタ間に接続され
る抵抗に応じて決まるので、電源電圧の低下時に
も前記出力電流を一定に保つことが出来るととも
に、前記定電流回路の入力側電流を前記出力電流
に応じて設定しているので、全体として消費電流
を減少させることが出来る。(E) Effect According to the present invention, the output current of the constant current circuit
Since the output current is determined depending on the resistance connected between the collector and emitter of the transistor, the output current can be kept constant even when the power supply voltage drops, and the input current of the constant current circuit can be adjusted according to the output current. Since this is set, the current consumption can be reduced as a whole.
(ヘ) 実施例
第１図は、本考案の一実施例を示す回路図で、
７はPNP型の第１トランジスタ、８はベース及
びエミツタが前記第１トランジスタ７のベース及
びエミツタと共通接続されたPNP型の第２トラ
ンジスタ、９及び１０は前記第１トランジスタの
ベースと電源（＋VCC）との間に直列接続された
第１及び第２シヨツトキーダイオード、１１は前
記第１トランジスタ７のエミツタと電源との間に
接続された抵抗、１２はコレクタが前記第１トラ
ンジスタ７のコレクタに接続されるとともに、ベ
ース・コレクタが短絡されてダイオード接続型と
成されたNPN型の第３トランジスタ、１３はコ
レクタが前記第２トランジスタ８のコレクタに接
続されるとともに、ベース及びエミツタが前記第
３トランジスタ１２のベース及びエミツタとそれ
ぞれ共通接続されたNPN型の第４トランジスタ、
１４は前記第３トランジスタ１２のコレクタ・エ
ミツタ間に並列接続された抵抗、１５は第５及び
第６トランジスタ１６及び１７から成り、前記第
２トランジスタ８のコレクタ電流と前記第４トラ
ンジスタ１３のコレクタ電流との差電流を反転し
て出力端子１８に導出する電流ミラー回路、及び
１９はベース及びエミツタが前記第６トランジス
タ１７のベース及びエミツタに接続され、コレク
タが前記第１トランジスタ７のベースに接続され
た定電流トランジスタである。(F) Embodiment Figure 1 is a circuit diagram showing an embodiment of the present invention.
7 is a PNP type first transistor; 8 is a PNP type second transistor whose base and emitter are commonly connected to the base and emitter of the first transistor 7; 9 and 10 are connected to the base of the first transistor and the power supply (+V 11 is a resistor connected between the emitter of the first transistor 7 and the power supply; 12 is a resistor whose collector is connected to the power source of the first transistor 7 ; A third NPN type transistor 13 is connected to the collector of the second transistor 8, and has its base and collector shorted to form a diode-connected type. a fourth NPN transistor commonly connected to the base and emitter of the third transistor 12;
14 is a resistor connected in parallel between the collector and emitter of the third transistor 12; 15 is a fifth and sixth transistor 16 and 17; the collector current of the second transistor 8 and the collector current of the fourth transistor 13; and a current mirror circuit 19 which inverts the difference current between the two and outputs it to the output terminal 18, and a current mirror circuit 19 has a base and an emitter connected to the base and emitter of the sixth transistor 17, and a collector connected to the base of the first transistor 7. It is a constant current transistor.
次に動作を説明する。電源（＋VCC）を投入す
ると、第１及び第２シヨツトキーダイオード９及
び１０と抵抗２０とに起動電流が流れ、それに応
じて第１及び第２トランジスタ７及び８がオン
し、抵抗１１に電流が流れる。しかして、前記抵
抗１１に流れる電流は、２等分され一方において
前記第１トランジスタ７のコレクタ電流となり、
他方において前記第２トランジスタ８のコレクタ
電流となる。そして前記第１トランジスタ７のコ
レクタ電流は、第３トランジスタ１２のコレクタ
電流と抵抗１４に流れる電流とに分流され、前記
第２トランジスタ８のコレクタ電流の一部は第４
トランジスタ１３のコレクタ電流となる。いま、
抵抗１１に流れる電流をI1とすれば、該電流I1
は、
I1＝2VDS−VBE／R1 …(1)
〔ただし、VDSはシヨツトキーダイオードの順
方向電圧降下
VBEはトランジスタのベース・エミツタ間電圧
R1は抵抗１１の抵抗値〕
となり、第１及び第２トランジスタ７及び８のコ
レクタ電流I2は、それぞれ
I2＝I1／２ …(2)
となる。また、第３トランジスタ１２のコレクタ
電流I3は、
I3＝I2−VBE／R2 …(3)
〔ただし、R2は抵抗１４の抵抗値〕
となり、前記第３トランジスタ１２と第４トラン
ジスタ１３とのミラー比を１：１に設定すれば、
前記第４トランジスタ１３のコレクタ電流もI3と
なる。その為、第２トランジスタ８のコレクタ電
流I2と第４トランジスタ１３のコレクタ電流との
間に差を生じ、差電流△Ｉは、
△Ｉ＝I2−I3＝VBE／R2 …(4)
となり、電流ミラー回路１５の第５トランジスタ
１６のコレクタに流入する。その際、電流ミラー
回路１５のミラー比を１：１に設定すれば、前記
電流ミラー回路１５の第６トランジスタ１７のコ
レクタ電流も△Ｉとなる。従つて、出力端子１８
に得られる定電流回路の出力電流I0は、
I0＝△Ｉ＝VBE／R2 …(5)
となり、電源電圧の影響を受けず、抵抗１４の値
に応じて決まる一定の出力電流を得ることが出来
る。 Next, the operation will be explained. When the power supply (+V CC ) is turned on, a starting current flows through the first and second shot key diodes 9 and 10 and the resistor 20, and accordingly, the first and second transistors 7 and 8 are turned on, and the resistor 11 is turned on. Current flows. Therefore, the current flowing through the resistor 11 is divided into two equal parts, one of which becomes the collector current of the first transistor 7,
On the other hand, it becomes the collector current of the second transistor 8. The collector current of the first transistor 7 is divided into the collector current of the third transistor 12 and the current flowing through the resistor 14, and a part of the collector current of the second transistor 8 is divided into the collector current of the third transistor 12 and the current flowing through the resistor 14.
This becomes the collector current of the transistor 13. now,
If the current flowing through the resistor 11 is I 1 , the current I 1
I 1 = 2V DS −V BE /R 1 …(1) [However, V DS is the forward voltage drop of the Schottky diode, V BE is the voltage between the base and emitter of the transistor, and R 1 is the resistance value of resistor 11. ] The collector currents I 2 of the first and second transistors 7 and 8 are respectively I 2 =I 1 /2 (2). Further, the collector current I 3 of the third transistor 12 is I 3 =I 2 −V BE /R 2 (3) [where R 2 is the resistance value of the resistor 14], and the third transistor 12 and the fourth If the mirror ratio with transistor 13 is set to 1:1,
The collector current of the fourth transistor 13 is also I3 . Therefore, a difference occurs between the collector current I 2 of the second transistor 8 and the collector current of the fourth transistor 13, and the difference current ΔI is as follows: ΔI=I 2 −I 3 =V BE /R 2 ( 4) and flows into the collector of the fifth transistor 16 of the current mirror circuit 15 . At this time, if the mirror ratio of the current mirror circuit 15 is set to 1:1, the collector current of the sixth transistor 17 of the current mirror circuit 15 also becomes ΔI. Therefore, the output terminal 18
The output current I 0 of the constant current circuit obtained is I 0 =△I=V BE /R 2 (5), which is a constant output current that is not affected by the power supply voltage and is determined according to the value of the resistor 14. can be obtained.
また、定電流トランジスタ１９のベース及びエ
ミツタは、第５及び第６トランジスタ１６及び１
７のベース及びエミツタと共通接続されているの
で、前記定電流トランジスタ１９のコレクタ電流
もI0の一定電流となる。そして、前記定電流トラ
ンジスタ１９のコレクタは第１トランジスタ７の
ベースに接続されているので、第１及び第２シヨ
ツトキーダイオード９及び１０に前記定電流I0が
流れる。尚、起動用の抵抗２０の抵抗値は大であ
る為、前記抵抗２０に流れる電流は無視出来る程
小である。 Further, the base and emitter of the constant current transistor 19 are connected to the fifth and sixth transistors 16 and 1.
Since the base and emitter of the constant current transistor 19 are commonly connected, the collector current of the constant current transistor 19 also becomes a constant current of I0 . Since the collector of the constant current transistor 19 is connected to the base of the first transistor 7, the constant current I0 flows through the first and second Schottky diodes 9 and 10. Incidentally, since the resistance value of the starting resistor 20 is large, the current flowing through the resistor 20 is negligibly small.
上述の如く、第１図の回路の場合、第１及び第
２シヨツトキーダイオード９及び１０にI0の定電
流が流れ、抵抗１１にI1の電流が流れる。シヨツ
トキーダイオードの順方向電圧降下VDSは0.4V、
トランジスタのベース・エミツタ間電圧は0.6V
であるから、前記抵抗１１に流れる電流I1は該抵
抗１１の値に応じて設定出来、また第１及び第２
シヨツトキーダイオード９及び１０に流れる電流
I0も抵抗１４の値に応じて設定出来る。その為、
必要な出力定電流が定まれば、全体の消費電流を
電源電圧に依らず、抵抗１１及び１４の値を設定
するだけで決めることが出来、低消費電流化を容
易に計ることが出来る。 As mentioned above, in the case of the circuit shown in FIG. 1, a constant current of I0 flows through the first and second Schottky diodes 9 and 10, and a current of I1 flows through the resistor 11 . The forward voltage drop V DS of the Schottky diode is 0.4V,
The voltage between the base and emitter of the transistor is 0.6V
Therefore, the current I1 flowing through the resistor 11 can be set according to the value of the resistor 11, and the
Current flowing through Schottky diodes 9 and 10
I 0 can also be set according to the value of the resistor 14. For that reason,
Once the necessary output constant current is determined, the overall current consumption can be determined simply by setting the values of the resistors 11 and 14 without depending on the power supply voltage, and it is possible to easily reduce the current consumption.
次に、電源電圧の低下時の動作について説明す
る。第２図の従来回路の場合、電源電圧が低下
し、1.5V程度になると、第１及び第２ダイオー
ド２及び３に流れる電流が極度に小となる為、前
記第１及び第２ダイオード２及び３の順方向電圧
降下VDが小になり、I0＝VD／R1で定まる出力電流I0
が減少する。それに対し、第１図の実施例の場合
は、電源電圧（VCC）がVBE＋VCES（ただし、VCES
は第１トランジスタ７のコレクタ・エミツタ間飽
和電圧）に低下する迄、出力電流I0が略一定に保
たれる。VBE＝0.6V、VCES＝0.2Vとすれば、第１
図の定電流回路は、電源電圧が約0.8Vに低下す
る迄出力電流を一定に保つことが出来る。従つ
て、1.5Vの乾電池（補償電圧0.9V）１個で十分
に動作する定電流回路を提供出来る。 Next, the operation when the power supply voltage decreases will be explained. In the case of the conventional circuit shown in FIG. 2, when the power supply voltage decreases to about 1.5V, the current flowing through the first and second diodes 2 and 3 becomes extremely small. The forward voltage drop V D of 3 becomes small, and the output current I 0 determined by I 0 =V D /R 1 decreases. On the other hand, in the case of the embodiment shown in FIG. 1, the power supply voltage (V CC ) is V BE +V CES (however, V CES
The output current I 0 is kept substantially constant until it decreases to the collector-emitter saturation voltage of the first transistor 7. If V BE = 0.6V and V CES = 0.2V, the first
The constant current circuit shown in the figure can keep the output current constant until the power supply voltage drops to about 0.8V. Therefore, it is possible to provide a constant current circuit that operates satisfactorily with a single 1.5V dry battery (compensation voltage 0.9V).
第３図は、第１図の実施例（実線）と第２図の
従来回路例（一点鎖線）との特性を比較する為の
特性図である。一点鎖線で示される如く、従来の
定電流回路においては、電源電圧が1.5V以下に
なると、出力電流I0が急激に減少する。一方、本
考案に係る定電流回路は、電源電圧が0.8Vに低
下する迄定電流を発生し続ける。従つて、本考案
に依れば、電源電圧の低下時にも安定に一定の電
流を発生する定電流回路を提供出来る。 FIG. 3 is a characteristic diagram for comparing the characteristics of the embodiment shown in FIG. 1 (solid line) and the conventional circuit example shown in FIG. 2 (dotted chain line). As shown by the dashed line, in the conventional constant current circuit, when the power supply voltage becomes 1.5V or less, the output current I 0 decreases rapidly. On the other hand, the constant current circuit according to the present invention continues to generate a constant current until the power supply voltage drops to 0.8V. Therefore, according to the present invention, it is possible to provide a constant current circuit that stably generates a constant current even when the power supply voltage decreases.
(ト) 考案の効果
以上述べた如く、本考案に依れば、電源電圧の
低下時にも安定に定電流を発生する定電流回路を
提供出来る。また、本考案に依れば、消費電流の
少い定電流回路を提供出来る。更に本考案に依れ
ば、第１及び第２トランジスタのコレクタ・エミ
ツタ間電圧を等しく設定出来るので、アーリー効
果を相殺出来、IC化に適した定電流回路を提供
出来る。(g) Effects of the invention As described above, according to the invention, it is possible to provide a constant current circuit that stably generates a constant current even when the power supply voltage drops. Further, according to the present invention, a constant current circuit with low current consumption can be provided. Furthermore, according to the present invention, since the collector-emitter voltages of the first and second transistors can be set equally, the Early effect can be canceled out, and a constant current circuit suitable for IC implementation can be provided.
第１図は、本考案の一実施例を示す回路図、第
２図は従来の定電流回路を示す回路図、及び第３
図は本考案の説明に供する為の特性図である。
主な図番の説明、７，８，１２，１３……第
１、第２、第３、第４トランジスタ、９，１０…
…第１、第２シヨツトキーダイオード、１１，１
４……抵抗、１５……電流ミラー回路、１９……
定電流トランジスタ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional constant current circuit, and FIG.
The figure is a characteristic diagram for explaining the present invention. Explanation of main figure numbers, 7, 8, 12, 13...first, second, third, fourth transistors, 9, 10...
...First and second shot key diodes, 11,1
4...Resistor, 15 ...Current mirror circuit, 19...
Constant current transistor.
Claims (1)
第２トランジスタと、該第１及び第２トランジス
タの共通エミツタと電源との間に接続された抵抗
と、前記第１及び第２トランジスタの共通ベース
と電源との間に接続されたシヨツトキーダイオー
ドと、前記第１トランジスタのコレクタに接続さ
れたダイオード接続型の第３トランジスタと、該
第３トランジスタのコレクタ・エミツタ間に並列
接続された抵抗と、前記第３トランジスタとミラ
ー関係に接続されるとともに、コレクタが前記第
２トランジスタのコレクタに接続された第４トラ
ンジスタと、前記第２及び第４トランジスタのコ
レクタ電流の差電流を取り出す電流ミラー回路
と、該電流ミラー回路を構成するトランジスタと
ベース及びエミツタが共通接続され、コレクタが
前記第１及び第２トランジスタの共通ベースに接
続された定電流トランジスタから成り、前記電流
ミラー回路の出力端に定電流を発生する様にした
定電流回路。 first and second transistors whose bases and emitters are commonly connected; a resistor connected between the common emitters of the first and second transistors and a power source; and a common base and the power source of the first and second transistors. a Schottky diode connected between the first transistor, a diode-connected third transistor connected to the collector of the first transistor, and a resistor connected in parallel between the collector and emitter of the third transistor; a fourth transistor connected in a mirror relationship to a third transistor and having a collector connected to the collector of the second transistor; a current mirror circuit for extracting a difference current between the collector currents of the second and fourth transistors; A transistor forming a current mirror circuit includes a constant current transistor whose base and emitter are commonly connected, and whose collector is connected to the common base of the first and second transistors, and generates a constant current at the output terminal of the current mirror circuit. A constant current circuit designed to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15602284U JPH0512812Y2 (en) | 1984-10-16 | 1984-10-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15602284U JPH0512812Y2 (en) | 1984-10-16 | 1984-10-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170217U JPS6170217U (en) | 1986-05-14 |
| JPH0512812Y2 true JPH0512812Y2 (en) | 1993-04-05 |
Family
ID=30714037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15602284U Expired - Lifetime JPH0512812Y2 (en) | 1984-10-16 | 1984-10-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0512812Y2 (en) |
-
1984
- 1984-10-16 JP JP15602284U patent/JPH0512812Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6170217U (en) | 1986-05-14 |
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