JPH05129941A - Phase comparator - Google Patents
Phase comparatorInfo
- Publication number
- JPH05129941A JPH05129941A JP3291195A JP29119591A JPH05129941A JP H05129941 A JPH05129941 A JP H05129941A JP 3291195 A JP3291195 A JP 3291195A JP 29119591 A JP29119591 A JP 29119591A JP H05129941 A JPH05129941 A JP H05129941A
- Authority
- JP
- Japan
- Prior art keywords
- constant current
- diode bridge
- switching circuit
- semiconductor integrated
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、PLL回路などに使用
する位相比較器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator used in a PLL circuit or the like.
【0002】[0002]
【従来の技術】図2を用いて説明する。演算器1は3個
の差動アンプ8〜10と3個のカレントミラー11〜1
3及び電流値I1の電流源7で構成される掛算器で、入
力端子4,5の2信号の位相差は、出力端子6において
は,位相比較出力電流ieに変換される。2は電流スイ
ッチ回路で、MOSトランジスタ14で構成されてお
り、ゲート15の電圧がスレッショルド電圧より高いと
きのみ、ソース,ドレイン間が導通し、位相比較出力電
流ieが、後段のホールドコンデンサ16を充放電す
る。そして、ゲート15の電圧がスレッショルド電圧よ
り低いときは、MOSトランジスタ14はカットオフと
なり、演算器1の出力電流は、ホールドコンデンサ16
に伝達されず、ホールドコンデンサ16の端子電圧は保
持される。そしてこの端子電圧がVCO制御端子18に
伝達されVCO回路19のVCO発振周波数を制御す
る。2. Description of the Related Art A description will be given with reference to FIG. The arithmetic unit 1 includes three differential amplifiers 8 to 10 and three current mirrors 11 to 1
In the multiplier composed of 3 and the current source 7 having the current value I 1 , the phase difference between the two signals at the input terminals 4 and 5 is converted to the phase comparison output current ie at the output terminal 6. Reference numeral 2 denotes a current switch circuit, which is composed of a MOS transistor 14 and conducts between the source and the drain only when the voltage of the gate 15 is higher than the threshold voltage, and the phase comparison output current ie charges the hold capacitor 16 in the subsequent stage. To discharge. Then, when the voltage of the gate 15 is lower than the threshold voltage, the MOS transistor 14 is cut off, and the output current of the arithmetic unit 1 becomes equal to the hold capacitor 16
Is not transmitted to the hold capacitor 16 and the terminal voltage of the hold capacitor 16 is held. This terminal voltage is transmitted to the VCO control terminal 18 to control the VCO oscillation frequency of the VCO circuit 19.
【0003】[0003]
【発明が解決しようとする課題】このような回路をバイ
ポーラ半導体集積回路化しようとした場合、双方向(コ
ンデンサ16に対し充電方向にも、放電方向にも働く)
の電流スイッチ回路はMOSトランジスタを外付け部品
として用いていた。そうすると、バイポーラ半導体集積
回路に、位相比較出力端子6と、VOC発振周波数制御
端子18を別々に設ける必要があり、バイポーラ半導体
集積回路のピン数が増えてしまうという問題があった。
また、外付け部品としては、高価なMOSトランジスタ
を必要とするという問題も生じる。When such a circuit is to be made into a bipolar semiconductor integrated circuit, it is bidirectional (acts on both the charging direction and the discharging direction with respect to the capacitor 16).
The current switch circuit of 1 used a MOS transistor as an external component. Then, it is necessary to separately provide the phase comparison output terminal 6 and the VOC oscillation frequency control terminal 18 in the bipolar semiconductor integrated circuit, which causes a problem that the number of pins of the bipolar semiconductor integrated circuit increases.
Further, there is a problem that an expensive MOS transistor is required as an external component.
【0004】本発明は上記問題を解決するもので、ピン
数の少ないバイポーラ半導体集積回路化位相比較器の提
供を目的としている。The present invention solves the above problems, and an object thereof is to provide a bipolar semiconductor integrated circuit phase comparator having a small number of pins.
【0005】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するため、4個のダイオードによるダイオードブリッジ
と、2個の定電流源を備えた構成を有する。In order to achieve the above object, the present invention has a structure including a diode bridge formed of four diodes and two constant current sources.
【0006】[0006]
【作用】上記の構成をとることによって、外付け部品と
して高価なMOSトランジスタを不用にする。With the above structure, expensive MOS transistors are not required as external parts.
【0007】[0007]
【実施例】以下、本発明の一実施例の位相比較器を図1
を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A phase comparator according to an embodiment of the present invention will be described below with reference to FIG.
Will be described with reference to.
【0008】図2と同一機能を呈する素子には同一符号
を付与した。定電流源20,21の電流が、I0の場
合、演算器1の出力端子6からの位相比較出力電流ie
はダイオード22〜25で構成される平衡ブリッジ回路
の故に出力端子18からサンプルホールドコンデンサ1
6に流れる。コンデンサ16から放電する場合も全く同
様である。一方、定電流源20,21に電流が流れてい
ない場合には、ダイオードブリッジスイッチ回路は開放
状態となり、コンデンサ16の端子電圧は保持される。
このように、定電流源20,21に電流が流れている期
間は演算器の位相比較出力電流を後段のホールドコンデ
ンサ16に伝達し、定電流源20,21に電流が流れて
いない期間は、ホールドコンデンサ16の端子電圧を保
持することができる。Elements having the same functions as those in FIG. 2 are designated by the same reference numerals. When the currents of the constant current sources 20 and 21 are I 0 , the phase comparison output current ie from the output terminal 6 of the arithmetic unit 1
Is a balanced bridge circuit composed of diodes 22 to 25.
It flows to 6. The same applies when discharging from the capacitor 16. On the other hand, when no current flows in the constant current sources 20 and 21, the diode bridge switch circuit is in an open state and the terminal voltage of the capacitor 16 is held.
In this way, the phase comparison output current of the arithmetic unit is transmitted to the hold capacitor 16 in the subsequent stage while the current is flowing through the constant current sources 20 and 21, and the current is not flowing through the constant current sources 20 and 21 during the period. The terminal voltage of the hold capacitor 16 can be held.
【0009】このように本発明の実施例の位相比較器に
よれば、MOSトランジスタの代わりにダイオードブリ
ッジでスイッチ回路を構成してあるので、外付けMOS
トランジスタは不用となり、バイポーラ半導体集積回路
にした場合においてもピン数を減ずることができる。As described above, according to the phase comparator of the embodiment of the present invention, since the switch circuit is constituted by the diode bridge instead of the MOS transistor, the external MOS is provided.
Since the transistor is unnecessary, the number of pins can be reduced even when the bipolar semiconductor integrated circuit is used.
【0010】[0010]
【発明の効果】以上の実施例から明らかなように本発明
によれば、演算器の位相比較出力電流を所定期間のみ後
段のホールドコンデンサに伝達し、その他の期間は保持
する電流スイッチをMOSトランジスタを用いず、実現
できるのでバイポーラ半導体集積回路化した場合、外付
け部品として高価なMOSトランジスタを必要とせず、
また、半導体集積回路のピン数としてMOSトタンジス
タを外付け部品として用いた場合には2ピン必要だった
が、定電流源20,21はバイポーラ半導体集積回路で
実現可能であるためVCO制御端子18の1ピンですむ
位相比較器を提供できる。As is apparent from the above-described embodiments, according to the present invention, the current switch for transmitting the phase comparison output current of the arithmetic unit to the hold capacitor in the subsequent stage only for a predetermined period and holding it for the other period is a MOS transistor. Since it can be realized without using a bipolar semiconductor integrated circuit, an expensive MOS transistor is not required as an external component,
Further, when the MOS transistor was used as an external component as the number of pins of the semiconductor integrated circuit, two pins were required. However, since the constant current sources 20 and 21 can be realized by the bipolar semiconductor integrated circuit, the VCO control terminal 18 has We can provide a phase comparator that requires only one pin.
【図1】本発明の一実施例の位相比較器およびVCO回
路を示す回路図FIG. 1 is a circuit diagram showing a phase comparator and a VCO circuit according to an embodiment of the present invention.
【図2】従来の位相比較器およびVCO回路を示す回路
図FIG. 2 is a circuit diagram showing a conventional phase comparator and VCO circuit.
1 演算器(掛算器) 16 ホールドコンデンサ 20,21 電流源 22,23,24,25 ダイオード 1 calculator (multiplier) 16 hold capacitor 20,21 current source 22,23,24,25 diode
Claims (1)
ホールドコンデンサの間に接続されたダイオードブリッ
ジスイッチ回路と、前記ダイオードブリッジスイッチ回
路に定電流を流すための電流源を備え、所定期間のみ前
記電流源は定電流を流し、その他の期間は定電流を遮断
するようにした位相比較器。1. A multiplier, a diode bridge switch circuit connected between a phase comparison output current terminal of the multiplier and a hold capacitor, and a current source for supplying a constant current to the diode bridge switch circuit. A phase comparator in which the current source supplies a constant current and cuts off the constant current during other periods.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3291195A JPH05129941A (en) | 1991-11-07 | 1991-11-07 | Phase comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3291195A JPH05129941A (en) | 1991-11-07 | 1991-11-07 | Phase comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129941A true JPH05129941A (en) | 1993-05-25 |
Family
ID=17765691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3291195A Pending JPH05129941A (en) | 1991-11-07 | 1991-11-07 | Phase comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129941A (en) |
-
1991
- 1991-11-07 JP JP3291195A patent/JPH05129941A/en active Pending
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